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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define i64 @test_Pr_wide_scalar_simple(i64 noundef %0) nounwind {6; CHECK-LABEL: test_Pr_wide_scalar_simple:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: #APP9; CHECK-NEXT: # a2 <- a010; CHECK-NEXT: #NO_APP11; CHECK-NEXT: mv a0, a212; CHECK-NEXT: mv a1, a313; CHECK-NEXT: ret14entry:15 %1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %0)16 ret i64 %117}18 19define i32 @test_Pr_wide_scalar_with_ops(i32 noundef %0) nounwind {20; CHECK-LABEL: test_Pr_wide_scalar_with_ops:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: mv a1, a023; CHECK-NEXT: #APP24; CHECK-NEXT: # a2 <- a025; CHECK-NEXT: #NO_APP26; CHECK-NEXT: or a0, a2, a327; CHECK-NEXT: ret28entry:29 %1 = zext i32 %0 to i6430 %2 = shl i64 %1, 3231 %3 = or i64 %1, %232 %4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %3)33 %5 = trunc i64 %4 to i3234 %6 = lshr i64 %4, 3235 %7 = trunc i64 %6 to i3236 %8 = or i32 %5, %737 ret i32 %838}39 40define i64 @test_Pr_wide_scalar_inout(ptr %0, i64 noundef %1) nounwind {41; CHECK-LABEL: test_Pr_wide_scalar_inout:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: addi sp, sp, -1644; CHECK-NEXT: mv a3, a245; CHECK-NEXT: sw a0, 12(sp)46; CHECK-NEXT: mv a2, a147; CHECK-NEXT: sw a1, 0(sp)48; CHECK-NEXT: sw a3, 4(sp)49; CHECK-NEXT: #APP50; CHECK-NEXT: # a0; a251; CHECK-NEXT: #NO_APP52; CHECK-NEXT: sw a0, 12(sp)53; CHECK-NEXT: sw a2, 0(sp)54; CHECK-NEXT: sw a3, 4(sp)55; CHECK-NEXT: mv a0, a256; CHECK-NEXT: mv a1, a357; CHECK-NEXT: addi sp, sp, 1658; CHECK-NEXT: ret59entry:60 %2 = alloca ptr, align 461 %3 = alloca i64, align 862 store ptr %0, ptr %2, align 463 store i64 %1, ptr %3, align 864 %4 = load ptr, ptr %2, align 465 %5 = load i64, ptr %3, align 866 %6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=R,0,1"(ptr %4, i64 %5)67 %7 = extractvalue { ptr, i64} %6, 068 %8 = extractvalue { ptr, i64 } %6, 169 store ptr %7, ptr %2, align 470 store i64 %8, ptr %3, align 871 %9 = load i64, ptr %3, align 872 ret i64 %973}74 75define i64 @test_cR_wide_scalar_simple(i64 noundef %0) nounwind {76; CHECK-LABEL: test_cR_wide_scalar_simple:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: #APP79; CHECK-NEXT: # a2 <- a080; CHECK-NEXT: #NO_APP81; CHECK-NEXT: mv a0, a282; CHECK-NEXT: mv a1, a383; CHECK-NEXT: ret84entry:85 %1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i64 %0)86 ret i64 %187}88 89define i32 @test_cR_wide_scalar_with_ops(i32 noundef %0) nounwind {90; CHECK-LABEL: test_cR_wide_scalar_with_ops:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: mv a1, a093; CHECK-NEXT: #APP94; CHECK-NEXT: # a2 <- a095; CHECK-NEXT: #NO_APP96; CHECK-NEXT: or a0, a2, a397; CHECK-NEXT: ret98entry:99 %1 = zext i32 %0 to i64100 %2 = shl i64 %1, 32101 %3 = or i64 %1, %2102 %4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i64 %3)103 %5 = trunc i64 %4 to i32104 %6 = lshr i64 %4, 32105 %7 = trunc i64 %6 to i32106 %8 = or i32 %5, %7107 ret i32 %8108}109 110define i64 @test_cR_wide_scalar_inout(ptr %0, i64 noundef %1) nounwind {111; CHECK-LABEL: test_cR_wide_scalar_inout:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: addi sp, sp, -16114; CHECK-NEXT: mv a3, a2115; CHECK-NEXT: sw a0, 12(sp)116; CHECK-NEXT: mv a2, a1117; CHECK-NEXT: sw a1, 0(sp)118; CHECK-NEXT: sw a3, 4(sp)119; CHECK-NEXT: #APP120; CHECK-NEXT: # a0; a2121; CHECK-NEXT: #NO_APP122; CHECK-NEXT: sw a0, 12(sp)123; CHECK-NEXT: sw a2, 0(sp)124; CHECK-NEXT: sw a3, 4(sp)125; CHECK-NEXT: mv a0, a2126; CHECK-NEXT: mv a1, a3127; CHECK-NEXT: addi sp, sp, 16128; CHECK-NEXT: ret129entry:130 %2 = alloca ptr, align 4131 %3 = alloca i64, align 8132 store ptr %0, ptr %2, align 4133 store i64 %1, ptr %3, align 8134 %4 = load ptr, ptr %2, align 4135 %5 = load i64, ptr %3, align 8136 %6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=^cR,0,1"(ptr %4, i64 %5)137 %7 = extractvalue { ptr, i64} %6, 0138 %8 = extractvalue { ptr, i64 } %6, 1139 store ptr %7, ptr %2, align 4140 store i64 %8, ptr %3, align 8141 %9 = load i64, ptr %3, align 8142 ret i64 %9143}144