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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64I %s6 7; This file provides a simple test check of half operations for8; RV32I and RV64I. This is primarily intended to ensure that custom9; legalisation or DAG combines aren't incorrectly triggered when the Zfh10; extension isn't enabled.11 12define half @half_test(half %a, half %b) nounwind {13; RV32I-LABEL: half_test:14; RV32I: # %bb.0:15; RV32I-NEXT: addi sp, sp, -1616; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill17; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill18; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill19; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill20; RV32I-NEXT: mv s0, a121; RV32I-NEXT: lui a1, 1622; RV32I-NEXT: addi s2, a1, -123; RV32I-NEXT: and a0, a0, s224; RV32I-NEXT: call __extendhfsf225; RV32I-NEXT: mv s1, a026; RV32I-NEXT: and a0, s0, s227; RV32I-NEXT: call __extendhfsf228; RV32I-NEXT: mv s0, a029; RV32I-NEXT: mv a0, s130; RV32I-NEXT: mv a1, s031; RV32I-NEXT: call __addsf332; RV32I-NEXT: call __truncsfhf233; RV32I-NEXT: and a0, a0, s234; RV32I-NEXT: call __extendhfsf235; RV32I-NEXT: mv a1, s036; RV32I-NEXT: call __divsf337; RV32I-NEXT: call __truncsfhf238; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload39; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload40; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload41; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload42; RV32I-NEXT: addi sp, sp, 1643; RV32I-NEXT: ret44;45; RV64I-LABEL: half_test:46; RV64I: # %bb.0:47; RV64I-NEXT: addi sp, sp, -3248; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill49; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill50; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill51; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill52; RV64I-NEXT: mv s0, a153; RV64I-NEXT: lui a1, 1654; RV64I-NEXT: addi s2, a1, -155; RV64I-NEXT: and a0, a0, s256; RV64I-NEXT: call __extendhfsf257; RV64I-NEXT: mv s1, a058; RV64I-NEXT: and a0, s0, s259; RV64I-NEXT: call __extendhfsf260; RV64I-NEXT: mv s0, a061; RV64I-NEXT: mv a0, s162; RV64I-NEXT: mv a1, s063; RV64I-NEXT: call __addsf364; RV64I-NEXT: call __truncsfhf265; RV64I-NEXT: and a0, a0, s266; RV64I-NEXT: call __extendhfsf267; RV64I-NEXT: mv a1, s068; RV64I-NEXT: call __divsf369; RV64I-NEXT: call __truncsfhf270; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload71; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload72; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload73; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload74; RV64I-NEXT: addi sp, sp, 3275; RV64I-NEXT: ret76 %1 = fadd half %a, %b77 %2 = fdiv half %1, %b78 ret half %279}80