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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define i32 @ctlz_i32(i32 %a) nounwind {6; CHECK-LABEL: ctlz_i32:7; CHECK: # %bb.0:8; CHECK-NEXT: clz a0, a09; CHECK-NEXT: ret10 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)11 ret i32 %112}13 14define i64 @ctlz_i64(i64 %a) nounwind {15; CHECK-LABEL: ctlz_i64:16; CHECK: # %bb.0:17; CHECK-NEXT: bnez a1, .LBB1_218; CHECK-NEXT: # %bb.1:19; CHECK-NEXT: clz a0, a020; CHECK-NEXT: addi a0, a0, 3221; CHECK-NEXT: li a1, 022; CHECK-NEXT: ret23; CHECK-NEXT: .LBB1_2:24; CHECK-NEXT: clz a0, a125; CHECK-NEXT: li a1, 026; CHECK-NEXT: ret27 %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)28 ret i64 %129}30 31define i32 @cttz_i32(i32 %a) nounwind {32; CHECK-LABEL: cttz_i32:33; CHECK: # %bb.0:34; CHECK-NEXT: beqz a0, .LBB2_235; CHECK-NEXT: # %bb.1: # %cond.false36; CHECK-NEXT: addi a1, a0, -137; CHECK-NEXT: not a0, a038; CHECK-NEXT: and a0, a0, a139; CHECK-NEXT: clz a0, a040; CHECK-NEXT: li a1, 3241; CHECK-NEXT: sub a0, a1, a042; CHECK-NEXT: ret43; CHECK-NEXT: .LBB2_2:44; CHECK-NEXT: li a0, 3245; CHECK-NEXT: ret46 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)47 ret i32 %148}49 50define i64 @cttz_i64(i64 %a) nounwind {51; CHECK-LABEL: cttz_i64:52; CHECK: # %bb.0:53; CHECK-NEXT: or a2, a0, a154; CHECK-NEXT: beqz a2, .LBB3_355; CHECK-NEXT: # %bb.1: # %cond.false56; CHECK-NEXT: bnez a0, .LBB3_457; CHECK-NEXT: # %bb.2: # %cond.false58; CHECK-NEXT: addi a0, a1, -159; CHECK-NEXT: not a1, a160; CHECK-NEXT: and a0, a1, a061; CHECK-NEXT: clz a0, a062; CHECK-NEXT: li a1, 6463; CHECK-NEXT: j .LBB3_564; CHECK-NEXT: .LBB3_3:65; CHECK-NEXT: li a1, 066; CHECK-NEXT: li a0, 6467; CHECK-NEXT: ret68; CHECK-NEXT: .LBB3_4:69; CHECK-NEXT: addi a1, a0, -170; CHECK-NEXT: not a0, a071; CHECK-NEXT: and a0, a0, a172; CHECK-NEXT: clz a0, a073; CHECK-NEXT: li a1, 3274; CHECK-NEXT: .LBB3_5: # %cond.false75; CHECK-NEXT: sub a0, a1, a076; CHECK-NEXT: li a1, 077; CHECK-NEXT: ret78 %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)79 ret i64 %180}81 82define i32 @sextb_i32(i32 %a) nounwind {83; CHECK-LABEL: sextb_i32:84; CHECK: # %bb.0:85; CHECK-NEXT: sext.b a0, a086; CHECK-NEXT: ret87 %shl = shl i32 %a, 2488 %shr = ashr exact i32 %shl, 2489 ret i32 %shr90}91 92define i64 @sextb_i64(i64 %a) nounwind {93; CHECK-LABEL: sextb_i64:94; CHECK: # %bb.0:95; CHECK-NEXT: sext.b a0, a096; CHECK-NEXT: srai a1, a0, 3197; CHECK-NEXT: ret98 %shl = shl i64 %a, 5699 %shr = ashr exact i64 %shl, 56100 ret i64 %shr101}102 103define i32 @sexth_i32(i32 %a) nounwind {104; CHECK-LABEL: sexth_i32:105; CHECK: # %bb.0:106; CHECK-NEXT: sext.h a0, a0107; CHECK-NEXT: ret108 %shl = shl i32 %a, 16109 %shr = ashr exact i32 %shl, 16110 ret i32 %shr111}112 113define i64 @sexth_i64(i64 %a) nounwind {114; CHECK-LABEL: sexth_i64:115; CHECK: # %bb.0:116; CHECK-NEXT: sext.h a0, a0117; CHECK-NEXT: srai a1, a0, 31118; CHECK-NEXT: ret119 %shl = shl i64 %a, 48120 %shr = ashr exact i64 %shl, 48121 ret i64 %shr122}123 124define i32 @min_i32(i32 %a, i32 %b) nounwind {125; CHECK-LABEL: min_i32:126; CHECK: # %bb.0:127; CHECK-NEXT: min a0, a0, a1128; CHECK-NEXT: ret129 %cmp = icmp slt i32 %a, %b130 %cond = select i1 %cmp, i32 %a, i32 %b131 ret i32 %cond132}133 134; As we are not matching directly i64 code patterns on RV32 some i64 patterns135; don't have yet any matching bit manipulation instructions on RV32.136; This test is presented here in case future expansions of the Bitmanip137; extensions introduce instructions suitable for this pattern.138 139define i64 @min_i64(i64 %a, i64 %b) nounwind {140; CHECK-LABEL: min_i64:141; CHECK: # %bb.0:142; CHECK-NEXT: beq a1, a3, .LBB9_2143; CHECK-NEXT: # %bb.1:144; CHECK-NEXT: slt a4, a1, a3145; CHECK-NEXT: beqz a4, .LBB9_3146; CHECK-NEXT: j .LBB9_4147; CHECK-NEXT: .LBB9_2:148; CHECK-NEXT: sltu a4, a0, a2149; CHECK-NEXT: bnez a4, .LBB9_4150; CHECK-NEXT: .LBB9_3:151; CHECK-NEXT: mv a0, a2152; CHECK-NEXT: mv a1, a3153; CHECK-NEXT: .LBB9_4:154; CHECK-NEXT: ret155 %cmp = icmp slt i64 %a, %b156 %cond = select i1 %cmp, i64 %a, i64 %b157 ret i64 %cond158}159 160define i32 @max_i32(i32 %a, i32 %b) nounwind {161; CHECK-LABEL: max_i32:162; CHECK: # %bb.0:163; CHECK-NEXT: max a0, a0, a1164; CHECK-NEXT: ret165 %cmp = icmp sgt i32 %a, %b166 %cond = select i1 %cmp, i32 %a, i32 %b167 ret i32 %cond168}169 170; As we are not matching directly i64 code patterns on RV32 some i64 patterns171; don't have yet any matching bit manipulation instructions on RV32.172; This test is presented here in case future expansions of the Bitmanip173; extensions introduce instructions suitable for this pattern.174 175define i64 @max_i64(i64 %a, i64 %b) nounwind {176; CHECK-LABEL: max_i64:177; CHECK: # %bb.0:178; CHECK-NEXT: beq a1, a3, .LBB11_2179; CHECK-NEXT: # %bb.1:180; CHECK-NEXT: slt a4, a3, a1181; CHECK-NEXT: beqz a4, .LBB11_3182; CHECK-NEXT: j .LBB11_4183; CHECK-NEXT: .LBB11_2:184; CHECK-NEXT: sltu a4, a2, a0185; CHECK-NEXT: bnez a4, .LBB11_4186; CHECK-NEXT: .LBB11_3:187; CHECK-NEXT: mv a0, a2188; CHECK-NEXT: mv a1, a3189; CHECK-NEXT: .LBB11_4:190; CHECK-NEXT: ret191 %cmp = icmp sgt i64 %a, %b192 %cond = select i1 %cmp, i64 %a, i64 %b193 ret i64 %cond194}195 196define i32 @minu_i32(i32 %a, i32 %b) nounwind {197; CHECK-LABEL: minu_i32:198; CHECK: # %bb.0:199; CHECK-NEXT: minu a0, a0, a1200; CHECK-NEXT: ret201 %cmp = icmp ult i32 %a, %b202 %cond = select i1 %cmp, i32 %a, i32 %b203 ret i32 %cond204}205 206; As we are not matching directly i64 code patterns on RV32 some i64 patterns207; don't have yet any matching bit manipulation instructions on RV32.208; This test is presented here in case future expansions of the Bitmanip209; extensions introduce instructions suitable for this pattern.210 211define i64 @minu_i64(i64 %a, i64 %b) nounwind {212; CHECK-LABEL: minu_i64:213; CHECK: # %bb.0:214; CHECK-NEXT: beq a1, a3, .LBB13_2215; CHECK-NEXT: # %bb.1:216; CHECK-NEXT: sltu a4, a1, a3217; CHECK-NEXT: beqz a4, .LBB13_3218; CHECK-NEXT: j .LBB13_4219; CHECK-NEXT: .LBB13_2:220; CHECK-NEXT: sltu a4, a0, a2221; CHECK-NEXT: bnez a4, .LBB13_4222; CHECK-NEXT: .LBB13_3:223; CHECK-NEXT: mv a0, a2224; CHECK-NEXT: mv a1, a3225; CHECK-NEXT: .LBB13_4:226; CHECK-NEXT: ret227 %cmp = icmp ult i64 %a, %b228 %cond = select i1 %cmp, i64 %a, i64 %b229 ret i64 %cond230}231 232define i32 @maxu_i32(i32 %a, i32 %b) nounwind {233; CHECK-LABEL: maxu_i32:234; CHECK: # %bb.0:235; CHECK-NEXT: maxu a0, a0, a1236; CHECK-NEXT: ret237 %cmp = icmp ugt i32 %a, %b238 %cond = select i1 %cmp, i32 %a, i32 %b239 ret i32 %cond240}241 242; As we are not matching directly i64 code patterns on RV32 some i64 patterns243; don't have yet any matching bit manipulation instructions on RV32.244; This test is presented here in case future expansions of the Bitmanip245; extensions introduce instructions suitable for this pattern.246 247define i64 @maxu_i64(i64 %a, i64 %b) nounwind {248; CHECK-LABEL: maxu_i64:249; CHECK: # %bb.0:250; CHECK-NEXT: beq a1, a3, .LBB15_2251; CHECK-NEXT: # %bb.1:252; CHECK-NEXT: sltu a4, a3, a1253; CHECK-NEXT: beqz a4, .LBB15_3254; CHECK-NEXT: j .LBB15_4255; CHECK-NEXT: .LBB15_2:256; CHECK-NEXT: sltu a4, a2, a0257; CHECK-NEXT: bnez a4, .LBB15_4258; CHECK-NEXT: .LBB15_3:259; CHECK-NEXT: mv a0, a2260; CHECK-NEXT: mv a1, a3261; CHECK-NEXT: .LBB15_4:262; CHECK-NEXT: ret263 %cmp = icmp ugt i64 %a, %b264 %cond = select i1 %cmp, i64 %a, i64 %b265 ret i64 %cond266}267 268define i32 @abs_i32(i32 %x) {269; CHECK-LABEL: abs_i32:270; CHECK: # %bb.0:271; CHECK-NEXT: abs a0, a0272; CHECK-NEXT: ret273 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)274 ret i32 %abs275}276 277define i64 @abs_i64(i64 %x) {278; CHECK-LABEL: abs_i64:279; CHECK: # %bb.0:280; CHECK-NEXT: bgez a1, .LBB17_2281; CHECK-NEXT: # %bb.1:282; CHECK-NEXT: snez a2, a0283; CHECK-NEXT: neg a0, a0284; CHECK-NEXT: neg a1, a1285; CHECK-NEXT: sub a1, a1, a2286; CHECK-NEXT: .LBB17_2:287; CHECK-NEXT: ret288 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)289 ret i64 %abs290}291 292define i32 @zexth_i32(i32 %a) nounwind {293; CHECK-LABEL: zexth_i32:294; CHECK: # %bb.0:295; CHECK-NEXT: slli a0, a0, 16296; CHECK-NEXT: srli a0, a0, 16297; CHECK-NEXT: ret298 %and = and i32 %a, 65535299 ret i32 %and300}301 302define i64 @zexth_i64(i64 %a) nounwind {303; CHECK-LABEL: zexth_i64:304; CHECK: # %bb.0:305; CHECK-NEXT: slli a0, a0, 16306; CHECK-NEXT: srli a0, a0, 16307; CHECK-NEXT: li a1, 0308; CHECK-NEXT: ret309 %and = and i64 %a, 65535310 ret i64 %and311}312 313define i32 @bswap_i32(i32 %a) nounwind {314; CHECK-LABEL: bswap_i32:315; CHECK: # %bb.0:316; CHECK-NEXT: rev8 a0, a0317; CHECK-NEXT: ret318 %1 = tail call i32 @llvm.bswap.i32(i32 %a)319 ret i32 %1320}321 322define i64 @bswap_i64(i64 %a) {323; CHECK-LABEL: bswap_i64:324; CHECK: # %bb.0:325; CHECK-NEXT: rev8 a2, a1326; CHECK-NEXT: rev8 a1, a0327; CHECK-NEXT: mv a0, a2328; CHECK-NEXT: ret329 %1 = call i64 @llvm.bswap.i64(i64 %a)330 ret i64 %1331}332 333define i32 @srai_slli(i16 signext %0) {334; CHECK-LABEL: srai_slli:335; CHECK: # %bb.0:336; CHECK-NEXT: slli a0, a0, 25337; CHECK-NEXT: srai a0, a0, 31338; CHECK-NEXT: ret339 %2 = shl i16 %0, 9340 %sext = ashr i16 %2, 15341 %3 = sext i16 %sext to i32342 ret i32 %3343}344 345define i32 @srai_slli2(i16 signext %0) {346; CHECK-LABEL: srai_slli2:347; CHECK: # %bb.0:348; CHECK-NEXT: slli a0, a0, 25349; CHECK-NEXT: srai a0, a0, 30350; CHECK-NEXT: ret351 %2 = shl i16 %0, 9352 %sext = ashr i16 %2, 14353 %3 = sext i16 %sext to i32354 ret i32 %3355}356define i8 @sub_if_uge_i8(i8 %x, i8 %y) {357; CHECK-LABEL: sub_if_uge_i8:358; CHECK: # %bb.0:359; CHECK-NEXT: zext.b a2, a0360; CHECK-NEXT: sub a0, a0, a1361; CHECK-NEXT: zext.b a0, a0362; CHECK-NEXT: minu a0, a2, a0363; CHECK-NEXT: ret364 %cmp = icmp ult i8 %x, %y365 %select = select i1 %cmp, i8 0, i8 %y366 %sub = sub nuw i8 %x, %select367 ret i8 %sub368}369 370define i16 @sub_if_uge_i16(i16 %x, i16 %y) {371; CHECK-LABEL: sub_if_uge_i16:372; CHECK: # %bb.0:373; CHECK-NEXT: lui a2, 16374; CHECK-NEXT: sub a1, a0, a1375; CHECK-NEXT: addi a2, a2, -1376; CHECK-NEXT: and a0, a0, a2377; CHECK-NEXT: and a1, a1, a2378; CHECK-NEXT: minu a0, a0, a1379; CHECK-NEXT: ret380 %cmp = icmp ult i16 %x, %y381 %select = select i1 %cmp, i16 0, i16 %y382 %sub = sub nuw i16 %x, %select383 ret i16 %sub384}385 386define i32 @sub_if_uge_i32(i32 %x, i32 %y) {387; CHECK-LABEL: sub_if_uge_i32:388; CHECK: # %bb.0:389; CHECK-NEXT: sub a1, a0, a1390; CHECK-NEXT: minu a0, a0, a1391; CHECK-NEXT: ret392 %cmp = icmp ult i32 %x, %y393 %select = select i1 %cmp, i32 0, i32 %y394 %sub = sub nuw i32 %x, %select395 ret i32 %sub396}397 398define i64 @sub_if_uge_i64(i64 %x, i64 %y) {399; CHECK-LABEL: sub_if_uge_i64:400; CHECK: # %bb.0:401; CHECK-NEXT: beq a1, a3, .LBB27_2402; CHECK-NEXT: # %bb.1:403; CHECK-NEXT: sltu a4, a1, a3404; CHECK-NEXT: j .LBB27_3405; CHECK-NEXT: .LBB27_2:406; CHECK-NEXT: sltu a4, a0, a2407; CHECK-NEXT: .LBB27_3:408; CHECK-NEXT: addi a4, a4, -1409; CHECK-NEXT: and a3, a4, a3410; CHECK-NEXT: and a2, a4, a2411; CHECK-NEXT: sltu a4, a0, a2412; CHECK-NEXT: sub a1, a1, a3413; CHECK-NEXT: sub a1, a1, a4414; CHECK-NEXT: sub a0, a0, a2415; CHECK-NEXT: ret416 %cmp = icmp ult i64 %x, %y417 %select = select i1 %cmp, i64 0, i64 %y418 %sub = sub nuw i64 %x, %select419 ret i64 %sub420}421 422define i128 @sub_if_uge_i128(i128 %x, i128 %y) {423; CHECK-LABEL: sub_if_uge_i128:424; CHECK: # %bb.0:425; CHECK-NEXT: lw a3, 4(a1)426; CHECK-NEXT: lw a4, 8(a1)427; CHECK-NEXT: lw a5, 12(a1)428; CHECK-NEXT: lw a6, 4(a2)429; CHECK-NEXT: lw t0, 12(a2)430; CHECK-NEXT: lw a7, 8(a2)431; CHECK-NEXT: beq a5, t0, .LBB28_2432; CHECK-NEXT: # %bb.1:433; CHECK-NEXT: sltu t1, a5, t0434; CHECK-NEXT: j .LBB28_3435; CHECK-NEXT: .LBB28_2:436; CHECK-NEXT: sltu t1, a4, a7437; CHECK-NEXT: .LBB28_3:438; CHECK-NEXT: lw a1, 0(a1)439; CHECK-NEXT: lw a2, 0(a2)440; CHECK-NEXT: beq a3, a6, .LBB28_5441; CHECK-NEXT: # %bb.4:442; CHECK-NEXT: sltu t2, a3, a6443; CHECK-NEXT: j .LBB28_6444; CHECK-NEXT: .LBB28_5:445; CHECK-NEXT: sltu t2, a1, a2446; CHECK-NEXT: .LBB28_6:447; CHECK-NEXT: xor t3, a5, t0448; CHECK-NEXT: xor t4, a4, a7449; CHECK-NEXT: or t3, t4, t3450; CHECK-NEXT: beqz t3, .LBB28_8451; CHECK-NEXT: # %bb.7:452; CHECK-NEXT: mv t2, t1453; CHECK-NEXT: .LBB28_8:454; CHECK-NEXT: addi t3, t2, -1455; CHECK-NEXT: and t2, t3, t0456; CHECK-NEXT: and t0, t3, a2457; CHECK-NEXT: and t1, t3, a6458; CHECK-NEXT: sltu a2, a1, t0459; CHECK-NEXT: and a7, t3, a7460; CHECK-NEXT: mv a6, a2461; CHECK-NEXT: beq a3, t1, .LBB28_10462; CHECK-NEXT: # %bb.9:463; CHECK-NEXT: sltu a6, a3, t1464; CHECK-NEXT: .LBB28_10:465; CHECK-NEXT: sub t3, a4, a7466; CHECK-NEXT: sltu a4, a4, a7467; CHECK-NEXT: sub a5, a5, t2468; CHECK-NEXT: sub a3, a3, t1469; CHECK-NEXT: sub a1, a1, t0470; CHECK-NEXT: sltu a7, t3, a6471; CHECK-NEXT: sub a5, a5, a4472; CHECK-NEXT: sub a4, t3, a6473; CHECK-NEXT: sub a3, a3, a2474; CHECK-NEXT: sub a2, a5, a7475; CHECK-NEXT: sw a1, 0(a0)476; CHECK-NEXT: sw a3, 4(a0)477; CHECK-NEXT: sw a4, 8(a0)478; CHECK-NEXT: sw a2, 12(a0)479; CHECK-NEXT: ret480 %cmp = icmp ult i128 %x, %y481 %select = select i1 %cmp, i128 0, i128 %y482 %sub = sub nuw i128 %x, %select483 ret i128 %sub484}485 486define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {487; CHECK-LABEL: sub_if_uge_multiuse_select_i32:488; CHECK: # %bb.0:489; CHECK-NEXT: sltu a2, a0, a1490; CHECK-NEXT: addi a2, a2, -1491; CHECK-NEXT: and a1, a2, a1492; CHECK-NEXT: sub a0, a0, a1493; CHECK-NEXT: sll a0, a0, a1494; CHECK-NEXT: ret495 %cmp = icmp ult i32 %x, %y496 %select = select i1 %cmp, i32 0, i32 %y497 %sub = sub nuw i32 %x, %select498 %shl = shl i32 %sub, %select499 ret i32 %shl500}501 502define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {503; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:504; CHECK: # %bb.0:505; CHECK-NEXT: sub a2, a0, a1506; CHECK-NEXT: minu a2, a0, a2507; CHECK-NEXT: bltu a0, a1, .LBB30_2508; CHECK-NEXT: # %bb.1:509; CHECK-NEXT: li a0, 4510; CHECK-NEXT: sll a0, a2, a0511; CHECK-NEXT: ret512; CHECK-NEXT: .LBB30_2:513; CHECK-NEXT: li a0, 2514; CHECK-NEXT: sll a0, a2, a0515; CHECK-NEXT: ret516 %cmp = icmp ult i32 %x, %y517 %select = select i1 %cmp, i32 0, i32 %y518 %sub = sub nuw i32 %x, %select519 %select2 = select i1 %cmp, i32 2, i32 4520 %shl = shl i32 %sub, %select2521 ret i32 %shl522}523 524define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) {525; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:526; CHECK: # %bb.0:527; CHECK-NEXT: sltu a3, a0, a1528; CHECK-NEXT: sub a1, a0, a1529; CHECK-NEXT: xori a3, a3, 1530; CHECK-NEXT: minu a0, a0, a1531; CHECK-NEXT: sw a3, 0(a2)532; CHECK-NEXT: ret533 %cmp = icmp uge i32 %x, %y534 %conv = zext i1 %cmp to i32535 store i32 %conv, ptr %z, align 4536 %select = select i1 %cmp, i32 %y, i32 0537 %sub = sub nuw i32 %x, %select538 ret i32 %sub539}540 541define i8 @sub_if_uge_C_i8(i8 zeroext %x) {542; CHECK-LABEL: sub_if_uge_C_i8:543; CHECK: # %bb.0:544; CHECK-NEXT: addi a1, a0, -13545; CHECK-NEXT: zext.b a1, a1546; CHECK-NEXT: minu a0, a1, a0547; CHECK-NEXT: ret548 %cmp = icmp ugt i8 %x, 12549 %sub = add i8 %x, -13550 %conv4 = select i1 %cmp, i8 %sub, i8 %x551 ret i8 %conv4552}553 554define i16 @sub_if_uge_C_i16(i16 zeroext %x) {555; CHECK-LABEL: sub_if_uge_C_i16:556; CHECK: # %bb.0:557; CHECK-NEXT: addi a1, a0, -251558; CHECK-NEXT: slli a1, a1, 16559; CHECK-NEXT: srli a1, a1, 16560; CHECK-NEXT: minu a0, a1, a0561; CHECK-NEXT: ret562 %cmp = icmp ugt i16 %x, 250563 %sub = add i16 %x, -251564 %conv4 = select i1 %cmp, i16 %sub, i16 %x565 ret i16 %conv4566}567 568define i32 @sub_if_uge_C_i32(i32 signext %x) {569; CHECK-LABEL: sub_if_uge_C_i32:570; CHECK: # %bb.0:571; CHECK-NEXT: lui a1, 1048560572; CHECK-NEXT: addi a1, a1, 15573; CHECK-NEXT: add a1, a0, a1574; CHECK-NEXT: minu a0, a1, a0575; CHECK-NEXT: ret576 %cmp = icmp ugt i32 %x, 65520577 %sub = add i32 %x, -65521578 %cond = select i1 %cmp, i32 %sub, i32 %x579 ret i32 %cond580}581 582define i64 @sub_if_uge_C_i64(i64 %x) {583; CHECK-LABEL: sub_if_uge_C_i64:584; CHECK: # %bb.0:585; CHECK-NEXT: li a2, 1586; CHECK-NEXT: beq a1, a2, .LBB35_2587; CHECK-NEXT: # %bb.1:588; CHECK-NEXT: sltiu a2, a1, 2589; CHECK-NEXT: xori a2, a2, 1590; CHECK-NEXT: j .LBB35_3591; CHECK-NEXT: .LBB35_2:592; CHECK-NEXT: lui a2, 172127593; CHECK-NEXT: addi a2, a2, 511594; CHECK-NEXT: sltu a2, a2, a0595; CHECK-NEXT: .LBB35_3:596; CHECK-NEXT: neg a2, a2597; CHECK-NEXT: andi a3, a2, -2598; CHECK-NEXT: add a1, a1, a3599; CHECK-NEXT: lui a3, 876449600; CHECK-NEXT: addi a3, a3, -512601; CHECK-NEXT: and a2, a2, a3602; CHECK-NEXT: add a2, a0, a2603; CHECK-NEXT: sltu a0, a2, a0604; CHECK-NEXT: add a1, a1, a0605; CHECK-NEXT: mv a0, a2606; CHECK-NEXT: ret607 %cmp = icmp ugt i64 %x, 4999999999608 %sub = add i64 %x, -5000000000609 %cond = select i1 %cmp, i64 %sub, i64 %x610 ret i64 %cond611}612 613define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {614; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:615; CHECK: # %bb.0:616; CHECK-NEXT: lui a2, 16617; CHECK-NEXT: lui a3, 1048560618; CHECK-NEXT: addi a2, a2, -16619; CHECK-NEXT: addi a3, a3, 15620; CHECK-NEXT: sltu a2, a2, a0621; CHECK-NEXT: add a3, a0, a3622; CHECK-NEXT: minu a0, a3, a0623; CHECK-NEXT: sw a2, 0(a1)624; CHECK-NEXT: ret625 %cmp = icmp ugt i32 %x, 65520626 %conv = zext i1 %cmp to i32627 store i32 %conv, ptr %z, align 4628 %sub = add i32 %x, -65521629 %cond = select i1 %cmp, i32 %sub, i32 %x630 ret i32 %cond631}632 633define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {634; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:635; CHECK: # %bb.0:636; CHECK-NEXT: lui a2, 1048560637; CHECK-NEXT: addi a2, a2, 15638; CHECK-NEXT: add a2, a0, a2639; CHECK-NEXT: minu a0, a2, a0640; CHECK-NEXT: sw a2, 0(a1)641; CHECK-NEXT: ret642 %sub = add i32 %x, -65521643 store i32 %sub, ptr %z, align 4644 %cmp = icmp ugt i32 %x, 65520645 %cond = select i1 %cmp, i32 %sub, i32 %x646 ret i32 %cond647}648 649define i32 @sub_if_uge_C_swapped_i32(i32 %x) {650; CHECK-LABEL: sub_if_uge_C_swapped_i32:651; CHECK: # %bb.0:652; CHECK-NEXT: lui a1, 1048560653; CHECK-NEXT: addi a1, a1, 15654; CHECK-NEXT: add a1, a0, a1655; CHECK-NEXT: minu a0, a0, a1656; CHECK-NEXT: ret657 %cmp = icmp ult i32 %x, 65521658 %sub = add i32 %x, -65521659 %cond = select i1 %cmp, i32 %x, i32 %sub660 ret i32 %cond661}662 663define i7 @sub_if_uge_C_nsw_i7(i7 %a) {664; CHECK-LABEL: sub_if_uge_C_nsw_i7:665; CHECK: # %bb.0:666; CHECK-NEXT: ori a0, a0, 51667; CHECK-NEXT: andi a1, a0, 127668; CHECK-NEXT: addi a0, a0, 17669; CHECK-NEXT: andi a0, a0, 92670; CHECK-NEXT: minu a0, a0, a1671; CHECK-NEXT: ret672 %x = or i7 %a, 51673 %c = icmp ugt i7 %x, -18674 %add = add nsw i7 %x, 17675 %s = select i1 %c, i7 %add, i7 %x676 ret i7 %s677}678 679define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {680; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:681; CHECK: # %bb.0:682; CHECK-NEXT: ori a0, a0, 51683; CHECK-NEXT: andi a1, a0, 127684; CHECK-NEXT: addi a0, a0, 17685; CHECK-NEXT: andi a0, a0, 92686; CHECK-NEXT: minu a0, a1, a0687; CHECK-NEXT: ret688 %x = or i7 %a, 51689 %c = icmp ult i7 %x, -17690 %add = add nsw i7 %x, 17691 %s = select i1 %c, i7 %x, i7 %add692 ret i7 %s693}694