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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub2; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+m,+xtheadba -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBA6 7define signext i16 @th_addsl_1(i64 %0, ptr %1) {8; RV32I-LABEL: th_addsl_1:9; RV32I: # %bb.0:10; RV32I-NEXT: slli a0, a0, 111; RV32I-NEXT: add a0, a2, a012; RV32I-NEXT: lh a0, 0(a0)13; RV32I-NEXT: ret14;15; RV32XTHEADBA-LABEL: th_addsl_1:16; RV32XTHEADBA: # %bb.0:17; RV32XTHEADBA-NEXT: th.addsl a0, a2, a0, 118; RV32XTHEADBA-NEXT: lh a0, 0(a0)19; RV32XTHEADBA-NEXT: ret20 %3 = getelementptr inbounds i16, ptr %1, i64 %021 %4 = load i16, ptr %322 ret i16 %423}24 25define signext i32 @th_addsl_2(i64 %0, ptr %1) {26; RV32I-LABEL: th_addsl_2:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 229; RV32I-NEXT: add a0, a2, a030; RV32I-NEXT: lw a0, 0(a0)31; RV32I-NEXT: ret32;33; RV32XTHEADBA-LABEL: th_addsl_2:34; RV32XTHEADBA: # %bb.0:35; RV32XTHEADBA-NEXT: th.addsl a0, a2, a0, 236; RV32XTHEADBA-NEXT: lw a0, 0(a0)37; RV32XTHEADBA-NEXT: ret38 %3 = getelementptr inbounds i32, ptr %1, i64 %039 %4 = load i32, ptr %340 ret i32 %441}42 43define i64 @th_addsl_3(i64 %0, ptr %1) {44; RV32I-LABEL: th_addsl_3:45; RV32I: # %bb.0:46; RV32I-NEXT: slli a0, a0, 347; RV32I-NEXT: add a2, a2, a048; RV32I-NEXT: lw a0, 0(a2)49; RV32I-NEXT: lw a1, 4(a2)50; RV32I-NEXT: ret51;52; RV32XTHEADBA-LABEL: th_addsl_3:53; RV32XTHEADBA: # %bb.0:54; RV32XTHEADBA-NEXT: th.addsl a1, a2, a0, 355; RV32XTHEADBA-NEXT: lw a0, 0(a1)56; RV32XTHEADBA-NEXT: lw a1, 4(a1)57; RV32XTHEADBA-NEXT: ret58 %3 = getelementptr inbounds i64, ptr %1, i64 %059 %4 = load i64, ptr %360 ret i64 %461}62 63; Type legalization inserts a sext_inreg after the first add. That add will be64; selected as th.addsl which does not sign extend. SimplifyDemandedBits is unable65; to remove the sext_inreg because it has multiple uses. The ashr will use the66; sext_inreg to become sraiw. This leaves the sext_inreg only used by the shl.67; If the shl is selected as sllw, we don't need the sext_inreg.68define i64 @th_addsl_2_extra_sext(i32 %x, i32 %y, i32 %z) {69; RV32I-LABEL: th_addsl_2_extra_sext:70; RV32I: # %bb.0:71; RV32I-NEXT: slli a0, a0, 272; RV32I-NEXT: add a0, a0, a173; RV32I-NEXT: sll a1, a2, a074; RV32I-NEXT: srai a2, a0, 275; RV32I-NEXT: mul a0, a1, a276; RV32I-NEXT: mulh a1, a1, a277; RV32I-NEXT: ret78;79; RV32XTHEADBA-LABEL: th_addsl_2_extra_sext:80; RV32XTHEADBA: # %bb.0:81; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 282; RV32XTHEADBA-NEXT: sll a1, a2, a083; RV32XTHEADBA-NEXT: srai a2, a0, 284; RV32XTHEADBA-NEXT: mul a0, a1, a285; RV32XTHEADBA-NEXT: mulh a1, a1, a286; RV32XTHEADBA-NEXT: ret87 %a = shl i32 %x, 288 %b = add i32 %a, %y89 %c = shl i32 %z, %b90 %d = ashr i32 %b, 291 %e = sext i32 %c to i6492 %f = sext i32 %d to i6493 %g = mul i64 %e, %f94 ret i64 %g95}96 97define i32 @addmul6(i32 %a, i32 %b) {98; RV32I-LABEL: addmul6:99; RV32I: # %bb.0:100; RV32I-NEXT: slli a2, a0, 1101; RV32I-NEXT: slli a0, a0, 2102; RV32I-NEXT: add a0, a0, a2103; RV32I-NEXT: add a0, a0, a1104; RV32I-NEXT: ret105;106; RV32XTHEADBA-LABEL: addmul6:107; RV32XTHEADBA: # %bb.0:108; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1109; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1110; RV32XTHEADBA-NEXT: ret111 %c = mul i32 %a, 6112 %d = add i32 %c, %b113 ret i32 %d114}115 116define i32 @addmul10(i32 %a, i32 %b) {117; RV32I-LABEL: addmul10:118; RV32I: # %bb.0:119; RV32I-NEXT: slli a2, a0, 1120; RV32I-NEXT: slli a0, a0, 3121; RV32I-NEXT: add a0, a0, a2122; RV32I-NEXT: add a0, a0, a1123; RV32I-NEXT: ret124;125; RV32XTHEADBA-LABEL: addmul10:126; RV32XTHEADBA: # %bb.0:127; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2128; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1129; RV32XTHEADBA-NEXT: ret130 %c = mul i32 %a, 10131 %d = add i32 %c, %b132 ret i32 %d133}134 135define i32 @addmul12(i32 %a, i32 %b) {136; RV32I-LABEL: addmul12:137; RV32I: # %bb.0:138; RV32I-NEXT: slli a2, a0, 2139; RV32I-NEXT: slli a0, a0, 3140; RV32I-NEXT: add a0, a0, a2141; RV32I-NEXT: add a0, a0, a1142; RV32I-NEXT: ret143;144; RV32XTHEADBA-LABEL: addmul12:145; RV32XTHEADBA: # %bb.0:146; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1147; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2148; RV32XTHEADBA-NEXT: ret149 %c = mul i32 %a, 12150 %d = add i32 %c, %b151 ret i32 %d152}153 154define i32 @addmul18(i32 %a, i32 %b) {155; RV32I-LABEL: addmul18:156; RV32I: # %bb.0:157; RV32I-NEXT: slli a2, a0, 1158; RV32I-NEXT: slli a0, a0, 4159; RV32I-NEXT: add a0, a0, a2160; RV32I-NEXT: add a0, a0, a1161; RV32I-NEXT: ret162;163; RV32XTHEADBA-LABEL: addmul18:164; RV32XTHEADBA: # %bb.0:165; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3166; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1167; RV32XTHEADBA-NEXT: ret168 %c = mul i32 %a, 18169 %d = add i32 %c, %b170 ret i32 %d171}172 173define i32 @addmul20(i32 %a, i32 %b) {174; RV32I-LABEL: addmul20:175; RV32I: # %bb.0:176; RV32I-NEXT: slli a2, a0, 2177; RV32I-NEXT: slli a0, a0, 4178; RV32I-NEXT: add a0, a0, a2179; RV32I-NEXT: add a0, a0, a1180; RV32I-NEXT: ret181;182; RV32XTHEADBA-LABEL: addmul20:183; RV32XTHEADBA: # %bb.0:184; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2185; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2186; RV32XTHEADBA-NEXT: ret187 %c = mul i32 %a, 20188 %d = add i32 %c, %b189 ret i32 %d190}191 192define i32 @addmul24(i32 %a, i32 %b) {193; RV32I-LABEL: addmul24:194; RV32I: # %bb.0:195; RV32I-NEXT: slli a2, a0, 3196; RV32I-NEXT: slli a0, a0, 4197; RV32I-NEXT: add a0, a0, a2198; RV32I-NEXT: add a0, a0, a1199; RV32I-NEXT: ret200;201; RV32XTHEADBA-LABEL: addmul24:202; RV32XTHEADBA: # %bb.0:203; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1204; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3205; RV32XTHEADBA-NEXT: ret206 %c = mul i32 %a, 24207 %d = add i32 %c, %b208 ret i32 %d209}210 211define i32 @addmul36(i32 %a, i32 %b) {212; RV32I-LABEL: addmul36:213; RV32I: # %bb.0:214; RV32I-NEXT: slli a2, a0, 2215; RV32I-NEXT: slli a0, a0, 5216; RV32I-NEXT: add a0, a0, a2217; RV32I-NEXT: add a0, a0, a1218; RV32I-NEXT: ret219;220; RV32XTHEADBA-LABEL: addmul36:221; RV32XTHEADBA: # %bb.0:222; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3223; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2224; RV32XTHEADBA-NEXT: ret225 %c = mul i32 %a, 36226 %d = add i32 %c, %b227 ret i32 %d228}229 230define i32 @addmul40(i32 %a, i32 %b) {231; RV32I-LABEL: addmul40:232; RV32I: # %bb.0:233; RV32I-NEXT: slli a2, a0, 3234; RV32I-NEXT: slli a0, a0, 5235; RV32I-NEXT: add a0, a0, a2236; RV32I-NEXT: add a0, a0, a1237; RV32I-NEXT: ret238;239; RV32XTHEADBA-LABEL: addmul40:240; RV32XTHEADBA: # %bb.0:241; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2242; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3243; RV32XTHEADBA-NEXT: ret244 %c = mul i32 %a, 40245 %d = add i32 %c, %b246 ret i32 %d247}248 249define i32 @addmul72(i32 %a, i32 %b) {250; RV32I-LABEL: addmul72:251; RV32I: # %bb.0:252; RV32I-NEXT: slli a2, a0, 3253; RV32I-NEXT: slli a0, a0, 6254; RV32I-NEXT: add a0, a0, a2255; RV32I-NEXT: add a0, a0, a1256; RV32I-NEXT: ret257;258; RV32XTHEADBA-LABEL: addmul72:259; RV32XTHEADBA: # %bb.0:260; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3261; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3262; RV32XTHEADBA-NEXT: ret263 %c = mul i32 %a, 72264 %d = add i32 %c, %b265 ret i32 %d266}267 268define i32 @mul96(i32 %a) {269; RV32I-LABEL: mul96:270; RV32I: # %bb.0:271; RV32I-NEXT: slli a1, a0, 5272; RV32I-NEXT: slli a0, a0, 6273; RV32I-NEXT: add a0, a0, a1274; RV32I-NEXT: ret275;276; RV32XTHEADBA-LABEL: mul96:277; RV32XTHEADBA: # %bb.0:278; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1279; RV32XTHEADBA-NEXT: slli a0, a0, 5280; RV32XTHEADBA-NEXT: ret281 %c = mul i32 %a, 96282 ret i32 %c283}284 285define i32 @mul160(i32 %a) {286; RV32I-LABEL: mul160:287; RV32I: # %bb.0:288; RV32I-NEXT: slli a1, a0, 5289; RV32I-NEXT: slli a0, a0, 7290; RV32I-NEXT: add a0, a0, a1291; RV32I-NEXT: ret292;293; RV32XTHEADBA-LABEL: mul160:294; RV32XTHEADBA: # %bb.0:295; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2296; RV32XTHEADBA-NEXT: slli a0, a0, 5297; RV32XTHEADBA-NEXT: ret298 %c = mul i32 %a, 160299 ret i32 %c300}301 302define i32 @mul200(i32 %a) {303; RV32I-LABEL: mul200:304; RV32I: # %bb.0:305; RV32I-NEXT: li a1, 200306; RV32I-NEXT: mul a0, a0, a1307; RV32I-NEXT: ret308;309; RV32XTHEADBA-LABEL: mul200:310; RV32XTHEADBA: # %bb.0:311; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2312; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2313; RV32XTHEADBA-NEXT: slli a0, a0, 3314; RV32XTHEADBA-NEXT: ret315 %c = mul i32 %a, 200316 ret i32 %c317}318 319define i32 @mul288(i32 %a) {320; RV32I-LABEL: mul288:321; RV32I: # %bb.0:322; RV32I-NEXT: slli a1, a0, 5323; RV32I-NEXT: slli a0, a0, 8324; RV32I-NEXT: add a0, a0, a1325; RV32I-NEXT: ret326;327; RV32XTHEADBA-LABEL: mul288:328; RV32XTHEADBA: # %bb.0:329; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3330; RV32XTHEADBA-NEXT: slli a0, a0, 5331; RV32XTHEADBA-NEXT: ret332 %c = mul i32 %a, 288333 ret i32 %c334}335 336define i32 @mul258(i32 %a) {337; RV32I-LABEL: mul258:338; RV32I: # %bb.0:339; RV32I-NEXT: slli a1, a0, 1340; RV32I-NEXT: slli a0, a0, 8341; RV32I-NEXT: add a0, a0, a1342; RV32I-NEXT: ret343;344; RV32XTHEADBA-LABEL: mul258:345; RV32XTHEADBA: # %bb.0:346; RV32XTHEADBA-NEXT: slli a1, a0, 8347; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1348; RV32XTHEADBA-NEXT: ret349 %c = mul i32 %a, 258350 ret i32 %c351}352 353define i32 @mul260(i32 %a) {354; RV32I-LABEL: mul260:355; RV32I: # %bb.0:356; RV32I-NEXT: slli a1, a0, 2357; RV32I-NEXT: slli a0, a0, 8358; RV32I-NEXT: add a0, a0, a1359; RV32I-NEXT: ret360;361; RV32XTHEADBA-LABEL: mul260:362; RV32XTHEADBA: # %bb.0:363; RV32XTHEADBA-NEXT: slli a1, a0, 8364; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2365; RV32XTHEADBA-NEXT: ret366 %c = mul i32 %a, 260367 ret i32 %c368}369 370define i32 @mul264(i32 %a) {371; RV32I-LABEL: mul264:372; RV32I: # %bb.0:373; RV32I-NEXT: slli a1, a0, 3374; RV32I-NEXT: slli a0, a0, 8375; RV32I-NEXT: add a0, a0, a1376; RV32I-NEXT: ret377;378; RV32XTHEADBA-LABEL: mul264:379; RV32XTHEADBA: # %bb.0:380; RV32XTHEADBA-NEXT: slli a1, a0, 8381; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3382; RV32XTHEADBA-NEXT: ret383 %c = mul i32 %a, 264384 ret i32 %c385}386 387define i32 @mul11(i32 %a) {388; RV32I-LABEL: mul11:389; RV32I: # %bb.0:390; RV32I-NEXT: li a1, 11391; RV32I-NEXT: mul a0, a0, a1392; RV32I-NEXT: ret393;394; RV32XTHEADBA-LABEL: mul11:395; RV32XTHEADBA: # %bb.0:396; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2397; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1398; RV32XTHEADBA-NEXT: ret399 %c = mul i32 %a, 11400 ret i32 %c401}402 403define i32 @mul19(i32 %a) {404; RV32I-LABEL: mul19:405; RV32I: # %bb.0:406; RV32I-NEXT: li a1, 19407; RV32I-NEXT: mul a0, a0, a1408; RV32I-NEXT: ret409;410; RV32XTHEADBA-LABEL: mul19:411; RV32XTHEADBA: # %bb.0:412; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3413; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1414; RV32XTHEADBA-NEXT: ret415 %c = mul i32 %a, 19416 ret i32 %c417}418 419define i32 @mul13(i32 %a) {420; RV32I-LABEL: mul13:421; RV32I: # %bb.0:422; RV32I-NEXT: li a1, 13423; RV32I-NEXT: mul a0, a0, a1424; RV32I-NEXT: ret425;426; RV32XTHEADBA-LABEL: mul13:427; RV32XTHEADBA: # %bb.0:428; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 1429; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2430; RV32XTHEADBA-NEXT: ret431 %c = mul i32 %a, 13432 ret i32 %c433}434 435define i32 @mul21(i32 %a) {436; RV32I-LABEL: mul21:437; RV32I: # %bb.0:438; RV32I-NEXT: li a1, 21439; RV32I-NEXT: mul a0, a0, a1440; RV32I-NEXT: ret441;442; RV32XTHEADBA-LABEL: mul21:443; RV32XTHEADBA: # %bb.0:444; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2445; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2446; RV32XTHEADBA-NEXT: ret447 %c = mul i32 %a, 21448 ret i32 %c449}450 451define i32 @mul37(i32 %a) {452; RV32I-LABEL: mul37:453; RV32I: # %bb.0:454; RV32I-NEXT: li a1, 37455; RV32I-NEXT: mul a0, a0, a1456; RV32I-NEXT: ret457;458; RV32XTHEADBA-LABEL: mul37:459; RV32XTHEADBA: # %bb.0:460; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3461; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2462; RV32XTHEADBA-NEXT: ret463 %c = mul i32 %a, 37464 ret i32 %c465}466 467define i32 @mul25(i32 %a) {468; RV32I-LABEL: mul25:469; RV32I: # %bb.0:470; RV32I-NEXT: li a1, 25471; RV32I-NEXT: mul a0, a0, a1472; RV32I-NEXT: ret473;474; RV32XTHEADBA-LABEL: mul25:475; RV32XTHEADBA: # %bb.0:476; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2477; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2478; RV32XTHEADBA-NEXT: ret479 %c = mul i32 %a, 25480 ret i32 %c481}482 483define i32 @mul41(i32 %a) {484; RV32I-LABEL: mul41:485; RV32I: # %bb.0:486; RV32I-NEXT: li a1, 41487; RV32I-NEXT: mul a0, a0, a1488; RV32I-NEXT: ret489;490; RV32XTHEADBA-LABEL: mul41:491; RV32XTHEADBA: # %bb.0:492; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 2493; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3494; RV32XTHEADBA-NEXT: ret495 %c = mul i32 %a, 41496 ret i32 %c497}498 499define i32 @mul73(i32 %a) {500; RV32I-LABEL: mul73:501; RV32I: # %bb.0:502; RV32I-NEXT: li a1, 73503; RV32I-NEXT: mul a0, a0, a1504; RV32I-NEXT: ret505;506; RV32XTHEADBA-LABEL: mul73:507; RV32XTHEADBA: # %bb.0:508; RV32XTHEADBA-NEXT: th.addsl a1, a0, a0, 3509; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3510; RV32XTHEADBA-NEXT: ret511 %c = mul i32 %a, 73512 ret i32 %c513}514 515define i32 @mul27(i32 %a) {516; RV32I-LABEL: mul27:517; RV32I: # %bb.0:518; RV32I-NEXT: li a1, 27519; RV32I-NEXT: mul a0, a0, a1520; RV32I-NEXT: ret521;522; RV32XTHEADBA-LABEL: mul27:523; RV32XTHEADBA: # %bb.0:524; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1525; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3526; RV32XTHEADBA-NEXT: ret527 %c = mul i32 %a, 27528 ret i32 %c529}530 531define i32 @mul45(i32 %a) {532; RV32I-LABEL: mul45:533; RV32I: # %bb.0:534; RV32I-NEXT: li a1, 45535; RV32I-NEXT: mul a0, a0, a1536; RV32I-NEXT: ret537;538; RV32XTHEADBA-LABEL: mul45:539; RV32XTHEADBA: # %bb.0:540; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2541; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3542; RV32XTHEADBA-NEXT: ret543 %c = mul i32 %a, 45544 ret i32 %c545}546 547define i32 @mul81(i32 %a) {548; RV32I-LABEL: mul81:549; RV32I: # %bb.0:550; RV32I-NEXT: li a1, 81551; RV32I-NEXT: mul a0, a0, a1552; RV32I-NEXT: ret553;554; RV32XTHEADBA-LABEL: mul81:555; RV32XTHEADBA: # %bb.0:556; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3557; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 3558; RV32XTHEADBA-NEXT: ret559 %c = mul i32 %a, 81560 ret i32 %c561}562 563define i32 @mul4098(i32 %a) {564; RV32I-LABEL: mul4098:565; RV32I: # %bb.0:566; RV32I-NEXT: slli a1, a0, 1567; RV32I-NEXT: slli a0, a0, 12568; RV32I-NEXT: add a0, a0, a1569; RV32I-NEXT: ret570;571; RV32XTHEADBA-LABEL: mul4098:572; RV32XTHEADBA: # %bb.0:573; RV32XTHEADBA-NEXT: slli a1, a0, 12574; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 1575; RV32XTHEADBA-NEXT: ret576 %c = mul i32 %a, 4098577 ret i32 %c578}579 580define i32 @mul4100(i32 %a) {581; RV32I-LABEL: mul4100:582; RV32I: # %bb.0:583; RV32I-NEXT: slli a1, a0, 2584; RV32I-NEXT: slli a0, a0, 12585; RV32I-NEXT: add a0, a0, a1586; RV32I-NEXT: ret587;588; RV32XTHEADBA-LABEL: mul4100:589; RV32XTHEADBA: # %bb.0:590; RV32XTHEADBA-NEXT: slli a1, a0, 12591; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 2592; RV32XTHEADBA-NEXT: ret593 %c = mul i32 %a, 4100594 ret i32 %c595}596 597define i32 @mul4104(i32 %a) {598; RV32I-LABEL: mul4104:599; RV32I: # %bb.0:600; RV32I-NEXT: slli a1, a0, 3601; RV32I-NEXT: slli a0, a0, 12602; RV32I-NEXT: add a0, a0, a1603; RV32I-NEXT: ret604;605; RV32XTHEADBA-LABEL: mul4104:606; RV32XTHEADBA: # %bb.0:607; RV32XTHEADBA-NEXT: slli a1, a0, 12608; RV32XTHEADBA-NEXT: th.addsl a0, a1, a0, 3609; RV32XTHEADBA-NEXT: ret610 %c = mul i32 %a, 4104611 ret i32 %c612}613 614define i32 @add4104(i32 %a) {615; RV32I-LABEL: add4104:616; RV32I: # %bb.0:617; RV32I-NEXT: lui a1, 1618; RV32I-NEXT: addi a1, a1, 8619; RV32I-NEXT: add a0, a0, a1620; RV32I-NEXT: ret621;622; RV32XTHEADBA-LABEL: add4104:623; RV32XTHEADBA: # %bb.0:624; RV32XTHEADBA-NEXT: li a1, 1026625; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2626; RV32XTHEADBA-NEXT: ret627 %c = add i32 %a, 4104628 ret i32 %c629}630 631define i32 @add8208(i32 %a) {632; RV32I-LABEL: add8208:633; RV32I: # %bb.0:634; RV32I-NEXT: lui a1, 2635; RV32I-NEXT: addi a1, a1, 16636; RV32I-NEXT: add a0, a0, a1637; RV32I-NEXT: ret638;639; RV32XTHEADBA-LABEL: add8208:640; RV32XTHEADBA: # %bb.0:641; RV32XTHEADBA-NEXT: li a1, 1026642; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3643; RV32XTHEADBA-NEXT: ret644 %c = add i32 %a, 8208645 ret i32 %c646}647 648define i32 @add8192(i32 %a) {649; CHECK-LABEL: add8192:650; CHECK: # %bb.0:651; CHECK-NEXT: lui a1, 2652; CHECK-NEXT: add a0, a0, a1653; CHECK-NEXT: ret654 %c = add i32 %a, 8192655 ret i32 %c656}657 658define i32 @addshl_5_6(i32 %a, i32 %b) {659; RV32I-LABEL: addshl_5_6:660; RV32I: # %bb.0:661; RV32I-NEXT: slli a0, a0, 5662; RV32I-NEXT: slli a1, a1, 6663; RV32I-NEXT: add a0, a0, a1664; RV32I-NEXT: ret665;666; RV32XTHEADBA-LABEL: addshl_5_6:667; RV32XTHEADBA: # %bb.0:668; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1669; RV32XTHEADBA-NEXT: slli a0, a0, 5670; RV32XTHEADBA-NEXT: ret671 %c = shl i32 %a, 5672 %d = shl i32 %b, 6673 %e = add i32 %c, %d674 ret i32 %e675}676 677define i32 @addshl_5_7(i32 %a, i32 %b) {678; RV32I-LABEL: addshl_5_7:679; RV32I: # %bb.0:680; RV32I-NEXT: slli a0, a0, 5681; RV32I-NEXT: slli a1, a1, 7682; RV32I-NEXT: add a0, a0, a1683; RV32I-NEXT: ret684;685; RV32XTHEADBA-LABEL: addshl_5_7:686; RV32XTHEADBA: # %bb.0:687; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2688; RV32XTHEADBA-NEXT: slli a0, a0, 5689; RV32XTHEADBA-NEXT: ret690 %c = shl i32 %a, 5691 %d = shl i32 %b, 7692 %e = add i32 %c, %d693 ret i32 %e694}695 696define i32 @addshl_5_8(i32 %a, i32 %b) {697; RV32I-LABEL: addshl_5_8:698; RV32I: # %bb.0:699; RV32I-NEXT: slli a0, a0, 5700; RV32I-NEXT: slli a1, a1, 8701; RV32I-NEXT: add a0, a0, a1702; RV32I-NEXT: ret703;704; RV32XTHEADBA-LABEL: addshl_5_8:705; RV32XTHEADBA: # %bb.0:706; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 3707; RV32XTHEADBA-NEXT: slli a0, a0, 5708; RV32XTHEADBA-NEXT: ret709 %c = shl i32 %a, 5710 %d = shl i32 %b, 8711 %e = add i32 %c, %d712 ret i32 %e713}714 715define i32 @srli_1_sh2add(ptr %0, i32 %1) {716; RV32I-LABEL: srli_1_sh2add:717; RV32I: # %bb.0:718; RV32I-NEXT: slli a1, a1, 1719; RV32I-NEXT: andi a1, a1, -4720; RV32I-NEXT: add a0, a0, a1721; RV32I-NEXT: lw a0, 0(a0)722; RV32I-NEXT: ret723;724; RV32XTHEADBA-LABEL: srli_1_sh2add:725; RV32XTHEADBA: # %bb.0:726; RV32XTHEADBA-NEXT: srli a1, a1, 1727; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2728; RV32XTHEADBA-NEXT: lw a0, 0(a0)729; RV32XTHEADBA-NEXT: ret730 %3 = lshr i32 %1, 1731 %4 = getelementptr inbounds i32, ptr %0, i32 %3732 %5 = load i32, ptr %4, align 4733 ret i32 %5734}735 736define i64 @srli_2_sh3add(ptr %0, i32 %1) {737; RV32I-LABEL: srli_2_sh3add:738; RV32I: # %bb.0:739; RV32I-NEXT: slli a1, a1, 1740; RV32I-NEXT: andi a1, a1, -8741; RV32I-NEXT: add a1, a0, a1742; RV32I-NEXT: lw a0, 0(a1)743; RV32I-NEXT: lw a1, 4(a1)744; RV32I-NEXT: ret745;746; RV32XTHEADBA-LABEL: srli_2_sh3add:747; RV32XTHEADBA: # %bb.0:748; RV32XTHEADBA-NEXT: srli a1, a1, 2749; RV32XTHEADBA-NEXT: th.addsl a1, a0, a1, 3750; RV32XTHEADBA-NEXT: lw a0, 0(a1)751; RV32XTHEADBA-NEXT: lw a1, 4(a1)752; RV32XTHEADBA-NEXT: ret753 %3 = lshr i32 %1, 2754 %4 = getelementptr inbounds i64, ptr %0, i32 %3755 %5 = load i64, ptr %4, align 8756 ret i64 %5757}758 759define signext i16 @srli_2_sh1add(ptr %0, i32 %1) {760; RV32I-LABEL: srli_2_sh1add:761; RV32I: # %bb.0:762; RV32I-NEXT: srli a1, a1, 1763; RV32I-NEXT: andi a1, a1, -2764; RV32I-NEXT: add a0, a0, a1765; RV32I-NEXT: lh a0, 0(a0)766; RV32I-NEXT: ret767;768; RV32XTHEADBA-LABEL: srli_2_sh1add:769; RV32XTHEADBA: # %bb.0:770; RV32XTHEADBA-NEXT: srli a1, a1, 2771; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 1772; RV32XTHEADBA-NEXT: lh a0, 0(a0)773; RV32XTHEADBA-NEXT: ret774 %3 = lshr i32 %1, 2775 %4 = getelementptr inbounds i16, ptr %0, i32 %3776 %5 = load i16, ptr %4, align 2777 ret i16 %5778}779 780define i32 @srli_3_sh2add(ptr %0, i32 %1) {781; RV32I-LABEL: srli_3_sh2add:782; RV32I: # %bb.0:783; RV32I-NEXT: srli a1, a1, 1784; RV32I-NEXT: andi a1, a1, -4785; RV32I-NEXT: add a0, a0, a1786; RV32I-NEXT: lw a0, 0(a0)787; RV32I-NEXT: ret788;789; RV32XTHEADBA-LABEL: srli_3_sh2add:790; RV32XTHEADBA: # %bb.0:791; RV32XTHEADBA-NEXT: srli a1, a1, 3792; RV32XTHEADBA-NEXT: th.addsl a0, a0, a1, 2793; RV32XTHEADBA-NEXT: lw a0, 0(a0)794; RV32XTHEADBA-NEXT: ret795 %3 = lshr i32 %1, 3796 %4 = getelementptr inbounds i32, ptr %0, i32 %3797 %5 = load i32, ptr %4, align 4798 ret i32 %5799}800 801define i64 @srli_4_sh3add(ptr %0, i32 %1) {802; RV32I-LABEL: srli_4_sh3add:803; RV32I: # %bb.0:804; RV32I-NEXT: srli a1, a1, 1805; RV32I-NEXT: andi a1, a1, -8806; RV32I-NEXT: add a1, a0, a1807; RV32I-NEXT: lw a0, 0(a1)808; RV32I-NEXT: lw a1, 4(a1)809; RV32I-NEXT: ret810;811; RV32XTHEADBA-LABEL: srli_4_sh3add:812; RV32XTHEADBA: # %bb.0:813; RV32XTHEADBA-NEXT: srli a1, a1, 4814; RV32XTHEADBA-NEXT: th.addsl a1, a0, a1, 3815; RV32XTHEADBA-NEXT: lw a0, 0(a1)816; RV32XTHEADBA-NEXT: lw a1, 4(a1)817; RV32XTHEADBA-NEXT: ret818 %3 = lshr i32 %1, 4819 %4 = getelementptr inbounds i64, ptr %0, i32 %3820 %5 = load i64, ptr %4, align 8821 ret i64 %5822}823 824define i32 @mul_neg1(i32 %a) {825; CHECK-LABEL: mul_neg1:826; CHECK: # %bb.0:827; CHECK-NEXT: neg a0, a0828; CHECK-NEXT: ret829 %c = mul i32 %a, -1830 ret i32 %c831}832 833define i32 @mul_neg2(i32 %a) {834; CHECK-LABEL: mul_neg2:835; CHECK: # %bb.0:836; CHECK-NEXT: slli a0, a0, 1837; CHECK-NEXT: neg a0, a0838; CHECK-NEXT: ret839 %c = mul i32 %a, -2840 ret i32 %c841}842 843define i32 @mul_neg3(i32 %a) {844; RV32I-LABEL: mul_neg3:845; RV32I: # %bb.0:846; RV32I-NEXT: slli a1, a0, 1847; RV32I-NEXT: neg a0, a0848; RV32I-NEXT: sub a0, a0, a1849; RV32I-NEXT: ret850;851; RV32XTHEADBA-LABEL: mul_neg3:852; RV32XTHEADBA: # %bb.0:853; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 1854; RV32XTHEADBA-NEXT: neg a0, a0855; RV32XTHEADBA-NEXT: ret856 %c = mul i32 %a, -3857 ret i32 %c858}859 860define i32 @mul_neg4(i32 %a) {861; CHECK-LABEL: mul_neg4:862; CHECK: # %bb.0:863; CHECK-NEXT: slli a0, a0, 2864; CHECK-NEXT: neg a0, a0865; CHECK-NEXT: ret866 %c = mul i32 %a, -4867 ret i32 %c868}869 870define i32 @mul_neg5(i32 %a) {871; RV32I-LABEL: mul_neg5:872; RV32I: # %bb.0:873; RV32I-NEXT: slli a1, a0, 2874; RV32I-NEXT: neg a0, a0875; RV32I-NEXT: sub a0, a0, a1876; RV32I-NEXT: ret877;878; RV32XTHEADBA-LABEL: mul_neg5:879; RV32XTHEADBA: # %bb.0:880; RV32XTHEADBA-NEXT: th.addsl a0, a0, a0, 2881; RV32XTHEADBA-NEXT: neg a0, a0882; RV32XTHEADBA-NEXT: ret883 %c = mul i32 %a, -5884 ret i32 %c885}886 887define i32 @mul_neg6(i32 %a) {888; CHECK-LABEL: mul_neg6:889; CHECK: # %bb.0:890; CHECK-NEXT: li a1, -6891; CHECK-NEXT: mul a0, a0, a1892; CHECK-NEXT: ret893 %c = mul i32 %a, -6894 ret i32 %c895}896 897define i32 @mul_neg7(i32 %a) {898; CHECK-LABEL: mul_neg7:899; CHECK: # %bb.0:900; CHECK-NEXT: slli a1, a0, 3901; CHECK-NEXT: sub a0, a0, a1902; CHECK-NEXT: ret903 %c = mul i32 %a, -7904 ret i32 %c905}906 907define i32 @mul_neg8(i32 %a) {908; CHECK-LABEL: mul_neg8:909; CHECK: # %bb.0:910; CHECK-NEXT: slli a0, a0, 3911; CHECK-NEXT: neg a0, a0912; CHECK-NEXT: ret913 %c = mul i32 %a, -8914 ret i32 %c915}916