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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV32I4; RUN: llc -mtriple=riscv32 -mattr=+xtheadbs -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV32XTHEADBS6 7define i32 @th_tst_i32(i32 %a) nounwind {8; RV32I-LABEL: th_tst_i32:9; RV32I: # %bb.0:10; RV32I-NEXT: slli a0, a0, 2611; RV32I-NEXT: srli a0, a0, 3112; RV32I-NEXT: ret13;14; RV32XTHEADBS-LABEL: th_tst_i32:15; RV32XTHEADBS: # %bb.0:16; RV32XTHEADBS-NEXT: th.tst a0, a0, 517; RV32XTHEADBS-NEXT: ret18 %shr = lshr i32 %a, 519 %and = and i32 %shr, 120 ret i32 %and21}22 23define i64 @th_tst_i64(i64 %a) nounwind {24; RV32I-LABEL: th_tst_i64:25; RV32I: # %bb.0:26; RV32I-NEXT: slli a0, a0, 2627; RV32I-NEXT: srli a0, a0, 3128; RV32I-NEXT: li a1, 029; RV32I-NEXT: ret30;31; RV32XTHEADBS-LABEL: th_tst_i64:32; RV32XTHEADBS: # %bb.0:33; RV32XTHEADBS-NEXT: th.tst a0, a0, 534; RV32XTHEADBS-NEXT: li a1, 035; RV32XTHEADBS-NEXT: ret36 %shr = lshr i64 %a, 537 %and = and i64 %shr, 138 ret i64 %and39}40 41define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind {42; RV32I-LABEL: th_tst_i32_cmp:43; RV32I: # %bb.0:44; RV32I-NEXT: slli a0, a0, 2645; RV32I-NEXT: srli a0, a0, 3146; RV32I-NEXT: ret47;48; RV32XTHEADBS-LABEL: th_tst_i32_cmp:49; RV32XTHEADBS: # %bb.0:50; RV32XTHEADBS-NEXT: th.tst a0, a0, 551; RV32XTHEADBS-NEXT: ret52 %and = and i32 %a, 3253 %cmp = icmp ne i32 %and, 054 %zext = zext i1 %cmp to i3255 ret i32 %zext56}57 58define i64 @th_tst_i64_cmp(i64 %a) nounwind {59; RV32I-LABEL: th_tst_i64_cmp:60; RV32I: # %bb.0:61; RV32I-NEXT: slli a0, a0, 2662; RV32I-NEXT: srli a0, a0, 3163; RV32I-NEXT: li a1, 064; RV32I-NEXT: ret65;66; RV32XTHEADBS-LABEL: th_tst_i64_cmp:67; RV32XTHEADBS: # %bb.0:68; RV32XTHEADBS-NEXT: th.tst a0, a0, 569; RV32XTHEADBS-NEXT: li a1, 070; RV32XTHEADBS-NEXT: ret71 %and = and i64 %a, 3272 %cmp = icmp ne i64 %and, 073 %zext = zext i1 %cmp to i6474 ret i64 %zext75}76