33 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32ZBB4 5define i32 @orcb(i32 %a) nounwind {6; RV32ZBB-LABEL: orcb:7; RV32ZBB: # %bb.0:8; RV32ZBB-NEXT: orc.b a0, a09; RV32ZBB-NEXT: ret10 %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)11 ret i32 %tmp12}13 14; Second and+or are redundant with the first, make sure we remove one of the15; ands and one of the ors.16define i32 @orcb_knownbits(i32 %a) nounwind {17; RV32ZBB-LABEL: orcb_knownbits:18; RV32ZBB: # %bb.0:19; RV32ZBB-NEXT: lui a1, 104448020; RV32ZBB-NEXT: and a0, a0, a121; RV32ZBB-NEXT: lui a1, 408022; RV32ZBB-NEXT: orc.b a0, a023; RV32ZBB-NEXT: addi a1, a1, 25524; RV32ZBB-NEXT: or a0, a0, a125; RV32ZBB-NEXT: ret26 %tmp = and i32 %a, 4278190080 ; 0xFF00000027 %tmp2 = or i32 %tmp, 8388609 ; 0x80000128 %tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2)29 %tmp4 = and i32 %tmp3, 4278190080 ; 0xFF00000030 %tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF31 ret i32 %tmp532}33