921 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB6; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB-ZBKB8 9define i32 @andn_i32(i32 %a, i32 %b) nounwind {10; RV32I-LABEL: andn_i32:11; RV32I: # %bb.0:12; RV32I-NEXT: not a1, a113; RV32I-NEXT: and a0, a1, a014; RV32I-NEXT: ret15;16; RV32ZBB-ZBKB-LABEL: andn_i32:17; RV32ZBB-ZBKB: # %bb.0:18; RV32ZBB-ZBKB-NEXT: andn a0, a0, a119; RV32ZBB-ZBKB-NEXT: ret20 %neg = xor i32 %b, -121 %and = and i32 %neg, %a22 ret i32 %and23}24 25define i64 @andn_i64(i64 %a, i64 %b) nounwind {26; RV32I-LABEL: andn_i64:27; RV32I: # %bb.0:28; RV32I-NEXT: not a3, a329; RV32I-NEXT: not a2, a230; RV32I-NEXT: and a0, a2, a031; RV32I-NEXT: and a1, a3, a132; RV32I-NEXT: ret33;34; RV32ZBB-ZBKB-LABEL: andn_i64:35; RV32ZBB-ZBKB: # %bb.0:36; RV32ZBB-ZBKB-NEXT: andn a0, a0, a237; RV32ZBB-ZBKB-NEXT: andn a1, a1, a338; RV32ZBB-ZBKB-NEXT: ret39 %neg = xor i64 %b, -140 %and = and i64 %neg, %a41 ret i64 %and42}43 44define i32 @orn_i32(i32 %a, i32 %b) nounwind {45; RV32I-LABEL: orn_i32:46; RV32I: # %bb.0:47; RV32I-NEXT: not a1, a148; RV32I-NEXT: or a0, a1, a049; RV32I-NEXT: ret50;51; RV32ZBB-ZBKB-LABEL: orn_i32:52; RV32ZBB-ZBKB: # %bb.0:53; RV32ZBB-ZBKB-NEXT: orn a0, a0, a154; RV32ZBB-ZBKB-NEXT: ret55 %neg = xor i32 %b, -156 %or = or i32 %neg, %a57 ret i32 %or58}59 60define i64 @orn_i64(i64 %a, i64 %b) nounwind {61; RV32I-LABEL: orn_i64:62; RV32I: # %bb.0:63; RV32I-NEXT: not a3, a364; RV32I-NEXT: not a2, a265; RV32I-NEXT: or a0, a2, a066; RV32I-NEXT: or a1, a3, a167; RV32I-NEXT: ret68;69; RV32ZBB-ZBKB-LABEL: orn_i64:70; RV32ZBB-ZBKB: # %bb.0:71; RV32ZBB-ZBKB-NEXT: orn a0, a0, a272; RV32ZBB-ZBKB-NEXT: orn a1, a1, a373; RV32ZBB-ZBKB-NEXT: ret74 %neg = xor i64 %b, -175 %or = or i64 %neg, %a76 ret i64 %or77}78 79define i32 @xnor_i32(i32 %a, i32 %b) nounwind {80; RV32I-LABEL: xnor_i32:81; RV32I: # %bb.0:82; RV32I-NEXT: xor a0, a0, a183; RV32I-NEXT: not a0, a084; RV32I-NEXT: ret85;86; RV32ZBB-ZBKB-LABEL: xnor_i32:87; RV32ZBB-ZBKB: # %bb.0:88; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a189; RV32ZBB-ZBKB-NEXT: ret90 %neg = xor i32 %a, -191 %xor = xor i32 %neg, %b92 ret i32 %xor93}94 95define i64 @xnor_i64(i64 %a, i64 %b) nounwind {96; RV32I-LABEL: xnor_i64:97; RV32I: # %bb.0:98; RV32I-NEXT: xor a1, a1, a399; RV32I-NEXT: xor a0, a0, a2100; RV32I-NEXT: not a0, a0101; RV32I-NEXT: not a1, a1102; RV32I-NEXT: ret103;104; RV32ZBB-ZBKB-LABEL: xnor_i64:105; RV32ZBB-ZBKB: # %bb.0:106; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a2107; RV32ZBB-ZBKB-NEXT: xnor a1, a1, a3108; RV32ZBB-ZBKB-NEXT: ret109 %neg = xor i64 %a, -1110 %xor = xor i64 %neg, %b111 ret i64 %xor112}113 114define i32 @disjoint_or_xnor_i32(i32 %a, i32 %b) nounwind {115; RV32I-LABEL: disjoint_or_xnor_i32:116; RV32I: # %bb.0:117; RV32I-NEXT: or a0, a0, a1118; RV32I-NEXT: not a0, a0119; RV32I-NEXT: ret120;121; RV32ZBB-ZBKB-LABEL: disjoint_or_xnor_i32:122; RV32ZBB-ZBKB: # %bb.0:123; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a1124; RV32ZBB-ZBKB-NEXT: ret125 %or = or disjoint i32 %a, %b126 %not = xor i32 %or, -1127 ret i32 %not128}129 130define i64 @disjoint_or_xnor_i64(i64 %a, i64 %b) nounwind {131; RV32I-LABEL: disjoint_or_xnor_i64:132; RV32I: # %bb.0:133; RV32I-NEXT: or a1, a1, a3134; RV32I-NEXT: or a0, a0, a2135; RV32I-NEXT: not a0, a0136; RV32I-NEXT: not a1, a1137; RV32I-NEXT: ret138;139; RV32ZBB-ZBKB-LABEL: disjoint_or_xnor_i64:140; RV32ZBB-ZBKB: # %bb.0:141; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a2142; RV32ZBB-ZBKB-NEXT: xnor a1, a1, a3143; RV32ZBB-ZBKB-NEXT: ret144 %or = or disjoint i64 %a, %b145 %not = xor i64 %or, -1146 ret i64 %not147}148 149define i32 @disjoint_or_xnor_knownbits_i32(i32 %x, i32 %y, i32 %z) nounwind {150; RV32I-LABEL: disjoint_or_xnor_knownbits_i32:151; RV32I: # %bb.0:152; RV32I-NEXT: andi a0, a0, 126153; RV32I-NEXT: andi a1, a1, -127154; RV32I-NEXT: or a0, a0, a1155; RV32I-NEXT: not a0, a0156; RV32I-NEXT: ret157;158; RV32ZBB-ZBKB-LABEL: disjoint_or_xnor_knownbits_i32:159; RV32ZBB-ZBKB: # %bb.0:160; RV32ZBB-ZBKB-NEXT: andi a0, a0, 126161; RV32ZBB-ZBKB-NEXT: andi a1, a1, -127162; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a1163; RV32ZBB-ZBKB-NEXT: ret164 %a = and i32 %x, 126165 %b = and i32 %y, -127166 %or = or i32 %a, %b167 %not = xor i32 %or, -1168 ret i32 %not169}170 171define i64 @disjoint_or_xnor_knownbits_i64(i64 %x, i64 %y, i64 %z) nounwind {172; RV32I-LABEL: disjoint_or_xnor_knownbits_i64:173; RV32I: # %bb.0:174; RV32I-NEXT: andi a0, a0, 126175; RV32I-NEXT: andi a1, a2, -127176; RV32I-NEXT: or a0, a0, a1177; RV32I-NEXT: not a0, a0178; RV32I-NEXT: not a1, a3179; RV32I-NEXT: ret180;181; RV32ZBB-ZBKB-LABEL: disjoint_or_xnor_knownbits_i64:182; RV32ZBB-ZBKB: # %bb.0:183; RV32ZBB-ZBKB-NEXT: andi a0, a0, 126184; RV32ZBB-ZBKB-NEXT: andi a1, a2, -127185; RV32ZBB-ZBKB-NEXT: xnor a0, a0, a1186; RV32ZBB-ZBKB-NEXT: not a1, a3187; RV32ZBB-ZBKB-NEXT: ret188 %a = and i64 %x, 126189 %b = and i64 %y, -127190 %or = or i64 %a, %b191 %not = xor i64 %or, -1192 ret i64 %not193}194 195define i32 @inverted_masked_merge_i32(i32 %x, i32 %y, i32 %z) nounwind {196; RV32I-LABEL: inverted_masked_merge_i32:197; RV32I: # %bb.0:198; RV32I-NEXT: xor a1, a1, a2199; RV32I-NEXT: and a0, a1, a0200; RV32I-NEXT: xor a0, a0, a2201; RV32I-NEXT: not a0, a0202; RV32I-NEXT: ret203;204; RV32ZBB-ZBKB-LABEL: inverted_masked_merge_i32:205; RV32ZBB-ZBKB: # %bb.0:206; RV32ZBB-ZBKB-NEXT: and a1, a0, a1207; RV32ZBB-ZBKB-NEXT: andn a0, a2, a0208; RV32ZBB-ZBKB-NEXT: xnor a0, a1, a0209; RV32ZBB-ZBKB-NEXT: ret210 %a = and i32 %x, %y211 %notx = xor i32 %x, -1212 %b = and i32 %notx, %z213 %or = or i32 %a, %b214 %not = xor i32 %or, -1215 ret i32 %not216}217 218define i64 @inverted_masked_merge_i64(i64 %x, i64 %y, i64 %z) nounwind {219; RV32I-LABEL: inverted_masked_merge_i64:220; RV32I: # %bb.0:221; RV32I-NEXT: xor a3, a3, a5222; RV32I-NEXT: xor a2, a2, a4223; RV32I-NEXT: and a1, a3, a1224; RV32I-NEXT: and a0, a2, a0225; RV32I-NEXT: xor a1, a1, a5226; RV32I-NEXT: xor a0, a0, a4227; RV32I-NEXT: not a0, a0228; RV32I-NEXT: not a1, a1229; RV32I-NEXT: ret230;231; RV32ZBB-ZBKB-LABEL: inverted_masked_merge_i64:232; RV32ZBB-ZBKB: # %bb.0:233; RV32ZBB-ZBKB-NEXT: and a3, a1, a3234; RV32ZBB-ZBKB-NEXT: and a2, a0, a2235; RV32ZBB-ZBKB-NEXT: andn a1, a5, a1236; RV32ZBB-ZBKB-NEXT: andn a0, a4, a0237; RV32ZBB-ZBKB-NEXT: xnor a0, a2, a0238; RV32ZBB-ZBKB-NEXT: xnor a1, a3, a1239; RV32ZBB-ZBKB-NEXT: ret240 %a = and i64 %x, %y241 %notx = xor i64 %x, -1242 %b = and i64 %notx, %z243 %or = or i64 %a, %b244 %not = xor i64 %or, -1245 ret i64 %not246}247 248define i32 @rol_i32(i32 %a, i32 %b) nounwind {249; RV32I-LABEL: rol_i32:250; RV32I: # %bb.0:251; RV32I-NEXT: sll a2, a0, a1252; RV32I-NEXT: neg a1, a1253; RV32I-NEXT: srl a0, a0, a1254; RV32I-NEXT: or a0, a2, a0255; RV32I-NEXT: ret256;257; RV32ZBB-ZBKB-LABEL: rol_i32:258; RV32ZBB-ZBKB: # %bb.0:259; RV32ZBB-ZBKB-NEXT: rol a0, a0, a1260; RV32ZBB-ZBKB-NEXT: ret261 %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)262 ret i32 %or263}264 265; This test is presented here in case future expansions of the Bitmanip266; extensions introduce instructions suitable for this pattern.267 268define i64 @rol_i64(i64 %a, i64 %b) nounwind {269; CHECK-LABEL: rol_i64:270; CHECK: # %bb.0:271; CHECK-NEXT: slli a5, a2, 26272; CHECK-NEXT: srli a5, a5, 31273; CHECK-NEXT: mv a3, a1274; CHECK-NEXT: bnez a5, .LBB13_2275; CHECK-NEXT: # %bb.1:276; CHECK-NEXT: mv a3, a0277; CHECK-NEXT: .LBB13_2:278; CHECK-NEXT: sll a4, a3, a2279; CHECK-NEXT: bnez a5, .LBB13_4280; CHECK-NEXT: # %bb.3:281; CHECK-NEXT: mv a0, a1282; CHECK-NEXT: .LBB13_4:283; CHECK-NEXT: srli a1, a0, 1284; CHECK-NEXT: not a5, a2285; CHECK-NEXT: sll a2, a0, a2286; CHECK-NEXT: srli a3, a3, 1287; CHECK-NEXT: srl a0, a1, a5288; CHECK-NEXT: srl a1, a3, a5289; CHECK-NEXT: or a0, a4, a0290; CHECK-NEXT: or a1, a2, a1291; CHECK-NEXT: ret292 %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)293 ret i64 %or294}295 296define i32 @ror_i32(i32 %a, i32 %b) nounwind {297; RV32I-LABEL: ror_i32:298; RV32I: # %bb.0:299; RV32I-NEXT: srl a2, a0, a1300; RV32I-NEXT: neg a1, a1301; RV32I-NEXT: sll a0, a0, a1302; RV32I-NEXT: or a0, a2, a0303; RV32I-NEXT: ret304;305; RV32ZBB-ZBKB-LABEL: ror_i32:306; RV32ZBB-ZBKB: # %bb.0:307; RV32ZBB-ZBKB-NEXT: ror a0, a0, a1308; RV32ZBB-ZBKB-NEXT: ret309 %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)310 ret i32 %or311}312 313; This test is presented here in case future expansions of the Bitmanip314; extensions introduce instructions suitable for this pattern.315 316define i64 @ror_i64(i64 %a, i64 %b) nounwind {317; CHECK-LABEL: ror_i64:318; CHECK: # %bb.0:319; CHECK-NEXT: andi a5, a2, 32320; CHECK-NEXT: mv a3, a0321; CHECK-NEXT: beqz a5, .LBB15_2322; CHECK-NEXT: # %bb.1:323; CHECK-NEXT: mv a3, a1324; CHECK-NEXT: .LBB15_2:325; CHECK-NEXT: srl a4, a3, a2326; CHECK-NEXT: beqz a5, .LBB15_4327; CHECK-NEXT: # %bb.3:328; CHECK-NEXT: mv a1, a0329; CHECK-NEXT: .LBB15_4:330; CHECK-NEXT: slli a0, a1, 1331; CHECK-NEXT: not a5, a2332; CHECK-NEXT: srl a1, a1, a2333; CHECK-NEXT: slli a3, a3, 1334; CHECK-NEXT: sll a0, a0, a5335; CHECK-NEXT: sll a2, a3, a5336; CHECK-NEXT: or a0, a0, a4337; CHECK-NEXT: or a1, a2, a1338; CHECK-NEXT: ret339 %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)340 ret i64 %or341}342 343define i32 @rori_i32_fshl(i32 %a) nounwind {344; RV32I-LABEL: rori_i32_fshl:345; RV32I: # %bb.0:346; RV32I-NEXT: srli a1, a0, 1347; RV32I-NEXT: slli a0, a0, 31348; RV32I-NEXT: or a0, a0, a1349; RV32I-NEXT: ret350;351; RV32ZBB-ZBKB-LABEL: rori_i32_fshl:352; RV32ZBB-ZBKB: # %bb.0:353; RV32ZBB-ZBKB-NEXT: rori a0, a0, 1354; RV32ZBB-ZBKB-NEXT: ret355 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31)356 ret i32 %1357}358 359define i32 @rori_i32_fshr(i32 %a) nounwind {360; RV32I-LABEL: rori_i32_fshr:361; RV32I: # %bb.0:362; RV32I-NEXT: slli a1, a0, 1363; RV32I-NEXT: srli a0, a0, 31364; RV32I-NEXT: or a0, a0, a1365; RV32I-NEXT: ret366;367; RV32ZBB-ZBKB-LABEL: rori_i32_fshr:368; RV32ZBB-ZBKB: # %bb.0:369; RV32ZBB-ZBKB-NEXT: rori a0, a0, 31370; RV32ZBB-ZBKB-NEXT: ret371 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)372 ret i32 %1373}374 375define i64 @rori_i64(i64 %a) nounwind {376; CHECK-LABEL: rori_i64:377; CHECK: # %bb.0:378; CHECK-NEXT: srli a2, a0, 1379; CHECK-NEXT: slli a3, a1, 31380; CHECK-NEXT: srli a1, a1, 1381; CHECK-NEXT: slli a4, a0, 31382; CHECK-NEXT: or a0, a3, a2383; CHECK-NEXT: or a1, a4, a1384; CHECK-NEXT: ret385 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63)386 ret i64 %1387}388 389define i64 @rori_i64_fshr(i64 %a) nounwind {390; CHECK-LABEL: rori_i64_fshr:391; CHECK: # %bb.0:392; CHECK-NEXT: srli a2, a1, 31393; CHECK-NEXT: slli a3, a0, 1394; CHECK-NEXT: srli a4, a0, 31395; CHECK-NEXT: slli a1, a1, 1396; CHECK-NEXT: or a0, a3, a2397; CHECK-NEXT: or a1, a1, a4398; CHECK-NEXT: ret399 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)400 ret i64 %1401}402 403define i32 @not_shl_one_i32(i32 %x) {404; RV32I-LABEL: not_shl_one_i32:405; RV32I: # %bb.0:406; RV32I-NEXT: li a1, 1407; RV32I-NEXT: sll a0, a1, a0408; RV32I-NEXT: not a0, a0409; RV32I-NEXT: ret410;411; RV32ZBB-ZBKB-LABEL: not_shl_one_i32:412; RV32ZBB-ZBKB: # %bb.0:413; RV32ZBB-ZBKB-NEXT: li a1, -2414; RV32ZBB-ZBKB-NEXT: rol a0, a1, a0415; RV32ZBB-ZBKB-NEXT: ret416 %1 = shl i32 1, %x417 %2 = xor i32 %1, -1418 ret i32 %2419}420 421define i64 @not_shl_one_i64(i64 %x) {422; CHECK-LABEL: not_shl_one_i64:423; CHECK: # %bb.0:424; CHECK-NEXT: addi a1, a0, -32425; CHECK-NEXT: li a2, 1426; CHECK-NEXT: srli a1, a1, 31427; CHECK-NEXT: sll a0, a2, a0428; CHECK-NEXT: neg a2, a1429; CHECK-NEXT: addi a1, a1, -1430; CHECK-NEXT: and a2, a2, a0431; CHECK-NEXT: and a1, a1, a0432; CHECK-NEXT: not a0, a2433; CHECK-NEXT: not a1, a1434; CHECK-NEXT: ret435 %1 = shl i64 1, %x436 %2 = xor i64 %1, -1437 ret i64 %2438}439 440define i8 @srli_i8(i8 %a) nounwind {441; CHECK-LABEL: srli_i8:442; CHECK: # %bb.0:443; CHECK-NEXT: slli a0, a0, 24444; CHECK-NEXT: srli a0, a0, 30445; CHECK-NEXT: ret446 %1 = lshr i8 %a, 6447 ret i8 %1448}449 450; We could use sext.b+srai, but slli+srai offers more opportunities for451; comppressed instructions.452define i8 @srai_i8(i8 %a) nounwind {453; CHECK-LABEL: srai_i8:454; CHECK: # %bb.0:455; CHECK-NEXT: slli a0, a0, 24456; CHECK-NEXT: srai a0, a0, 29457; CHECK-NEXT: ret458 %1 = ashr i8 %a, 5459 ret i8 %1460}461 462; We could use zext.h+srli, but slli+srli offers more opportunities for463; comppressed instructions.464define i16 @srli_i16(i16 %a) nounwind {465; CHECK-LABEL: srli_i16:466; CHECK: # %bb.0:467; CHECK-NEXT: slli a0, a0, 16468; CHECK-NEXT: srli a0, a0, 22469; CHECK-NEXT: ret470 %1 = lshr i16 %a, 6471 ret i16 %1472}473 474; We could use sext.h+srai, but slli+srai offers more opportunities for475; comppressed instructions.476define i16 @srai_i16(i16 %a) nounwind {477; CHECK-LABEL: srai_i16:478; CHECK: # %bb.0:479; CHECK-NEXT: slli a0, a0, 16480; CHECK-NEXT: srai a0, a0, 25481; CHECK-NEXT: ret482 %1 = ashr i16 %a, 9483 ret i16 %1484}485 486define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {487; RV32I-LABEL: andn_seqz_i32:488; RV32I: # %bb.0:489; RV32I-NEXT: and a0, a0, a1490; RV32I-NEXT: xor a0, a0, a1491; RV32I-NEXT: seqz a0, a0492; RV32I-NEXT: ret493;494; RV32ZBB-ZBKB-LABEL: andn_seqz_i32:495; RV32ZBB-ZBKB: # %bb.0:496; RV32ZBB-ZBKB-NEXT: andn a0, a1, a0497; RV32ZBB-ZBKB-NEXT: seqz a0, a0498; RV32ZBB-ZBKB-NEXT: ret499 %and = and i32 %a, %b500 %cmpeq = icmp eq i32 %and, %b501 ret i1 %cmpeq502}503 504define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {505; RV32I-LABEL: andn_seqz_i64:506; RV32I: # %bb.0:507; RV32I-NEXT: not a0, a0508; RV32I-NEXT: not a1, a1509; RV32I-NEXT: and a1, a1, a3510; RV32I-NEXT: and a0, a0, a2511; RV32I-NEXT: or a0, a0, a1512; RV32I-NEXT: seqz a0, a0513; RV32I-NEXT: ret514;515; RV32ZBB-ZBKB-LABEL: andn_seqz_i64:516; RV32ZBB-ZBKB: # %bb.0:517; RV32ZBB-ZBKB-NEXT: andn a1, a3, a1518; RV32ZBB-ZBKB-NEXT: andn a0, a2, a0519; RV32ZBB-ZBKB-NEXT: or a0, a0, a1520; RV32ZBB-ZBKB-NEXT: seqz a0, a0521; RV32ZBB-ZBKB-NEXT: ret522 %and = and i64 %a, %b523 %cmpeq = icmp eq i64 %and, %b524 ret i1 %cmpeq525}526 527define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {528; RV32I-LABEL: andn_snez_i32:529; RV32I: # %bb.0:530; RV32I-NEXT: and a0, a0, a1531; RV32I-NEXT: xor a0, a0, a1532; RV32I-NEXT: snez a0, a0533; RV32I-NEXT: ret534;535; RV32ZBB-ZBKB-LABEL: andn_snez_i32:536; RV32ZBB-ZBKB: # %bb.0:537; RV32ZBB-ZBKB-NEXT: andn a0, a1, a0538; RV32ZBB-ZBKB-NEXT: snez a0, a0539; RV32ZBB-ZBKB-NEXT: ret540 %and = and i32 %a, %b541 %cmpeq = icmp ne i32 %and, %b542 ret i1 %cmpeq543}544 545define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {546; RV32I-LABEL: andn_snez_i64:547; RV32I: # %bb.0:548; RV32I-NEXT: not a0, a0549; RV32I-NEXT: not a1, a1550; RV32I-NEXT: and a1, a1, a3551; RV32I-NEXT: and a0, a0, a2552; RV32I-NEXT: or a0, a0, a1553; RV32I-NEXT: snez a0, a0554; RV32I-NEXT: ret555;556; RV32ZBB-ZBKB-LABEL: andn_snez_i64:557; RV32ZBB-ZBKB: # %bb.0:558; RV32ZBB-ZBKB-NEXT: andn a1, a3, a1559; RV32ZBB-ZBKB-NEXT: andn a0, a2, a0560; RV32ZBB-ZBKB-NEXT: or a0, a0, a1561; RV32ZBB-ZBKB-NEXT: snez a0, a0562; RV32ZBB-ZBKB-NEXT: ret563 %and = and i64 %a, %b564 %cmpeq = icmp ne i64 %and, %b565 ret i1 %cmpeq566}567 568define i32 @and_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {569; RV32I-LABEL: and_hoisted_not_i32:570; RV32I: # %bb.0:571; RV32I-NEXT: beqz a2, .LBB30_2572; RV32I-NEXT: # %bb.1: # %mask573; RV32I-NEXT: not a1, a1574; RV32I-NEXT: and a0, a1, a0575; RV32I-NEXT: .LBB30_2: # %identity576; RV32I-NEXT: ret577;578; RV32ZBB-ZBKB-LABEL: and_hoisted_not_i32:579; RV32ZBB-ZBKB: # %bb.0:580; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB30_2581; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask582; RV32ZBB-ZBKB-NEXT: andn a0, a0, a1583; RV32ZBB-ZBKB-NEXT: .LBB30_2: # %identity584; RV32ZBB-ZBKB-NEXT: ret585 %a = xor i32 %m, -1586 br i1 %cond, label %mask, label %identity587 588mask:589 %masked = and i32 %a, %x590 ret i32 %masked591 592identity:593 ret i32 %x594}595 596define i32 @and_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {597; RV32I-LABEL: and_hoisted_not_i32_swapped:598; RV32I: # %bb.0:599; RV32I-NEXT: beqz a2, .LBB31_2600; RV32I-NEXT: # %bb.1: # %mask601; RV32I-NEXT: not a1, a1602; RV32I-NEXT: and a0, a0, a1603; RV32I-NEXT: .LBB31_2: # %identity604; RV32I-NEXT: ret605;606; RV32ZBB-ZBKB-LABEL: and_hoisted_not_i32_swapped:607; RV32ZBB-ZBKB: # %bb.0:608; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB31_2609; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask610; RV32ZBB-ZBKB-NEXT: andn a0, a0, a1611; RV32ZBB-ZBKB-NEXT: .LBB31_2: # %identity612; RV32ZBB-ZBKB-NEXT: ret613 %a = xor i32 %m, -1614 br i1 %cond, label %mask, label %identity615 616mask:617 %masked = and i32 %x, %a618 ret i32 %masked619 620identity:621 ret i32 %x622}623 624define i64 @and_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {625; RV32I-LABEL: and_hoisted_not_i64:626; RV32I: # %bb.0:627; RV32I-NEXT: beqz a4, .LBB32_2628; RV32I-NEXT: # %bb.1: # %mask629; RV32I-NEXT: not a3, a3630; RV32I-NEXT: not a2, a2631; RV32I-NEXT: and a0, a2, a0632; RV32I-NEXT: and a1, a3, a1633; RV32I-NEXT: .LBB32_2: # %identity634; RV32I-NEXT: ret635;636; RV32ZBB-ZBKB-LABEL: and_hoisted_not_i64:637; RV32ZBB-ZBKB: # %bb.0:638; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB32_2639; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask640; RV32ZBB-ZBKB-NEXT: andn a0, a0, a2641; RV32ZBB-ZBKB-NEXT: andn a1, a1, a3642; RV32ZBB-ZBKB-NEXT: .LBB32_2: # %identity643; RV32ZBB-ZBKB-NEXT: ret644 %a = xor i64 %m, -1645 br i1 %cond, label %mask, label %identity646 647mask:648 %masked = and i64 %a, %x649 ret i64 %masked650 651identity:652 ret i64 %x653}654 655define i64 @and_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {656; RV32I-LABEL: and_hoisted_not_i64_swapped:657; RV32I: # %bb.0:658; RV32I-NEXT: beqz a4, .LBB33_2659; RV32I-NEXT: # %bb.1: # %mask660; RV32I-NEXT: not a3, a3661; RV32I-NEXT: not a2, a2662; RV32I-NEXT: and a0, a0, a2663; RV32I-NEXT: and a1, a1, a3664; RV32I-NEXT: .LBB33_2: # %identity665; RV32I-NEXT: ret666;667; RV32ZBB-ZBKB-LABEL: and_hoisted_not_i64_swapped:668; RV32ZBB-ZBKB: # %bb.0:669; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB33_2670; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask671; RV32ZBB-ZBKB-NEXT: andn a0, a0, a2672; RV32ZBB-ZBKB-NEXT: andn a1, a1, a3673; RV32ZBB-ZBKB-NEXT: .LBB33_2: # %identity674; RV32ZBB-ZBKB-NEXT: ret675 %a = xor i64 %m, -1676 br i1 %cond, label %mask, label %identity677 678mask:679 %masked = and i64 %x, %a680 ret i64 %masked681 682identity:683 ret i64 %x684}685 686define i32 @or_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {687; RV32I-LABEL: or_hoisted_not_i32:688; RV32I: # %bb.0:689; RV32I-NEXT: beqz a2, .LBB34_2690; RV32I-NEXT: # %bb.1: # %mask691; RV32I-NEXT: not a1, a1692; RV32I-NEXT: or a0, a1, a0693; RV32I-NEXT: .LBB34_2: # %identity694; RV32I-NEXT: ret695;696; RV32ZBB-ZBKB-LABEL: or_hoisted_not_i32:697; RV32ZBB-ZBKB: # %bb.0:698; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB34_2699; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask700; RV32ZBB-ZBKB-NEXT: orn a0, a0, a1701; RV32ZBB-ZBKB-NEXT: .LBB34_2: # %identity702; RV32ZBB-ZBKB-NEXT: ret703 %a = xor i32 %m, -1704 br i1 %cond, label %mask, label %identity705 706mask:707 %masked = or i32 %a, %x708 ret i32 %masked709 710identity:711 ret i32 %x712}713 714define i32 @or_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {715; RV32I-LABEL: or_hoisted_not_i32_swapped:716; RV32I: # %bb.0:717; RV32I-NEXT: beqz a2, .LBB35_2718; RV32I-NEXT: # %bb.1: # %mask719; RV32I-NEXT: not a1, a1720; RV32I-NEXT: or a0, a0, a1721; RV32I-NEXT: .LBB35_2: # %identity722; RV32I-NEXT: ret723;724; RV32ZBB-ZBKB-LABEL: or_hoisted_not_i32_swapped:725; RV32ZBB-ZBKB: # %bb.0:726; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB35_2727; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask728; RV32ZBB-ZBKB-NEXT: orn a0, a0, a1729; RV32ZBB-ZBKB-NEXT: .LBB35_2: # %identity730; RV32ZBB-ZBKB-NEXT: ret731 %a = xor i32 %m, -1732 br i1 %cond, label %mask, label %identity733 734mask:735 %masked = or i32 %x, %a736 ret i32 %masked737 738identity:739 ret i32 %x740}741 742define i64 @or_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {743; RV32I-LABEL: or_hoisted_not_i64:744; RV32I: # %bb.0:745; RV32I-NEXT: beqz a4, .LBB36_2746; RV32I-NEXT: # %bb.1: # %mask747; RV32I-NEXT: not a3, a3748; RV32I-NEXT: not a2, a2749; RV32I-NEXT: or a0, a2, a0750; RV32I-NEXT: or a1, a3, a1751; RV32I-NEXT: .LBB36_2: # %identity752; RV32I-NEXT: ret753;754; RV32ZBB-ZBKB-LABEL: or_hoisted_not_i64:755; RV32ZBB-ZBKB: # %bb.0:756; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB36_2757; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask758; RV32ZBB-ZBKB-NEXT: orn a0, a0, a2759; RV32ZBB-ZBKB-NEXT: orn a1, a1, a3760; RV32ZBB-ZBKB-NEXT: .LBB36_2: # %identity761; RV32ZBB-ZBKB-NEXT: ret762 %a = xor i64 %m, -1763 br i1 %cond, label %mask, label %identity764 765mask:766 %masked = or i64 %a, %x767 ret i64 %masked768 769identity:770 ret i64 %x771}772 773define i64 @or_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {774; RV32I-LABEL: or_hoisted_not_i64_swapped:775; RV32I: # %bb.0:776; RV32I-NEXT: beqz a4, .LBB37_2777; RV32I-NEXT: # %bb.1: # %mask778; RV32I-NEXT: not a3, a3779; RV32I-NEXT: not a2, a2780; RV32I-NEXT: or a0, a0, a2781; RV32I-NEXT: or a1, a1, a3782; RV32I-NEXT: .LBB37_2: # %identity783; RV32I-NEXT: ret784;785; RV32ZBB-ZBKB-LABEL: or_hoisted_not_i64_swapped:786; RV32ZBB-ZBKB: # %bb.0:787; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB37_2788; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask789; RV32ZBB-ZBKB-NEXT: orn a0, a0, a2790; RV32ZBB-ZBKB-NEXT: orn a1, a1, a3791; RV32ZBB-ZBKB-NEXT: .LBB37_2: # %identity792; RV32ZBB-ZBKB-NEXT: ret793 %a = xor i64 %m, -1794 br i1 %cond, label %mask, label %identity795 796mask:797 %masked = or i64 %x, %a798 ret i64 %masked799 800identity:801 ret i64 %x802}803 804define i32 @xor_hoisted_not_i32(i32 %x, i32 %m, i1 zeroext %cond) {805; RV32I-LABEL: xor_hoisted_not_i32:806; RV32I: # %bb.0:807; RV32I-NEXT: beqz a2, .LBB38_2808; RV32I-NEXT: # %bb.1: # %mask809; RV32I-NEXT: not a1, a1810; RV32I-NEXT: xor a0, a1, a0811; RV32I-NEXT: .LBB38_2: # %identity812; RV32I-NEXT: ret813;814; RV32ZBB-ZBKB-LABEL: xor_hoisted_not_i32:815; RV32ZBB-ZBKB: # %bb.0:816; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB38_2817; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask818; RV32ZBB-ZBKB-NEXT: xnor a0, a1, a0819; RV32ZBB-ZBKB-NEXT: .LBB38_2: # %identity820; RV32ZBB-ZBKB-NEXT: ret821 %a = xor i32 %m, -1822 br i1 %cond, label %mask, label %identity823 824mask:825 %masked = xor i32 %a, %x826 ret i32 %masked827 828identity:829 ret i32 %x830}831 832define i32 @xor_hoisted_not_i32_swapped(i32 %x, i32 %m, i1 zeroext %cond) {833; RV32I-LABEL: xor_hoisted_not_i32_swapped:834; RV32I: # %bb.0:835; RV32I-NEXT: beqz a2, .LBB39_2836; RV32I-NEXT: # %bb.1: # %mask837; RV32I-NEXT: not a1, a1838; RV32I-NEXT: xor a0, a0, a1839; RV32I-NEXT: .LBB39_2: # %identity840; RV32I-NEXT: ret841;842; RV32ZBB-ZBKB-LABEL: xor_hoisted_not_i32_swapped:843; RV32ZBB-ZBKB: # %bb.0:844; RV32ZBB-ZBKB-NEXT: beqz a2, .LBB39_2845; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask846; RV32ZBB-ZBKB-NEXT: xnor a0, a1, a0847; RV32ZBB-ZBKB-NEXT: .LBB39_2: # %identity848; RV32ZBB-ZBKB-NEXT: ret849 %a = xor i32 %m, -1850 br i1 %cond, label %mask, label %identity851 852mask:853 %masked = xor i32 %x, %a854 ret i32 %masked855 856identity:857 ret i32 %x858}859 860define i64 @xor_hoisted_not_i64(i64 %x, i64 %m, i1 zeroext %cond) {861; RV32I-LABEL: xor_hoisted_not_i64:862; RV32I: # %bb.0:863; RV32I-NEXT: beqz a4, .LBB40_2864; RV32I-NEXT: # %bb.1: # %mask865; RV32I-NEXT: not a3, a3866; RV32I-NEXT: not a2, a2867; RV32I-NEXT: xor a0, a2, a0868; RV32I-NEXT: xor a1, a3, a1869; RV32I-NEXT: .LBB40_2: # %identity870; RV32I-NEXT: ret871;872; RV32ZBB-ZBKB-LABEL: xor_hoisted_not_i64:873; RV32ZBB-ZBKB: # %bb.0:874; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB40_2875; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask876; RV32ZBB-ZBKB-NEXT: xnor a0, a2, a0877; RV32ZBB-ZBKB-NEXT: xnor a1, a3, a1878; RV32ZBB-ZBKB-NEXT: .LBB40_2: # %identity879; RV32ZBB-ZBKB-NEXT: ret880 %a = xor i64 %m, -1881 br i1 %cond, label %mask, label %identity882 883mask:884 %masked = xor i64 %a, %x885 ret i64 %masked886 887identity:888 ret i64 %x889}890 891define i64 @xor_hoisted_not_i64_swapped(i64 %x, i64 %m, i1 zeroext %cond) {892; RV32I-LABEL: xor_hoisted_not_i64_swapped:893; RV32I: # %bb.0:894; RV32I-NEXT: beqz a4, .LBB41_2895; RV32I-NEXT: # %bb.1: # %mask896; RV32I-NEXT: not a3, a3897; RV32I-NEXT: not a2, a2898; RV32I-NEXT: xor a0, a0, a2899; RV32I-NEXT: xor a1, a1, a3900; RV32I-NEXT: .LBB41_2: # %identity901; RV32I-NEXT: ret902;903; RV32ZBB-ZBKB-LABEL: xor_hoisted_not_i64_swapped:904; RV32ZBB-ZBKB: # %bb.0:905; RV32ZBB-ZBKB-NEXT: beqz a4, .LBB41_2906; RV32ZBB-ZBKB-NEXT: # %bb.1: # %mask907; RV32ZBB-ZBKB-NEXT: xnor a0, a2, a0908; RV32ZBB-ZBKB-NEXT: xnor a1, a3, a1909; RV32ZBB-ZBKB-NEXT: .LBB41_2: # %identity910; RV32ZBB-ZBKB-NEXT: ret911 %a = xor i64 %m, -1912 br i1 %cond, label %mask, label %identity913 914mask:915 %masked = xor i64 %x, %a916 ret i64 %masked917 918identity:919 ret i64 %x920}921