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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB6 7define i32 @ctlz_i32(i32 %a) nounwind {8; RV32I-LABEL: ctlz_i32:9; RV32I: # %bb.0:10; RV32I-NEXT: beqz a0, .LBB0_211; RV32I-NEXT: # %bb.1: # %cond.false12; RV32I-NEXT: srli a1, a0, 113; RV32I-NEXT: lui a2, 34952514; RV32I-NEXT: or a0, a0, a115; RV32I-NEXT: addi a1, a2, 136516; RV32I-NEXT: srli a2, a0, 217; RV32I-NEXT: or a0, a0, a218; RV32I-NEXT: srli a2, a0, 419; RV32I-NEXT: or a0, a0, a220; RV32I-NEXT: srli a2, a0, 821; RV32I-NEXT: or a0, a0, a222; RV32I-NEXT: srli a2, a0, 1623; RV32I-NEXT: or a0, a0, a224; RV32I-NEXT: not a0, a025; RV32I-NEXT: srli a2, a0, 126; RV32I-NEXT: and a1, a2, a127; RV32I-NEXT: lui a2, 20971528; RV32I-NEXT: addi a2, a2, 81929; RV32I-NEXT: sub a0, a0, a130; RV32I-NEXT: and a1, a0, a231; RV32I-NEXT: srli a0, a0, 232; RV32I-NEXT: and a0, a0, a233; RV32I-NEXT: lui a2, 6168134; RV32I-NEXT: add a0, a1, a035; RV32I-NEXT: srli a1, a0, 436; RV32I-NEXT: add a0, a0, a137; RV32I-NEXT: addi a1, a2, -24138; RV32I-NEXT: and a0, a0, a139; RV32I-NEXT: slli a1, a0, 840; RV32I-NEXT: add a0, a0, a141; RV32I-NEXT: slli a1, a0, 1642; RV32I-NEXT: add a0, a0, a143; RV32I-NEXT: srli a0, a0, 2444; RV32I-NEXT: ret45; RV32I-NEXT: .LBB0_2:46; RV32I-NEXT: li a0, 3247; RV32I-NEXT: ret48;49; RV32ZBB-LABEL: ctlz_i32:50; RV32ZBB: # %bb.0:51; RV32ZBB-NEXT: clz a0, a052; RV32ZBB-NEXT: ret53 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)54 ret i32 %155}56 57define i64 @ctlz_i64(i64 %a) nounwind {58; RV32I-LABEL: ctlz_i64:59; RV32I: # %bb.0:60; RV32I-NEXT: or a2, a0, a161; RV32I-NEXT: beqz a2, .LBB1_362; RV32I-NEXT: # %bb.1: # %cond.false63; RV32I-NEXT: lui a2, 34952564; RV32I-NEXT: lui a3, 20971565; RV32I-NEXT: lui a5, 6168166; RV32I-NEXT: addi a4, a2, 136567; RV32I-NEXT: addi a3, a3, 81968; RV32I-NEXT: addi a2, a5, -24169; RV32I-NEXT: bnez a1, .LBB1_470; RV32I-NEXT: # %bb.2: # %cond.false71; RV32I-NEXT: srli a1, a0, 172; RV32I-NEXT: or a0, a0, a173; RV32I-NEXT: srli a1, a0, 274; RV32I-NEXT: or a0, a0, a175; RV32I-NEXT: srli a1, a0, 476; RV32I-NEXT: or a0, a0, a177; RV32I-NEXT: srli a1, a0, 878; RV32I-NEXT: or a0, a0, a179; RV32I-NEXT: srli a1, a0, 1680; RV32I-NEXT: or a0, a0, a181; RV32I-NEXT: not a0, a082; RV32I-NEXT: srli a1, a0, 183; RV32I-NEXT: and a1, a1, a484; RV32I-NEXT: sub a0, a0, a185; RV32I-NEXT: and a1, a0, a386; RV32I-NEXT: srli a0, a0, 287; RV32I-NEXT: and a0, a0, a388; RV32I-NEXT: add a0, a1, a089; RV32I-NEXT: srli a1, a0, 490; RV32I-NEXT: add a0, a0, a191; RV32I-NEXT: and a0, a0, a292; RV32I-NEXT: slli a1, a0, 893; RV32I-NEXT: add a0, a0, a194; RV32I-NEXT: slli a1, a0, 1695; RV32I-NEXT: add a0, a0, a196; RV32I-NEXT: srli a0, a0, 2497; RV32I-NEXT: addi a0, a0, 3298; RV32I-NEXT: li a1, 099; RV32I-NEXT: ret100; RV32I-NEXT: .LBB1_3:101; RV32I-NEXT: li a1, 0102; RV32I-NEXT: li a0, 64103; RV32I-NEXT: ret104; RV32I-NEXT: .LBB1_4:105; RV32I-NEXT: srli a0, a1, 1106; RV32I-NEXT: or a0, a1, a0107; RV32I-NEXT: srli a1, a0, 2108; RV32I-NEXT: or a0, a0, a1109; RV32I-NEXT: srli a1, a0, 4110; RV32I-NEXT: or a0, a0, a1111; RV32I-NEXT: srli a1, a0, 8112; RV32I-NEXT: or a0, a0, a1113; RV32I-NEXT: srli a1, a0, 16114; RV32I-NEXT: or a0, a0, a1115; RV32I-NEXT: not a0, a0116; RV32I-NEXT: srli a1, a0, 1117; RV32I-NEXT: and a1, a1, a4118; RV32I-NEXT: sub a0, a0, a1119; RV32I-NEXT: and a1, a0, a3120; RV32I-NEXT: srli a0, a0, 2121; RV32I-NEXT: and a0, a0, a3122; RV32I-NEXT: add a0, a1, a0123; RV32I-NEXT: srli a1, a0, 4124; RV32I-NEXT: add a0, a0, a1125; RV32I-NEXT: and a0, a0, a2126; RV32I-NEXT: slli a1, a0, 8127; RV32I-NEXT: add a0, a0, a1128; RV32I-NEXT: slli a1, a0, 16129; RV32I-NEXT: add a0, a0, a1130; RV32I-NEXT: srli a0, a0, 24131; RV32I-NEXT: li a1, 0132; RV32I-NEXT: ret133;134; RV32ZBB-LABEL: ctlz_i64:135; RV32ZBB: # %bb.0:136; RV32ZBB-NEXT: bnez a1, .LBB1_2137; RV32ZBB-NEXT: # %bb.1:138; RV32ZBB-NEXT: clz a0, a0139; RV32ZBB-NEXT: addi a0, a0, 32140; RV32ZBB-NEXT: li a1, 0141; RV32ZBB-NEXT: ret142; RV32ZBB-NEXT: .LBB1_2:143; RV32ZBB-NEXT: clz a0, a1144; RV32ZBB-NEXT: li a1, 0145; RV32ZBB-NEXT: ret146 %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)147 ret i64 %1148}149 150define i32 @cttz_i32(i32 %a) nounwind {151; RV32I-LABEL: cttz_i32:152; RV32I: # %bb.0:153; RV32I-NEXT: beqz a0, .LBB2_2154; RV32I-NEXT: # %bb.1: # %cond.false155; RV32I-NEXT: addi sp, sp, -16156; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill157; RV32I-NEXT: neg a1, a0158; RV32I-NEXT: and a0, a0, a1159; RV32I-NEXT: lui a1, 30667160; RV32I-NEXT: addi a1, a1, 1329161; RV32I-NEXT: call __mulsi3162; RV32I-NEXT: srli a0, a0, 27163; RV32I-NEXT: lui a1, %hi(.LCPI2_0)164; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0)165; RV32I-NEXT: add a0, a1, a0166; RV32I-NEXT: lbu a0, 0(a0)167; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload168; RV32I-NEXT: addi sp, sp, 16169; RV32I-NEXT: ret170; RV32I-NEXT: .LBB2_2:171; RV32I-NEXT: li a0, 32172; RV32I-NEXT: ret173;174; RV32ZBB-LABEL: cttz_i32:175; RV32ZBB: # %bb.0:176; RV32ZBB-NEXT: ctz a0, a0177; RV32ZBB-NEXT: ret178 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)179 ret i32 %1180}181 182define i64 @cttz_i64(i64 %a) nounwind {183; RV32I-LABEL: cttz_i64:184; RV32I: # %bb.0:185; RV32I-NEXT: addi sp, sp, -32186; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill187; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill188; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill189; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill190; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill191; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill192; RV32I-NEXT: mv s0, a1193; RV32I-NEXT: or a1, a0, a1194; RV32I-NEXT: beqz a1, .LBB3_3195; RV32I-NEXT: # %bb.1: # %cond.false196; RV32I-NEXT: neg a1, a0197; RV32I-NEXT: and a1, a0, a1198; RV32I-NEXT: lui s2, 30667199; RV32I-NEXT: addi s2, s2, 1329200; RV32I-NEXT: mv s4, a0201; RV32I-NEXT: mv a0, a1202; RV32I-NEXT: mv a1, s2203; RV32I-NEXT: call __mulsi3204; RV32I-NEXT: mv s1, a0205; RV32I-NEXT: lui s3, %hi(.LCPI3_0)206; RV32I-NEXT: addi s3, s3, %lo(.LCPI3_0)207; RV32I-NEXT: neg a0, s0208; RV32I-NEXT: and a0, s0, a0209; RV32I-NEXT: mv a1, s2210; RV32I-NEXT: call __mulsi3211; RV32I-NEXT: bnez s4, .LBB3_4212; RV32I-NEXT: # %bb.2: # %cond.false213; RV32I-NEXT: srli a0, a0, 27214; RV32I-NEXT: add a0, s3, a0215; RV32I-NEXT: lbu a0, 0(a0)216; RV32I-NEXT: addi a0, a0, 32217; RV32I-NEXT: j .LBB3_5218; RV32I-NEXT: .LBB3_3:219; RV32I-NEXT: li a0, 64220; RV32I-NEXT: j .LBB3_6221; RV32I-NEXT: .LBB3_4:222; RV32I-NEXT: srli s1, s1, 27223; RV32I-NEXT: add s1, s3, s1224; RV32I-NEXT: lbu a0, 0(s1)225; RV32I-NEXT: .LBB3_5: # %cond.false226; RV32I-NEXT: li a1, 0227; RV32I-NEXT: .LBB3_6: # %cond.end228; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload229; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload230; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload231; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload232; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload233; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload234; RV32I-NEXT: addi sp, sp, 32235; RV32I-NEXT: ret236;237; RV32ZBB-LABEL: cttz_i64:238; RV32ZBB: # %bb.0:239; RV32ZBB-NEXT: bnez a0, .LBB3_2240; RV32ZBB-NEXT: # %bb.1:241; RV32ZBB-NEXT: ctz a0, a1242; RV32ZBB-NEXT: addi a0, a0, 32243; RV32ZBB-NEXT: li a1, 0244; RV32ZBB-NEXT: ret245; RV32ZBB-NEXT: .LBB3_2:246; RV32ZBB-NEXT: ctz a0, a0247; RV32ZBB-NEXT: li a1, 0248; RV32ZBB-NEXT: ret249 %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)250 ret i64 %1251}252 253define i32 @ctpop_i32(i32 %a) nounwind {254; RV32I-LABEL: ctpop_i32:255; RV32I: # %bb.0:256; RV32I-NEXT: srli a1, a0, 1257; RV32I-NEXT: lui a2, 349525258; RV32I-NEXT: addi a2, a2, 1365259; RV32I-NEXT: and a1, a1, a2260; RV32I-NEXT: lui a2, 209715261; RV32I-NEXT: addi a2, a2, 819262; RV32I-NEXT: sub a0, a0, a1263; RV32I-NEXT: and a1, a0, a2264; RV32I-NEXT: srli a0, a0, 2265; RV32I-NEXT: and a0, a0, a2266; RV32I-NEXT: lui a2, 61681267; RV32I-NEXT: add a0, a1, a0268; RV32I-NEXT: srli a1, a0, 4269; RV32I-NEXT: add a0, a0, a1270; RV32I-NEXT: addi a1, a2, -241271; RV32I-NEXT: and a0, a0, a1272; RV32I-NEXT: slli a1, a0, 8273; RV32I-NEXT: add a0, a0, a1274; RV32I-NEXT: slli a1, a0, 16275; RV32I-NEXT: add a0, a0, a1276; RV32I-NEXT: srli a0, a0, 24277; RV32I-NEXT: ret278;279; RV32ZBB-LABEL: ctpop_i32:280; RV32ZBB: # %bb.0:281; RV32ZBB-NEXT: cpop a0, a0282; RV32ZBB-NEXT: ret283 %1 = call i32 @llvm.ctpop.i32(i32 %a)284 ret i32 %1285}286 287define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {288; RV32I-LABEL: ctpop_i32_ult_two:289; RV32I: # %bb.0:290; RV32I-NEXT: addi a1, a0, -1291; RV32I-NEXT: and a0, a0, a1292; RV32I-NEXT: seqz a0, a0293; RV32I-NEXT: ret294;295; RV32ZBB-LABEL: ctpop_i32_ult_two:296; RV32ZBB: # %bb.0:297; RV32ZBB-NEXT: cpop a0, a0298; RV32ZBB-NEXT: sltiu a0, a0, 2299; RV32ZBB-NEXT: ret300 %1 = call i32 @llvm.ctpop.i32(i32 %a)301 %2 = icmp ult i32 %1, 2302 ret i1 %2303}304 305define i1 @ctpop_i32_ugt_one(i32 signext %a) nounwind {306; RV32I-LABEL: ctpop_i32_ugt_one:307; RV32I: # %bb.0:308; RV32I-NEXT: addi a1, a0, -1309; RV32I-NEXT: and a0, a0, a1310; RV32I-NEXT: snez a0, a0311; RV32I-NEXT: ret312;313; RV32ZBB-LABEL: ctpop_i32_ugt_one:314; RV32ZBB: # %bb.0:315; RV32ZBB-NEXT: cpop a0, a0316; RV32ZBB-NEXT: sltiu a0, a0, 2317; RV32ZBB-NEXT: xori a0, a0, 1318; RV32ZBB-NEXT: ret319 %1 = call i32 @llvm.ctpop.i32(i32 %a)320 %2 = icmp ugt i32 %1, 1321 ret i1 %2322}323 324define i1 @ctpop_i32_eq_one(i32 signext %a) nounwind {325; RV32I-LABEL: ctpop_i32_eq_one:326; RV32I: # %bb.0:327; RV32I-NEXT: addi a1, a0, -1328; RV32I-NEXT: xor a0, a0, a1329; RV32I-NEXT: sltu a0, a1, a0330; RV32I-NEXT: ret331;332; RV32ZBB-LABEL: ctpop_i32_eq_one:333; RV32ZBB: # %bb.0:334; RV32ZBB-NEXT: cpop a0, a0335; RV32ZBB-NEXT: addi a0, a0, -1336; RV32ZBB-NEXT: seqz a0, a0337; RV32ZBB-NEXT: ret338 %1 = call i32 @llvm.ctpop.i32(i32 %a)339 %2 = icmp eq i32 %1, 1340 ret i1 %2341}342 343define i1 @ctpop_i32_ne_one(i32 signext %a) nounwind {344; RV32I-LABEL: ctpop_i32_ne_one:345; RV32I: # %bb.0:346; RV32I-NEXT: addi a1, a0, -1347; RV32I-NEXT: xor a0, a0, a1348; RV32I-NEXT: sltu a0, a1, a0349; RV32I-NEXT: xori a0, a0, 1350; RV32I-NEXT: ret351;352; RV32ZBB-LABEL: ctpop_i32_ne_one:353; RV32ZBB: # %bb.0:354; RV32ZBB-NEXT: cpop a0, a0355; RV32ZBB-NEXT: addi a0, a0, -1356; RV32ZBB-NEXT: snez a0, a0357; RV32ZBB-NEXT: ret358 %1 = call i32 @llvm.ctpop.i32(i32 %a)359 %2 = icmp ne i32 %1, 1360 ret i1 %2361}362 363define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind {364; RV32I-LABEL: ctpop_v2i32:365; RV32I: # %bb.0:366; RV32I-NEXT: srli a2, a0, 1367; RV32I-NEXT: lui a3, 349525368; RV32I-NEXT: lui a4, 209715369; RV32I-NEXT: srli a5, a1, 1370; RV32I-NEXT: addi a3, a3, 1365371; RV32I-NEXT: and a2, a2, a3372; RV32I-NEXT: and a3, a5, a3373; RV32I-NEXT: lui a5, 61681374; RV32I-NEXT: addi a4, a4, 819375; RV32I-NEXT: addi a5, a5, -241376; RV32I-NEXT: sub a0, a0, a2377; RV32I-NEXT: sub a1, a1, a3378; RV32I-NEXT: and a2, a0, a4379; RV32I-NEXT: srli a0, a0, 2380; RV32I-NEXT: and a3, a1, a4381; RV32I-NEXT: srli a1, a1, 2382; RV32I-NEXT: and a0, a0, a4383; RV32I-NEXT: and a1, a1, a4384; RV32I-NEXT: add a0, a2, a0385; RV32I-NEXT: add a1, a3, a1386; RV32I-NEXT: srli a2, a0, 4387; RV32I-NEXT: srli a3, a1, 4388; RV32I-NEXT: add a0, a0, a2389; RV32I-NEXT: add a1, a1, a3390; RV32I-NEXT: and a0, a0, a5391; RV32I-NEXT: and a1, a1, a5392; RV32I-NEXT: slli a2, a0, 8393; RV32I-NEXT: slli a3, a1, 8394; RV32I-NEXT: add a0, a0, a2395; RV32I-NEXT: add a1, a1, a3396; RV32I-NEXT: slli a2, a0, 16397; RV32I-NEXT: slli a3, a1, 16398; RV32I-NEXT: add a0, a0, a2399; RV32I-NEXT: add a1, a1, a3400; RV32I-NEXT: srli a0, a0, 24401; RV32I-NEXT: srli a1, a1, 24402; RV32I-NEXT: ret403;404; RV32ZBB-LABEL: ctpop_v2i32:405; RV32ZBB: # %bb.0:406; RV32ZBB-NEXT: cpop a0, a0407; RV32ZBB-NEXT: cpop a1, a1408; RV32ZBB-NEXT: ret409 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)410 ret <2 x i32> %1411}412 413define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {414; CHECK-LABEL: ctpop_v2i32_ult_two:415; CHECK: # %bb.0:416; CHECK-NEXT: addi a2, a0, -1417; CHECK-NEXT: addi a3, a1, -1418; CHECK-NEXT: and a1, a1, a3419; CHECK-NEXT: and a0, a0, a2420; CHECK-NEXT: seqz a0, a0421; CHECK-NEXT: seqz a1, a1422; CHECK-NEXT: ret423 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)424 %2 = icmp ult <2 x i32> %1, <i32 2, i32 2>425 ret <2 x i1> %2426}427 428define <2 x i1> @ctpop_v2i32_ugt_one(<2 x i32> %a) nounwind {429; CHECK-LABEL: ctpop_v2i32_ugt_one:430; CHECK: # %bb.0:431; CHECK-NEXT: addi a2, a0, -1432; CHECK-NEXT: addi a3, a1, -1433; CHECK-NEXT: and a1, a1, a3434; CHECK-NEXT: and a0, a0, a2435; CHECK-NEXT: snez a0, a0436; CHECK-NEXT: snez a1, a1437; CHECK-NEXT: ret438 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)439 %2 = icmp ugt <2 x i32> %1, <i32 1, i32 1>440 ret <2 x i1> %2441}442 443define <2 x i1> @ctpop_v2i32_eq_one(<2 x i32> %a) nounwind {444; CHECK-LABEL: ctpop_v2i32_eq_one:445; CHECK: # %bb.0:446; CHECK-NEXT: addi a2, a0, -1447; CHECK-NEXT: addi a3, a1, -1448; CHECK-NEXT: xor a1, a1, a3449; CHECK-NEXT: xor a0, a0, a2450; CHECK-NEXT: sltu a0, a2, a0451; CHECK-NEXT: sltu a1, a3, a1452; CHECK-NEXT: ret453 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)454 %2 = icmp eq <2 x i32> %1, <i32 1, i32 1>455 ret <2 x i1> %2456}457 458define <2 x i1> @ctpop_v2i32_ne_one(<2 x i32> %a) nounwind {459; CHECK-LABEL: ctpop_v2i32_ne_one:460; CHECK: # %bb.0:461; CHECK-NEXT: addi a2, a0, -1462; CHECK-NEXT: addi a3, a1, -1463; CHECK-NEXT: xor a1, a1, a3464; CHECK-NEXT: xor a0, a0, a2465; CHECK-NEXT: sltu a0, a2, a0466; CHECK-NEXT: sltu a1, a3, a1467; CHECK-NEXT: xori a0, a0, 1468; CHECK-NEXT: xori a1, a1, 1469; CHECK-NEXT: ret470 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)471 %2 = icmp ne <2 x i32> %1, <i32 1, i32 1>472 ret <2 x i1> %2473}474 475define i64 @ctpop_i64(i64 %a) nounwind {476; RV32I-LABEL: ctpop_i64:477; RV32I: # %bb.0:478; RV32I-NEXT: srli a2, a1, 1479; RV32I-NEXT: lui a3, 349525480; RV32I-NEXT: lui a4, 209715481; RV32I-NEXT: srli a5, a0, 1482; RV32I-NEXT: addi a3, a3, 1365483; RV32I-NEXT: and a2, a2, a3484; RV32I-NEXT: and a3, a5, a3485; RV32I-NEXT: lui a5, 61681486; RV32I-NEXT: addi a4, a4, 819487; RV32I-NEXT: addi a5, a5, -241488; RV32I-NEXT: sub a1, a1, a2489; RV32I-NEXT: sub a0, a0, a3490; RV32I-NEXT: and a2, a1, a4491; RV32I-NEXT: srli a1, a1, 2492; RV32I-NEXT: and a3, a0, a4493; RV32I-NEXT: srli a0, a0, 2494; RV32I-NEXT: and a1, a1, a4495; RV32I-NEXT: and a0, a0, a4496; RV32I-NEXT: add a1, a2, a1497; RV32I-NEXT: add a0, a3, a0498; RV32I-NEXT: srli a2, a1, 4499; RV32I-NEXT: srli a3, a0, 4500; RV32I-NEXT: add a1, a1, a2501; RV32I-NEXT: add a0, a0, a3502; RV32I-NEXT: and a1, a1, a5503; RV32I-NEXT: and a0, a0, a5504; RV32I-NEXT: slli a2, a1, 8505; RV32I-NEXT: slli a3, a0, 8506; RV32I-NEXT: add a1, a1, a2507; RV32I-NEXT: add a0, a0, a3508; RV32I-NEXT: slli a2, a1, 16509; RV32I-NEXT: slli a3, a0, 16510; RV32I-NEXT: add a1, a1, a2511; RV32I-NEXT: add a0, a0, a3512; RV32I-NEXT: srli a1, a1, 24513; RV32I-NEXT: srli a0, a0, 24514; RV32I-NEXT: add a0, a0, a1515; RV32I-NEXT: li a1, 0516; RV32I-NEXT: ret517;518; RV32ZBB-LABEL: ctpop_i64:519; RV32ZBB: # %bb.0:520; RV32ZBB-NEXT: cpop a1, a1521; RV32ZBB-NEXT: cpop a0, a0522; RV32ZBB-NEXT: add a0, a0, a1523; RV32ZBB-NEXT: li a1, 0524; RV32ZBB-NEXT: ret525 %1 = call i64 @llvm.ctpop.i64(i64 %a)526 ret i64 %1527}528 529define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {530; RV32I-LABEL: ctpop_i64_ugt_two:531; RV32I: # %bb.0:532; RV32I-NEXT: seqz a2, a0533; RV32I-NEXT: addi a3, a0, -1534; RV32I-NEXT: sub a2, a1, a2535; RV32I-NEXT: and a0, a0, a3536; RV32I-NEXT: and a1, a1, a2537; RV32I-NEXT: or a0, a0, a1538; RV32I-NEXT: seqz a0, a0539; RV32I-NEXT: ret540;541; RV32ZBB-LABEL: ctpop_i64_ugt_two:542; RV32ZBB: # %bb.0:543; RV32ZBB-NEXT: cpop a1, a1544; RV32ZBB-NEXT: cpop a0, a0545; RV32ZBB-NEXT: add a0, a0, a1546; RV32ZBB-NEXT: sltiu a0, a0, 2547; RV32ZBB-NEXT: ret548 %1 = call i64 @llvm.ctpop.i64(i64 %a)549 %2 = icmp ult i64 %1, 2550 ret i1 %2551}552 553define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {554; RV32I-LABEL: ctpop_i64_ugt_one:555; RV32I: # %bb.0:556; RV32I-NEXT: seqz a2, a0557; RV32I-NEXT: addi a3, a0, -1558; RV32I-NEXT: sub a2, a1, a2559; RV32I-NEXT: and a0, a0, a3560; RV32I-NEXT: and a1, a1, a2561; RV32I-NEXT: or a0, a0, a1562; RV32I-NEXT: snez a0, a0563; RV32I-NEXT: ret564;565; RV32ZBB-LABEL: ctpop_i64_ugt_one:566; RV32ZBB: # %bb.0:567; RV32ZBB-NEXT: cpop a1, a1568; RV32ZBB-NEXT: cpop a0, a0569; RV32ZBB-NEXT: add a0, a0, a1570; RV32ZBB-NEXT: sltiu a0, a0, 2571; RV32ZBB-NEXT: xori a0, a0, 1572; RV32ZBB-NEXT: ret573 %1 = call i64 @llvm.ctpop.i64(i64 %a)574 %2 = icmp ugt i64 %1, 1575 ret i1 %2576}577 578define i1 @ctpop_i64_eq_one(i64 %a) nounwind {579; RV32I-LABEL: ctpop_i64_eq_one:580; RV32I: # %bb.0:581; RV32I-NEXT: beqz a1, .LBB17_2582; RV32I-NEXT: # %bb.1:583; RV32I-NEXT: seqz a0, a0584; RV32I-NEXT: sub a0, a1, a0585; RV32I-NEXT: xor a1, a1, a0586; RV32I-NEXT: sltu a0, a0, a1587; RV32I-NEXT: ret588; RV32I-NEXT: .LBB17_2:589; RV32I-NEXT: addi a1, a0, -1590; RV32I-NEXT: xor a0, a0, a1591; RV32I-NEXT: sltu a0, a1, a0592; RV32I-NEXT: ret593;594; RV32ZBB-LABEL: ctpop_i64_eq_one:595; RV32ZBB: # %bb.0:596; RV32ZBB-NEXT: cpop a1, a1597; RV32ZBB-NEXT: cpop a0, a0598; RV32ZBB-NEXT: add a0, a0, a1599; RV32ZBB-NEXT: addi a0, a0, -1600; RV32ZBB-NEXT: seqz a0, a0601; RV32ZBB-NEXT: ret602 %1 = call i64 @llvm.ctpop.i64(i64 %a)603 %2 = icmp eq i64 %1, 1604 ret i1 %2605}606 607define i1 @ctpop_i64_ne_one(i64 %a) nounwind {608; RV32I-LABEL: ctpop_i64_ne_one:609; RV32I: # %bb.0:610; RV32I-NEXT: beqz a1, .LBB18_2611; RV32I-NEXT: # %bb.1:612; RV32I-NEXT: seqz a0, a0613; RV32I-NEXT: sub a0, a1, a0614; RV32I-NEXT: xor a1, a1, a0615; RV32I-NEXT: sltu a0, a0, a1616; RV32I-NEXT: xori a0, a0, 1617; RV32I-NEXT: ret618; RV32I-NEXT: .LBB18_2:619; RV32I-NEXT: addi a1, a0, -1620; RV32I-NEXT: xor a0, a0, a1621; RV32I-NEXT: sltu a0, a1, a0622; RV32I-NEXT: xori a0, a0, 1623; RV32I-NEXT: ret624;625; RV32ZBB-LABEL: ctpop_i64_ne_one:626; RV32ZBB: # %bb.0:627; RV32ZBB-NEXT: cpop a1, a1628; RV32ZBB-NEXT: cpop a0, a0629; RV32ZBB-NEXT: add a0, a0, a1630; RV32ZBB-NEXT: addi a0, a0, -1631; RV32ZBB-NEXT: snez a0, a0632; RV32ZBB-NEXT: ret633 %1 = call i64 @llvm.ctpop.i64(i64 %a)634 %2 = icmp ne i64 %1, 1635 ret i1 %2636}637 638define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {639; RV32I-LABEL: ctpop_v2i64:640; RV32I: # %bb.0:641; RV32I-NEXT: lw a3, 0(a1)642; RV32I-NEXT: lw a4, 4(a1)643; RV32I-NEXT: lw a2, 8(a1)644; RV32I-NEXT: lw a1, 12(a1)645; RV32I-NEXT: lui a5, 349525646; RV32I-NEXT: addi a5, a5, 1365647; RV32I-NEXT: srli a6, a4, 1648; RV32I-NEXT: srli a7, a3, 1649; RV32I-NEXT: srli t0, a1, 1650; RV32I-NEXT: srli t1, a2, 1651; RV32I-NEXT: and a6, a6, a5652; RV32I-NEXT: and a7, a7, a5653; RV32I-NEXT: and t0, t0, a5654; RV32I-NEXT: and a5, t1, a5655; RV32I-NEXT: lui t1, 209715656; RV32I-NEXT: addi t1, t1, 819657; RV32I-NEXT: sub a4, a4, a6658; RV32I-NEXT: sub a3, a3, a7659; RV32I-NEXT: sub a1, a1, t0660; RV32I-NEXT: sub a2, a2, a5661; RV32I-NEXT: and a5, a4, t1662; RV32I-NEXT: srli a4, a4, 2663; RV32I-NEXT: and a6, a3, t1664; RV32I-NEXT: srli a3, a3, 2665; RV32I-NEXT: and a7, a1, t1666; RV32I-NEXT: srli a1, a1, 2667; RV32I-NEXT: and t0, a2, t1668; RV32I-NEXT: srli a2, a2, 2669; RV32I-NEXT: and a4, a4, t1670; RV32I-NEXT: and a3, a3, t1671; RV32I-NEXT: and a1, a1, t1672; RV32I-NEXT: and a2, a2, t1673; RV32I-NEXT: add a4, a5, a4674; RV32I-NEXT: lui a5, 61681675; RV32I-NEXT: addi a5, a5, -241676; RV32I-NEXT: add a3, a6, a3677; RV32I-NEXT: add a1, a7, a1678; RV32I-NEXT: add a2, t0, a2679; RV32I-NEXT: srli a6, a4, 4680; RV32I-NEXT: srli a7, a3, 4681; RV32I-NEXT: srli t0, a1, 4682; RV32I-NEXT: add a4, a4, a6683; RV32I-NEXT: srli a6, a2, 4684; RV32I-NEXT: add a3, a3, a7685; RV32I-NEXT: add a1, a1, t0686; RV32I-NEXT: add a2, a2, a6687; RV32I-NEXT: and a4, a4, a5688; RV32I-NEXT: and a3, a3, a5689; RV32I-NEXT: and a1, a1, a5690; RV32I-NEXT: and a2, a2, a5691; RV32I-NEXT: slli a5, a4, 8692; RV32I-NEXT: slli a6, a3, 8693; RV32I-NEXT: slli a7, a1, 8694; RV32I-NEXT: slli t0, a2, 8695; RV32I-NEXT: add a4, a4, a5696; RV32I-NEXT: add a3, a3, a6697; RV32I-NEXT: add a1, a1, a7698; RV32I-NEXT: add a2, a2, t0699; RV32I-NEXT: slli a5, a4, 16700; RV32I-NEXT: slli a6, a3, 16701; RV32I-NEXT: slli a7, a1, 16702; RV32I-NEXT: slli t0, a2, 16703; RV32I-NEXT: add a4, a4, a5704; RV32I-NEXT: add a3, a3, a6705; RV32I-NEXT: add a1, a1, a7706; RV32I-NEXT: add a2, a2, t0707; RV32I-NEXT: srli a4, a4, 24708; RV32I-NEXT: srli a3, a3, 24709; RV32I-NEXT: srli a1, a1, 24710; RV32I-NEXT: srli a2, a2, 24711; RV32I-NEXT: add a3, a3, a4712; RV32I-NEXT: add a1, a2, a1713; RV32I-NEXT: sw a3, 0(a0)714; RV32I-NEXT: sw zero, 4(a0)715; RV32I-NEXT: sw a1, 8(a0)716; RV32I-NEXT: sw zero, 12(a0)717; RV32I-NEXT: ret718;719; RV32ZBB-LABEL: ctpop_v2i64:720; RV32ZBB: # %bb.0:721; RV32ZBB-NEXT: lw a2, 4(a1)722; RV32ZBB-NEXT: lw a3, 0(a1)723; RV32ZBB-NEXT: lw a4, 12(a1)724; RV32ZBB-NEXT: lw a1, 8(a1)725; RV32ZBB-NEXT: cpop a2, a2726; RV32ZBB-NEXT: cpop a3, a3727; RV32ZBB-NEXT: cpop a4, a4728; RV32ZBB-NEXT: cpop a1, a1729; RV32ZBB-NEXT: add a2, a3, a2730; RV32ZBB-NEXT: add a1, a1, a4731; RV32ZBB-NEXT: sw a2, 0(a0)732; RV32ZBB-NEXT: sw zero, 4(a0)733; RV32ZBB-NEXT: sw a1, 8(a0)734; RV32ZBB-NEXT: sw zero, 12(a0)735; RV32ZBB-NEXT: ret736 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)737 ret <2 x i64> %1738}739 740define <2 x i1> @ctpop_v2i64_ult_two(<2 x i64> %a) nounwind {741; CHECK-LABEL: ctpop_v2i64_ult_two:742; CHECK: # %bb.0:743; CHECK-NEXT: lw a1, 0(a0)744; CHECK-NEXT: lw a2, 8(a0)745; CHECK-NEXT: lw a3, 4(a0)746; CHECK-NEXT: lw a0, 12(a0)747; CHECK-NEXT: seqz a4, a1748; CHECK-NEXT: seqz a5, a2749; CHECK-NEXT: addi a6, a1, -1750; CHECK-NEXT: addi a7, a2, -1751; CHECK-NEXT: sub a4, a3, a4752; CHECK-NEXT: sub a5, a0, a5753; CHECK-NEXT: and a2, a2, a7754; CHECK-NEXT: and a1, a1, a6755; CHECK-NEXT: and a0, a0, a5756; CHECK-NEXT: and a3, a3, a4757; CHECK-NEXT: or a1, a1, a3758; CHECK-NEXT: or a2, a2, a0759; CHECK-NEXT: seqz a0, a1760; CHECK-NEXT: seqz a1, a2761; CHECK-NEXT: ret762 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)763 %2 = icmp ult <2 x i64> %1, <i64 2, i64 2>764 ret <2 x i1> %2765}766 767define <2 x i1> @ctpop_v2i64_ugt_one(<2 x i64> %a) nounwind {768; CHECK-LABEL: ctpop_v2i64_ugt_one:769; CHECK: # %bb.0:770; CHECK-NEXT: lw a1, 0(a0)771; CHECK-NEXT: lw a2, 8(a0)772; CHECK-NEXT: lw a3, 4(a0)773; CHECK-NEXT: lw a0, 12(a0)774; CHECK-NEXT: seqz a4, a1775; CHECK-NEXT: seqz a5, a2776; CHECK-NEXT: addi a6, a1, -1777; CHECK-NEXT: addi a7, a2, -1778; CHECK-NEXT: sub a4, a3, a4779; CHECK-NEXT: sub a5, a0, a5780; CHECK-NEXT: and a2, a2, a7781; CHECK-NEXT: and a1, a1, a6782; CHECK-NEXT: and a0, a0, a5783; CHECK-NEXT: and a3, a3, a4784; CHECK-NEXT: or a1, a1, a3785; CHECK-NEXT: or a2, a2, a0786; CHECK-NEXT: snez a0, a1787; CHECK-NEXT: snez a1, a2788; CHECK-NEXT: ret789 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)790 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>791 ret <2 x i1> %2792}793 794define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {795; CHECK-LABEL: ctpop_v2i64_eq_one:796; CHECK: # %bb.0:797; CHECK-NEXT: mv a1, a0798; CHECK-NEXT: lw a0, 0(a0)799; CHECK-NEXT: lw a3, 4(a1)800; CHECK-NEXT: lw a2, 12(a1)801; CHECK-NEXT: beqz a3, .LBB22_3802; CHECK-NEXT: # %bb.1:803; CHECK-NEXT: seqz a0, a0804; CHECK-NEXT: sub a0, a3, a0805; CHECK-NEXT: xor a3, a3, a0806; CHECK-NEXT: sltu a0, a0, a3807; CHECK-NEXT: lw a1, 8(a1)808; CHECK-NEXT: bnez a2, .LBB22_4809; CHECK-NEXT: .LBB22_2:810; CHECK-NEXT: addi a2, a1, -1811; CHECK-NEXT: xor a1, a1, a2812; CHECK-NEXT: sltu a1, a2, a1813; CHECK-NEXT: ret814; CHECK-NEXT: .LBB22_3:815; CHECK-NEXT: addi a3, a0, -1816; CHECK-NEXT: xor a0, a0, a3817; CHECK-NEXT: sltu a0, a3, a0818; CHECK-NEXT: lw a1, 8(a1)819; CHECK-NEXT: beqz a2, .LBB22_2820; CHECK-NEXT: .LBB22_4:821; CHECK-NEXT: seqz a1, a1822; CHECK-NEXT: sub a1, a2, a1823; CHECK-NEXT: xor a2, a2, a1824; CHECK-NEXT: sltu a1, a1, a2825; CHECK-NEXT: ret826 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)827 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>828 ret <2 x i1> %2829}830 831define <2 x i1> @ctpop_v2i64_ne_one(<2 x i64> %a) nounwind {832; CHECK-LABEL: ctpop_v2i64_ne_one:833; CHECK: # %bb.0:834; CHECK-NEXT: lw a2, 0(a0)835; CHECK-NEXT: lw a3, 4(a0)836; CHECK-NEXT: lw a1, 12(a0)837; CHECK-NEXT: beqz a3, .LBB23_2838; CHECK-NEXT: # %bb.1:839; CHECK-NEXT: seqz a2, a2840; CHECK-NEXT: sub a2, a3, a2841; CHECK-NEXT: xor a3, a3, a2842; CHECK-NEXT: sltu a2, a2, a3843; CHECK-NEXT: j .LBB23_3844; CHECK-NEXT: .LBB23_2:845; CHECK-NEXT: addi a3, a2, -1846; CHECK-NEXT: xor a2, a2, a3847; CHECK-NEXT: sltu a2, a3, a2848; CHECK-NEXT: .LBB23_3:849; CHECK-NEXT: lw a3, 8(a0)850; CHECK-NEXT: xori a0, a2, 1851; CHECK-NEXT: beqz a1, .LBB23_5852; CHECK-NEXT: # %bb.4:853; CHECK-NEXT: seqz a2, a3854; CHECK-NEXT: sub a2, a1, a2855; CHECK-NEXT: xor a1, a1, a2856; CHECK-NEXT: sltu a1, a2, a1857; CHECK-NEXT: xori a1, a1, 1858; CHECK-NEXT: ret859; CHECK-NEXT: .LBB23_5:860; CHECK-NEXT: addi a1, a3, -1861; CHECK-NEXT: xor a3, a3, a1862; CHECK-NEXT: sltu a1, a1, a3863; CHECK-NEXT: xori a1, a1, 1864; CHECK-NEXT: ret865 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)866 %2 = icmp ne <2 x i64> %1, <i64 1, i64 1>867 ret <2 x i1> %2868}869 870define i32 @sextb_i32(i32 %a) nounwind {871; RV32I-LABEL: sextb_i32:872; RV32I: # %bb.0:873; RV32I-NEXT: slli a0, a0, 24874; RV32I-NEXT: srai a0, a0, 24875; RV32I-NEXT: ret876;877; RV32ZBB-LABEL: sextb_i32:878; RV32ZBB: # %bb.0:879; RV32ZBB-NEXT: sext.b a0, a0880; RV32ZBB-NEXT: ret881 %shl = shl i32 %a, 24882 %shr = ashr exact i32 %shl, 24883 ret i32 %shr884}885 886define i64 @sextb_i64(i64 %a) nounwind {887; RV32I-LABEL: sextb_i64:888; RV32I: # %bb.0:889; RV32I-NEXT: slli a1, a0, 24890; RV32I-NEXT: srai a0, a1, 24891; RV32I-NEXT: srai a1, a1, 31892; RV32I-NEXT: ret893;894; RV32ZBB-LABEL: sextb_i64:895; RV32ZBB: # %bb.0:896; RV32ZBB-NEXT: sext.b a0, a0897; RV32ZBB-NEXT: srai a1, a0, 31898; RV32ZBB-NEXT: ret899 %shl = shl i64 %a, 56900 %shr = ashr exact i64 %shl, 56901 ret i64 %shr902}903 904define i32 @sexth_i32(i32 %a) nounwind {905; RV32I-LABEL: sexth_i32:906; RV32I: # %bb.0:907; RV32I-NEXT: slli a0, a0, 16908; RV32I-NEXT: srai a0, a0, 16909; RV32I-NEXT: ret910;911; RV32ZBB-LABEL: sexth_i32:912; RV32ZBB: # %bb.0:913; RV32ZBB-NEXT: sext.h a0, a0914; RV32ZBB-NEXT: ret915 %shl = shl i32 %a, 16916 %shr = ashr exact i32 %shl, 16917 ret i32 %shr918}919 920define i64 @sexth_i64(i64 %a) nounwind {921; RV32I-LABEL: sexth_i64:922; RV32I: # %bb.0:923; RV32I-NEXT: slli a1, a0, 16924; RV32I-NEXT: srai a0, a1, 16925; RV32I-NEXT: srai a1, a1, 31926; RV32I-NEXT: ret927;928; RV32ZBB-LABEL: sexth_i64:929; RV32ZBB: # %bb.0:930; RV32ZBB-NEXT: sext.h a0, a0931; RV32ZBB-NEXT: srai a1, a0, 31932; RV32ZBB-NEXT: ret933 %shl = shl i64 %a, 48934 %shr = ashr exact i64 %shl, 48935 ret i64 %shr936}937 938define i32 @min_i32(i32 %a, i32 %b) nounwind {939; RV32I-LABEL: min_i32:940; RV32I: # %bb.0:941; RV32I-NEXT: blt a0, a1, .LBB28_2942; RV32I-NEXT: # %bb.1:943; RV32I-NEXT: mv a0, a1944; RV32I-NEXT: .LBB28_2:945; RV32I-NEXT: ret946;947; RV32ZBB-LABEL: min_i32:948; RV32ZBB: # %bb.0:949; RV32ZBB-NEXT: min a0, a0, a1950; RV32ZBB-NEXT: ret951 %cmp = icmp slt i32 %a, %b952 %cond = select i1 %cmp, i32 %a, i32 %b953 ret i32 %cond954}955 956; As we are not matching directly i64 code patterns on RV32 some i64 patterns957; don't have yet any matching bit manipulation instructions on RV32.958; This test is presented here in case future expansions of the Bitmanip959; extensions introduce instructions suitable for this pattern.960 961define i64 @min_i64(i64 %a, i64 %b) nounwind {962; CHECK-LABEL: min_i64:963; CHECK: # %bb.0:964; CHECK-NEXT: beq a1, a3, .LBB29_2965; CHECK-NEXT: # %bb.1:966; CHECK-NEXT: slt a4, a1, a3967; CHECK-NEXT: beqz a4, .LBB29_3968; CHECK-NEXT: j .LBB29_4969; CHECK-NEXT: .LBB29_2:970; CHECK-NEXT: sltu a4, a0, a2971; CHECK-NEXT: bnez a4, .LBB29_4972; CHECK-NEXT: .LBB29_3:973; CHECK-NEXT: mv a0, a2974; CHECK-NEXT: mv a1, a3975; CHECK-NEXT: .LBB29_4:976; CHECK-NEXT: ret977 %cmp = icmp slt i64 %a, %b978 %cond = select i1 %cmp, i64 %a, i64 %b979 ret i64 %cond980}981 982define i32 @max_i32(i32 %a, i32 %b) nounwind {983; RV32I-LABEL: max_i32:984; RV32I: # %bb.0:985; RV32I-NEXT: blt a1, a0, .LBB30_2986; RV32I-NEXT: # %bb.1:987; RV32I-NEXT: mv a0, a1988; RV32I-NEXT: .LBB30_2:989; RV32I-NEXT: ret990;991; RV32ZBB-LABEL: max_i32:992; RV32ZBB: # %bb.0:993; RV32ZBB-NEXT: max a0, a0, a1994; RV32ZBB-NEXT: ret995 %cmp = icmp sgt i32 %a, %b996 %cond = select i1 %cmp, i32 %a, i32 %b997 ret i32 %cond998}999 1000; As we are not matching directly i64 code patterns on RV32 some i64 patterns1001; don't have yet any matching bit manipulation instructions on RV32.1002; This test is presented here in case future expansions of the Bitmanip1003; extensions introduce instructions suitable for this pattern.1004 1005define i64 @max_i64(i64 %a, i64 %b) nounwind {1006; CHECK-LABEL: max_i64:1007; CHECK: # %bb.0:1008; CHECK-NEXT: beq a1, a3, .LBB31_21009; CHECK-NEXT: # %bb.1:1010; CHECK-NEXT: slt a4, a3, a11011; CHECK-NEXT: beqz a4, .LBB31_31012; CHECK-NEXT: j .LBB31_41013; CHECK-NEXT: .LBB31_2:1014; CHECK-NEXT: sltu a4, a2, a01015; CHECK-NEXT: bnez a4, .LBB31_41016; CHECK-NEXT: .LBB31_3:1017; CHECK-NEXT: mv a0, a21018; CHECK-NEXT: mv a1, a31019; CHECK-NEXT: .LBB31_4:1020; CHECK-NEXT: ret1021 %cmp = icmp sgt i64 %a, %b1022 %cond = select i1 %cmp, i64 %a, i64 %b1023 ret i64 %cond1024}1025 1026define i32 @minu_i32(i32 %a, i32 %b) nounwind {1027; RV32I-LABEL: minu_i32:1028; RV32I: # %bb.0:1029; RV32I-NEXT: bltu a0, a1, .LBB32_21030; RV32I-NEXT: # %bb.1:1031; RV32I-NEXT: mv a0, a11032; RV32I-NEXT: .LBB32_2:1033; RV32I-NEXT: ret1034;1035; RV32ZBB-LABEL: minu_i32:1036; RV32ZBB: # %bb.0:1037; RV32ZBB-NEXT: minu a0, a0, a11038; RV32ZBB-NEXT: ret1039 %cmp = icmp ult i32 %a, %b1040 %cond = select i1 %cmp, i32 %a, i32 %b1041 ret i32 %cond1042}1043 1044; As we are not matching directly i64 code patterns on RV32 some i64 patterns1045; don't have yet any matching bit manipulation instructions on RV32.1046; This test is presented here in case future expansions of the Bitmanip1047; extensions introduce instructions suitable for this pattern.1048 1049define i64 @minu_i64(i64 %a, i64 %b) nounwind {1050; CHECK-LABEL: minu_i64:1051; CHECK: # %bb.0:1052; CHECK-NEXT: beq a1, a3, .LBB33_21053; CHECK-NEXT: # %bb.1:1054; CHECK-NEXT: sltu a4, a1, a31055; CHECK-NEXT: beqz a4, .LBB33_31056; CHECK-NEXT: j .LBB33_41057; CHECK-NEXT: .LBB33_2:1058; CHECK-NEXT: sltu a4, a0, a21059; CHECK-NEXT: bnez a4, .LBB33_41060; CHECK-NEXT: .LBB33_3:1061; CHECK-NEXT: mv a0, a21062; CHECK-NEXT: mv a1, a31063; CHECK-NEXT: .LBB33_4:1064; CHECK-NEXT: ret1065 %cmp = icmp ult i64 %a, %b1066 %cond = select i1 %cmp, i64 %a, i64 %b1067 ret i64 %cond1068}1069 1070define i32 @maxu_i32(i32 %a, i32 %b) nounwind {1071; RV32I-LABEL: maxu_i32:1072; RV32I: # %bb.0:1073; RV32I-NEXT: bltu a1, a0, .LBB34_21074; RV32I-NEXT: # %bb.1:1075; RV32I-NEXT: mv a0, a11076; RV32I-NEXT: .LBB34_2:1077; RV32I-NEXT: ret1078;1079; RV32ZBB-LABEL: maxu_i32:1080; RV32ZBB: # %bb.0:1081; RV32ZBB-NEXT: maxu a0, a0, a11082; RV32ZBB-NEXT: ret1083 %cmp = icmp ugt i32 %a, %b1084 %cond = select i1 %cmp, i32 %a, i32 %b1085 ret i32 %cond1086}1087 1088; As we are not matching directly i64 code patterns on RV32 some i64 patterns1089; don't have yet any matching bit manipulation instructions on RV32.1090; This test is presented here in case future expansions of the Bitmanip1091; extensions introduce instructions suitable for this pattern.1092 1093define i64 @maxu_i64(i64 %a, i64 %b) nounwind {1094; CHECK-LABEL: maxu_i64:1095; CHECK: # %bb.0:1096; CHECK-NEXT: beq a1, a3, .LBB35_21097; CHECK-NEXT: # %bb.1:1098; CHECK-NEXT: sltu a4, a3, a11099; CHECK-NEXT: beqz a4, .LBB35_31100; CHECK-NEXT: j .LBB35_41101; CHECK-NEXT: .LBB35_2:1102; CHECK-NEXT: sltu a4, a2, a01103; CHECK-NEXT: bnez a4, .LBB35_41104; CHECK-NEXT: .LBB35_3:1105; CHECK-NEXT: mv a0, a21106; CHECK-NEXT: mv a1, a31107; CHECK-NEXT: .LBB35_4:1108; CHECK-NEXT: ret1109 %cmp = icmp ugt i64 %a, %b1110 %cond = select i1 %cmp, i64 %a, i64 %b1111 ret i64 %cond1112}1113 1114define i32 @abs_i32(i32 %x) {1115; RV32I-LABEL: abs_i32:1116; RV32I: # %bb.0:1117; RV32I-NEXT: srai a1, a0, 311118; RV32I-NEXT: xor a0, a0, a11119; RV32I-NEXT: sub a0, a0, a11120; RV32I-NEXT: ret1121;1122; RV32ZBB-LABEL: abs_i32:1123; RV32ZBB: # %bb.0:1124; RV32ZBB-NEXT: neg a1, a01125; RV32ZBB-NEXT: max a0, a0, a11126; RV32ZBB-NEXT: ret1127 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)1128 ret i32 %abs1129}1130 1131define i64 @abs_i64(i64 %x) {1132; CHECK-LABEL: abs_i64:1133; CHECK: # %bb.0:1134; CHECK-NEXT: bgez a1, .LBB37_21135; CHECK-NEXT: # %bb.1:1136; CHECK-NEXT: snez a2, a01137; CHECK-NEXT: neg a0, a01138; CHECK-NEXT: neg a1, a11139; CHECK-NEXT: sub a1, a1, a21140; CHECK-NEXT: .LBB37_2:1141; CHECK-NEXT: ret1142 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)1143 ret i64 %abs1144}1145 1146define i32 @zexth_i32(i32 %a) nounwind {1147; RV32I-LABEL: zexth_i32:1148; RV32I: # %bb.0:1149; RV32I-NEXT: slli a0, a0, 161150; RV32I-NEXT: srli a0, a0, 161151; RV32I-NEXT: ret1152;1153; RV32ZBB-LABEL: zexth_i32:1154; RV32ZBB: # %bb.0:1155; RV32ZBB-NEXT: zext.h a0, a01156; RV32ZBB-NEXT: ret1157 %and = and i32 %a, 655351158 ret i32 %and1159}1160 1161define i64 @zexth_i64(i64 %a) nounwind {1162; RV32I-LABEL: zexth_i64:1163; RV32I: # %bb.0:1164; RV32I-NEXT: slli a0, a0, 161165; RV32I-NEXT: srli a0, a0, 161166; RV32I-NEXT: li a1, 01167; RV32I-NEXT: ret1168;1169; RV32ZBB-LABEL: zexth_i64:1170; RV32ZBB: # %bb.0:1171; RV32ZBB-NEXT: zext.h a0, a01172; RV32ZBB-NEXT: li a1, 01173; RV32ZBB-NEXT: ret1174 %and = and i64 %a, 655351175 ret i64 %and1176}1177 1178define i32 @bswap_i32(i32 %a) nounwind {1179; RV32I-LABEL: bswap_i32:1180; RV32I: # %bb.0:1181; RV32I-NEXT: srli a1, a0, 81182; RV32I-NEXT: lui a2, 161183; RV32I-NEXT: srli a3, a0, 241184; RV32I-NEXT: addi a2, a2, -2561185; RV32I-NEXT: and a1, a1, a21186; RV32I-NEXT: and a2, a0, a21187; RV32I-NEXT: or a1, a1, a31188; RV32I-NEXT: slli a2, a2, 81189; RV32I-NEXT: slli a0, a0, 241190; RV32I-NEXT: or a0, a0, a21191; RV32I-NEXT: or a0, a0, a11192; RV32I-NEXT: ret1193;1194; RV32ZBB-LABEL: bswap_i32:1195; RV32ZBB: # %bb.0:1196; RV32ZBB-NEXT: rev8 a0, a01197; RV32ZBB-NEXT: ret1198 %1 = tail call i32 @llvm.bswap.i32(i32 %a)1199 ret i32 %11200}1201 1202define i64 @bswap_i64(i64 %a) {1203; RV32I-LABEL: bswap_i64:1204; RV32I: # %bb.0:1205; RV32I-NEXT: srli a2, a1, 81206; RV32I-NEXT: lui a3, 161207; RV32I-NEXT: srli a4, a1, 241208; RV32I-NEXT: srli a5, a0, 81209; RV32I-NEXT: addi a3, a3, -2561210; RV32I-NEXT: and a2, a2, a31211; RV32I-NEXT: or a2, a2, a41212; RV32I-NEXT: srli a4, a0, 241213; RV32I-NEXT: and a5, a5, a31214; RV32I-NEXT: or a4, a5, a41215; RV32I-NEXT: slli a5, a1, 241216; RV32I-NEXT: and a1, a1, a31217; RV32I-NEXT: slli a1, a1, 81218; RV32I-NEXT: or a1, a5, a11219; RV32I-NEXT: and a3, a0, a31220; RV32I-NEXT: slli a0, a0, 241221; RV32I-NEXT: slli a3, a3, 81222; RV32I-NEXT: or a3, a0, a31223; RV32I-NEXT: or a0, a1, a21224; RV32I-NEXT: or a1, a3, a41225; RV32I-NEXT: ret1226;1227; RV32ZBB-LABEL: bswap_i64:1228; RV32ZBB: # %bb.0:1229; RV32ZBB-NEXT: rev8 a2, a11230; RV32ZBB-NEXT: rev8 a1, a01231; RV32ZBB-NEXT: mv a0, a21232; RV32ZBB-NEXT: ret1233 %1 = call i64 @llvm.bswap.i64(i64 %a)1234 ret i64 %11235}1236 1237define i16 @orc_b_i16(i16 %a) {1238; RV32I-LABEL: orc_b_i16:1239; RV32I: # %bb.0:1240; RV32I-NEXT: andi a0, a0, 2571241; RV32I-NEXT: slli a1, a0, 81242; RV32I-NEXT: sub a0, a1, a01243; RV32I-NEXT: ret1244;1245; RV32ZBB-LABEL: orc_b_i16:1246; RV32ZBB: # %bb.0:1247; RV32ZBB-NEXT: andi a0, a0, 2571248; RV32ZBB-NEXT: orc.b a0, a01249; RV32ZBB-NEXT: ret1250 %1 = and i16 %a, 2571251 %2 = mul nuw i16 %1, 2551252 ret i16 %21253}1254 1255define i32 @orc_b_i32(i32 %a) {1256; RV32I-LABEL: orc_b_i32:1257; RV32I: # %bb.0:1258; RV32I-NEXT: lui a1, 41121259; RV32I-NEXT: addi a1, a1, 2571260; RV32I-NEXT: and a0, a0, a11261; RV32I-NEXT: slli a1, a0, 81262; RV32I-NEXT: sub a0, a1, a01263; RV32I-NEXT: ret1264;1265; RV32ZBB-LABEL: orc_b_i32:1266; RV32ZBB: # %bb.0:1267; RV32ZBB-NEXT: lui a1, 41121268; RV32ZBB-NEXT: addi a1, a1, 2571269; RV32ZBB-NEXT: and a0, a0, a11270; RV32ZBB-NEXT: orc.b a0, a01271; RV32ZBB-NEXT: ret1272 %1 = and i32 %a, 168430091273 %2 = mul nuw i32 %1, 2551274 ret i32 %21275}1276 1277define i64 @orc_b_i64(i64 %a) {1278; CHECK-LABEL: orc_b_i64:1279; CHECK: # %bb.0:1280; CHECK-NEXT: lui a2, 41121281; CHECK-NEXT: addi a2, a2, 2571282; CHECK-NEXT: and a1, a1, a21283; CHECK-NEXT: and a0, a0, a21284; CHECK-NEXT: slli a2, a0, 81285; CHECK-NEXT: srli a3, a0, 241286; CHECK-NEXT: slli a4, a1, 81287; CHECK-NEXT: sltu a5, a2, a01288; CHECK-NEXT: or a3, a4, a31289; CHECK-NEXT: sub a1, a3, a11290; CHECK-NEXT: sub a1, a1, a51291; CHECK-NEXT: sub a0, a2, a01292; CHECK-NEXT: ret1293 %1 = and i64 %a, 723401728380766731294 %2 = mul nuw i64 %1, 2551295 ret i64 %21296}1297 1298define i32 @srai_slli(i16 signext %0) {1299; CHECK-LABEL: srai_slli:1300; CHECK: # %bb.0:1301; CHECK-NEXT: slli a0, a0, 251302; CHECK-NEXT: srai a0, a0, 311303; CHECK-NEXT: ret1304 %2 = shl i16 %0, 91305 %sext = ashr i16 %2, 151306 %3 = sext i16 %sext to i321307 ret i32 %31308}1309 1310define i32 @srai_slli2(i16 signext %0) {1311; CHECK-LABEL: srai_slli2:1312; CHECK: # %bb.0:1313; CHECK-NEXT: slli a0, a0, 251314; CHECK-NEXT: srai a0, a0, 301315; CHECK-NEXT: ret1316 %2 = shl i16 %0, 91317 %sext = ashr i16 %2, 141318 %3 = sext i16 %sext to i321319 ret i32 %31320}1321 1322define i1 @ctpop32_eq_one_nonzero(i32 %x) {1323; RV32I-LABEL: ctpop32_eq_one_nonzero:1324; RV32I: # %bb.0: # %entry1325; RV32I-NEXT: addi a1, a0, -11326; RV32I-NEXT: and a0, a0, a11327; RV32I-NEXT: seqz a0, a01328; RV32I-NEXT: ret1329;1330; RV32ZBB-LABEL: ctpop32_eq_one_nonzero:1331; RV32ZBB: # %bb.0: # %entry1332; RV32ZBB-NEXT: cpop a0, a01333; RV32ZBB-NEXT: sltiu a0, a0, 21334; RV32ZBB-NEXT: ret1335entry:1336 %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)1337 %cmp = icmp eq i32 %popcnt, 11338 ret i1 %cmp1339}1340 1341define i1 @ctpop32_ne_one_nonzero(i32 %x) {1342; RV32I-LABEL: ctpop32_ne_one_nonzero:1343; RV32I: # %bb.0: # %entry1344; RV32I-NEXT: addi a1, a0, -11345; RV32I-NEXT: and a0, a0, a11346; RV32I-NEXT: snez a0, a01347; RV32I-NEXT: ret1348;1349; RV32ZBB-LABEL: ctpop32_ne_one_nonzero:1350; RV32ZBB: # %bb.0: # %entry1351; RV32ZBB-NEXT: cpop a0, a01352; RV32ZBB-NEXT: sltiu a0, a0, 21353; RV32ZBB-NEXT: xori a0, a0, 11354; RV32ZBB-NEXT: ret1355entry:1356 %popcnt = tail call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)1357 %cmp = icmp ne i32 %popcnt, 11358 ret i1 %cmp1359}1360 1361define i8 @sub_if_uge_i8(i8 %x, i8 %y) {1362; RV32I-LABEL: sub_if_uge_i8:1363; RV32I: # %bb.0:1364; RV32I-NEXT: zext.b a2, a11365; RV32I-NEXT: zext.b a3, a01366; RV32I-NEXT: sltu a2, a3, a21367; RV32I-NEXT: addi a2, a2, -11368; RV32I-NEXT: and a1, a2, a11369; RV32I-NEXT: sub a0, a0, a11370; RV32I-NEXT: ret1371;1372; RV32ZBB-LABEL: sub_if_uge_i8:1373; RV32ZBB: # %bb.0:1374; RV32ZBB-NEXT: zext.b a2, a01375; RV32ZBB-NEXT: sub a0, a0, a11376; RV32ZBB-NEXT: zext.b a0, a01377; RV32ZBB-NEXT: minu a0, a2, a01378; RV32ZBB-NEXT: ret1379 %cmp = icmp ult i8 %x, %y1380 %select = select i1 %cmp, i8 0, i8 %y1381 %sub = sub nuw i8 %x, %select1382 ret i8 %sub1383}1384 1385define i16 @sub_if_uge_i16(i16 %x, i16 %y) {1386; RV32I-LABEL: sub_if_uge_i16:1387; RV32I: # %bb.0:1388; RV32I-NEXT: lui a2, 161389; RV32I-NEXT: addi a2, a2, -11390; RV32I-NEXT: and a3, a1, a21391; RV32I-NEXT: and a2, a0, a21392; RV32I-NEXT: sltu a2, a2, a31393; RV32I-NEXT: addi a2, a2, -11394; RV32I-NEXT: and a1, a2, a11395; RV32I-NEXT: sub a0, a0, a11396; RV32I-NEXT: ret1397;1398; RV32ZBB-LABEL: sub_if_uge_i16:1399; RV32ZBB: # %bb.0:1400; RV32ZBB-NEXT: zext.h a2, a01401; RV32ZBB-NEXT: sub a0, a0, a11402; RV32ZBB-NEXT: zext.h a0, a01403; RV32ZBB-NEXT: minu a0, a2, a01404; RV32ZBB-NEXT: ret1405 %cmp = icmp ult i16 %x, %y1406 %select = select i1 %cmp, i16 0, i16 %y1407 %sub = sub nuw i16 %x, %select1408 ret i16 %sub1409}1410 1411define i32 @sub_if_uge_i32(i32 %x, i32 %y) {1412; RV32I-LABEL: sub_if_uge_i32:1413; RV32I: # %bb.0:1414; RV32I-NEXT: sltu a2, a0, a11415; RV32I-NEXT: addi a2, a2, -11416; RV32I-NEXT: and a1, a2, a11417; RV32I-NEXT: sub a0, a0, a11418; RV32I-NEXT: ret1419;1420; RV32ZBB-LABEL: sub_if_uge_i32:1421; RV32ZBB: # %bb.0:1422; RV32ZBB-NEXT: sub a1, a0, a11423; RV32ZBB-NEXT: minu a0, a0, a11424; RV32ZBB-NEXT: ret1425 %cmp = icmp ult i32 %x, %y1426 %select = select i1 %cmp, i32 0, i32 %y1427 %sub = sub nuw i32 %x, %select1428 ret i32 %sub1429}1430 1431define i64 @sub_if_uge_i64(i64 %x, i64 %y) {1432; CHECK-LABEL: sub_if_uge_i64:1433; CHECK: # %bb.0:1434; CHECK-NEXT: beq a1, a3, .LBB52_21435; CHECK-NEXT: # %bb.1:1436; CHECK-NEXT: sltu a4, a1, a31437; CHECK-NEXT: j .LBB52_31438; CHECK-NEXT: .LBB52_2:1439; CHECK-NEXT: sltu a4, a0, a21440; CHECK-NEXT: .LBB52_3:1441; CHECK-NEXT: addi a4, a4, -11442; CHECK-NEXT: and a3, a4, a31443; CHECK-NEXT: and a2, a4, a21444; CHECK-NEXT: sltu a4, a0, a21445; CHECK-NEXT: sub a1, a1, a31446; CHECK-NEXT: sub a1, a1, a41447; CHECK-NEXT: sub a0, a0, a21448; CHECK-NEXT: ret1449 %cmp = icmp ult i64 %x, %y1450 %select = select i1 %cmp, i64 0, i64 %y1451 %sub = sub nuw i64 %x, %select1452 ret i64 %sub1453}1454 1455define i128 @sub_if_uge_i128(i128 %x, i128 %y) {1456; CHECK-LABEL: sub_if_uge_i128:1457; CHECK: # %bb.0:1458; CHECK-NEXT: lw a3, 4(a1)1459; CHECK-NEXT: lw a4, 8(a1)1460; CHECK-NEXT: lw a5, 12(a1)1461; CHECK-NEXT: lw a6, 4(a2)1462; CHECK-NEXT: lw t0, 12(a2)1463; CHECK-NEXT: lw a7, 8(a2)1464; CHECK-NEXT: beq a5, t0, .LBB53_21465; CHECK-NEXT: # %bb.1:1466; CHECK-NEXT: sltu t1, a5, t01467; CHECK-NEXT: j .LBB53_31468; CHECK-NEXT: .LBB53_2:1469; CHECK-NEXT: sltu t1, a4, a71470; CHECK-NEXT: .LBB53_3:1471; CHECK-NEXT: lw a1, 0(a1)1472; CHECK-NEXT: lw a2, 0(a2)1473; CHECK-NEXT: beq a3, a6, .LBB53_51474; CHECK-NEXT: # %bb.4:1475; CHECK-NEXT: sltu t2, a3, a61476; CHECK-NEXT: j .LBB53_61477; CHECK-NEXT: .LBB53_5:1478; CHECK-NEXT: sltu t2, a1, a21479; CHECK-NEXT: .LBB53_6:1480; CHECK-NEXT: xor t3, a5, t01481; CHECK-NEXT: xor t4, a4, a71482; CHECK-NEXT: or t3, t4, t31483; CHECK-NEXT: beqz t3, .LBB53_81484; CHECK-NEXT: # %bb.7:1485; CHECK-NEXT: mv t2, t11486; CHECK-NEXT: .LBB53_8:1487; CHECK-NEXT: addi t3, t2, -11488; CHECK-NEXT: and t2, t3, t01489; CHECK-NEXT: and t0, t3, a21490; CHECK-NEXT: and t1, t3, a61491; CHECK-NEXT: sltu a2, a1, t01492; CHECK-NEXT: and a7, t3, a71493; CHECK-NEXT: mv a6, a21494; CHECK-NEXT: beq a3, t1, .LBB53_101495; CHECK-NEXT: # %bb.9:1496; CHECK-NEXT: sltu a6, a3, t11497; CHECK-NEXT: .LBB53_10:1498; CHECK-NEXT: sub t3, a4, a71499; CHECK-NEXT: sltu a4, a4, a71500; CHECK-NEXT: sub a5, a5, t21501; CHECK-NEXT: sub a3, a3, t11502; CHECK-NEXT: sub a1, a1, t01503; CHECK-NEXT: sltu a7, t3, a61504; CHECK-NEXT: sub a5, a5, a41505; CHECK-NEXT: sub a4, t3, a61506; CHECK-NEXT: sub a3, a3, a21507; CHECK-NEXT: sub a2, a5, a71508; CHECK-NEXT: sw a1, 0(a0)1509; CHECK-NEXT: sw a3, 4(a0)1510; CHECK-NEXT: sw a4, 8(a0)1511; CHECK-NEXT: sw a2, 12(a0)1512; CHECK-NEXT: ret1513 %cmp = icmp ult i128 %x, %y1514 %select = select i1 %cmp, i128 0, i128 %y1515 %sub = sub nuw i128 %x, %select1516 ret i128 %sub1517}1518 1519define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {1520; CHECK-LABEL: sub_if_uge_multiuse_select_i32:1521; CHECK: # %bb.0:1522; CHECK-NEXT: sltu a2, a0, a11523; CHECK-NEXT: addi a2, a2, -11524; CHECK-NEXT: and a1, a2, a11525; CHECK-NEXT: sub a0, a0, a11526; CHECK-NEXT: sll a0, a0, a11527; CHECK-NEXT: ret1528 %cmp = icmp ult i32 %x, %y1529 %select = select i1 %cmp, i32 0, i32 %y1530 %sub = sub nuw i32 %x, %select1531 %shl = shl i32 %sub, %select1532 ret i32 %shl1533}1534 1535define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {1536; RV32I-LABEL: sub_if_uge_multiuse_cmp_i32:1537; RV32I: # %bb.0:1538; RV32I-NEXT: sltu a2, a0, a11539; RV32I-NEXT: addi a2, a2, -11540; RV32I-NEXT: and a2, a2, a11541; RV32I-NEXT: sub a2, a0, a21542; RV32I-NEXT: bltu a0, a1, .LBB55_21543; RV32I-NEXT: # %bb.1:1544; RV32I-NEXT: li a0, 41545; RV32I-NEXT: sll a0, a2, a01546; RV32I-NEXT: ret1547; RV32I-NEXT: .LBB55_2:1548; RV32I-NEXT: li a0, 21549; RV32I-NEXT: sll a0, a2, a01550; RV32I-NEXT: ret1551;1552; RV32ZBB-LABEL: sub_if_uge_multiuse_cmp_i32:1553; RV32ZBB: # %bb.0:1554; RV32ZBB-NEXT: sub a2, a0, a11555; RV32ZBB-NEXT: minu a2, a0, a21556; RV32ZBB-NEXT: bltu a0, a1, .LBB55_21557; RV32ZBB-NEXT: # %bb.1:1558; RV32ZBB-NEXT: li a0, 41559; RV32ZBB-NEXT: sll a0, a2, a01560; RV32ZBB-NEXT: ret1561; RV32ZBB-NEXT: .LBB55_2:1562; RV32ZBB-NEXT: li a0, 21563; RV32ZBB-NEXT: sll a0, a2, a01564; RV32ZBB-NEXT: ret1565 %cmp = icmp ult i32 %x, %y1566 %select = select i1 %cmp, i32 0, i32 %y1567 %sub = sub nuw i32 %x, %select1568 %select2 = select i1 %cmp, i32 2, i32 41569 %shl = shl i32 %sub, %select21570 ret i32 %shl1571}1572 1573define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) {1574; RV32I-LABEL: sub_if_uge_multiuse_cmp_store_i32:1575; RV32I: # %bb.0:1576; RV32I-NEXT: sltu a3, a0, a11577; RV32I-NEXT: xori a4, a3, 11578; RV32I-NEXT: addi a3, a3, -11579; RV32I-NEXT: and a1, a3, a11580; RV32I-NEXT: sub a0, a0, a11581; RV32I-NEXT: sw a4, 0(a2)1582; RV32I-NEXT: ret1583;1584; RV32ZBB-LABEL: sub_if_uge_multiuse_cmp_store_i32:1585; RV32ZBB: # %bb.0:1586; RV32ZBB-NEXT: sltu a3, a0, a11587; RV32ZBB-NEXT: sub a1, a0, a11588; RV32ZBB-NEXT: xori a3, a3, 11589; RV32ZBB-NEXT: minu a0, a0, a11590; RV32ZBB-NEXT: sw a3, 0(a2)1591; RV32ZBB-NEXT: ret1592 %cmp = icmp uge i32 %x, %y1593 %conv = zext i1 %cmp to i321594 store i32 %conv, ptr %z, align 41595 %select = select i1 %cmp, i32 %y, i32 01596 %sub = sub nuw i32 %x, %select1597 ret i32 %sub1598}1599 1600define i8 @sub_if_uge_C_i8(i8 zeroext %x) {1601; RV32I-LABEL: sub_if_uge_C_i8:1602; RV32I: # %bb.0:1603; RV32I-NEXT: sltiu a1, a0, 131604; RV32I-NEXT: addi a1, a1, -11605; RV32I-NEXT: andi a1, a1, -131606; RV32I-NEXT: add a0, a0, a11607; RV32I-NEXT: ret1608;1609; RV32ZBB-LABEL: sub_if_uge_C_i8:1610; RV32ZBB: # %bb.0:1611; RV32ZBB-NEXT: addi a1, a0, -131612; RV32ZBB-NEXT: zext.b a1, a11613; RV32ZBB-NEXT: minu a0, a1, a01614; RV32ZBB-NEXT: ret1615 %cmp = icmp ugt i8 %x, 121616 %sub = add i8 %x, -131617 %conv4 = select i1 %cmp, i8 %sub, i8 %x1618 ret i8 %conv41619}1620 1621define i16 @sub_if_uge_C_i16(i16 zeroext %x) {1622; RV32I-LABEL: sub_if_uge_C_i16:1623; RV32I: # %bb.0:1624; RV32I-NEXT: sltiu a1, a0, 2511625; RV32I-NEXT: addi a1, a1, -11626; RV32I-NEXT: andi a1, a1, -2511627; RV32I-NEXT: add a0, a0, a11628; RV32I-NEXT: ret1629;1630; RV32ZBB-LABEL: sub_if_uge_C_i16:1631; RV32ZBB: # %bb.0:1632; RV32ZBB-NEXT: addi a1, a0, -2511633; RV32ZBB-NEXT: zext.h a1, a11634; RV32ZBB-NEXT: minu a0, a1, a01635; RV32ZBB-NEXT: ret1636 %cmp = icmp ugt i16 %x, 2501637 %sub = add i16 %x, -2511638 %conv4 = select i1 %cmp, i16 %sub, i16 %x1639 ret i16 %conv41640}1641 1642define i32 @sub_if_uge_C_i32(i32 signext %x) {1643; RV32I-LABEL: sub_if_uge_C_i32:1644; RV32I: # %bb.0:1645; RV32I-NEXT: lui a1, 161646; RV32I-NEXT: lui a2, 10485601647; RV32I-NEXT: addi a1, a1, -161648; RV32I-NEXT: sltu a1, a1, a01649; RV32I-NEXT: neg a1, a11650; RV32I-NEXT: addi a2, a2, 151651; RV32I-NEXT: and a1, a1, a21652; RV32I-NEXT: add a0, a0, a11653; RV32I-NEXT: ret1654;1655; RV32ZBB-LABEL: sub_if_uge_C_i32:1656; RV32ZBB: # %bb.0:1657; RV32ZBB-NEXT: lui a1, 10485601658; RV32ZBB-NEXT: addi a1, a1, 151659; RV32ZBB-NEXT: add a1, a0, a11660; RV32ZBB-NEXT: minu a0, a1, a01661; RV32ZBB-NEXT: ret1662 %cmp = icmp ugt i32 %x, 655201663 %sub = add i32 %x, -655211664 %cond = select i1 %cmp, i32 %sub, i32 %x1665 ret i32 %cond1666}1667 1668define i64 @sub_if_uge_C_i64(i64 %x) {1669; CHECK-LABEL: sub_if_uge_C_i64:1670; CHECK: # %bb.0:1671; CHECK-NEXT: li a2, 11672; CHECK-NEXT: beq a1, a2, .LBB60_21673; CHECK-NEXT: # %bb.1:1674; CHECK-NEXT: sltiu a2, a1, 21675; CHECK-NEXT: xori a2, a2, 11676; CHECK-NEXT: j .LBB60_31677; CHECK-NEXT: .LBB60_2:1678; CHECK-NEXT: lui a2, 1721271679; CHECK-NEXT: addi a2, a2, 5111680; CHECK-NEXT: sltu a2, a2, a01681; CHECK-NEXT: .LBB60_3:1682; CHECK-NEXT: neg a2, a21683; CHECK-NEXT: andi a3, a2, -21684; CHECK-NEXT: add a1, a1, a31685; CHECK-NEXT: lui a3, 8764491686; CHECK-NEXT: addi a3, a3, -5121687; CHECK-NEXT: and a2, a2, a31688; CHECK-NEXT: add a2, a0, a21689; CHECK-NEXT: sltu a0, a2, a01690; CHECK-NEXT: add a1, a1, a01691; CHECK-NEXT: mv a0, a21692; CHECK-NEXT: ret1693 %cmp = icmp ugt i64 %x, 49999999991694 %sub = add i64 %x, -50000000001695 %cond = select i1 %cmp, i64 %sub, i64 %x1696 ret i64 %cond1697}1698 1699define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {1700; RV32I-LABEL: sub_if_uge_C_multiuse_cmp_i32:1701; RV32I: # %bb.0:1702; RV32I-NEXT: lui a2, 161703; RV32I-NEXT: lui a3, 10485601704; RV32I-NEXT: addi a2, a2, -161705; RV32I-NEXT: sltu a2, a2, a01706; RV32I-NEXT: neg a4, a21707; RV32I-NEXT: addi a3, a3, 151708; RV32I-NEXT: and a3, a4, a31709; RV32I-NEXT: add a0, a0, a31710; RV32I-NEXT: sw a2, 0(a1)1711; RV32I-NEXT: ret1712;1713; RV32ZBB-LABEL: sub_if_uge_C_multiuse_cmp_i32:1714; RV32ZBB: # %bb.0:1715; RV32ZBB-NEXT: lui a2, 161716; RV32ZBB-NEXT: lui a3, 10485601717; RV32ZBB-NEXT: addi a2, a2, -161718; RV32ZBB-NEXT: addi a3, a3, 151719; RV32ZBB-NEXT: sltu a2, a2, a01720; RV32ZBB-NEXT: add a3, a0, a31721; RV32ZBB-NEXT: minu a0, a3, a01722; RV32ZBB-NEXT: sw a2, 0(a1)1723; RV32ZBB-NEXT: ret1724 %cmp = icmp ugt i32 %x, 655201725 %conv = zext i1 %cmp to i321726 store i32 %conv, ptr %z, align 41727 %sub = add i32 %x, -655211728 %cond = select i1 %cmp, i32 %sub, i32 %x1729 ret i32 %cond1730}1731 1732define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {1733; RV32I-LABEL: sub_if_uge_C_multiuse_sub_i32:1734; RV32I: # %bb.0:1735; RV32I-NEXT: lui a2, 10485601736; RV32I-NEXT: lui a3, 161737; RV32I-NEXT: addi a2, a2, 151738; RV32I-NEXT: add a2, a0, a21739; RV32I-NEXT: addi a3, a3, -161740; RV32I-NEXT: sw a2, 0(a1)1741; RV32I-NEXT: bltu a3, a0, .LBB62_21742; RV32I-NEXT: # %bb.1:1743; RV32I-NEXT: mv a2, a01744; RV32I-NEXT: .LBB62_2:1745; RV32I-NEXT: mv a0, a21746; RV32I-NEXT: ret1747;1748; RV32ZBB-LABEL: sub_if_uge_C_multiuse_sub_i32:1749; RV32ZBB: # %bb.0:1750; RV32ZBB-NEXT: lui a2, 10485601751; RV32ZBB-NEXT: addi a2, a2, 151752; RV32ZBB-NEXT: add a2, a0, a21753; RV32ZBB-NEXT: minu a0, a2, a01754; RV32ZBB-NEXT: sw a2, 0(a1)1755; RV32ZBB-NEXT: ret1756 %sub = add i32 %x, -655211757 store i32 %sub, ptr %z, align 41758 %cmp = icmp ugt i32 %x, 655201759 %cond = select i1 %cmp, i32 %sub, i32 %x1760 ret i32 %cond1761}1762 1763define i32 @sub_if_uge_C_swapped_i32(i32 %x) {1764; RV32I-LABEL: sub_if_uge_C_swapped_i32:1765; RV32I: # %bb.0:1766; RV32I-NEXT: lui a1, 161767; RV32I-NEXT: lui a2, 10485601768; RV32I-NEXT: addi a1, a1, -151769; RV32I-NEXT: sltu a1, a0, a11770; RV32I-NEXT: addi a1, a1, -11771; RV32I-NEXT: addi a2, a2, 151772; RV32I-NEXT: and a1, a1, a21773; RV32I-NEXT: add a0, a0, a11774; RV32I-NEXT: ret1775;1776; RV32ZBB-LABEL: sub_if_uge_C_swapped_i32:1777; RV32ZBB: # %bb.0:1778; RV32ZBB-NEXT: lui a1, 10485601779; RV32ZBB-NEXT: addi a1, a1, 151780; RV32ZBB-NEXT: add a1, a0, a11781; RV32ZBB-NEXT: minu a0, a0, a11782; RV32ZBB-NEXT: ret1783 %cmp = icmp ult i32 %x, 655211784 %sub = add i32 %x, -655211785 %cond = select i1 %cmp, i32 %x, i32 %sub1786 ret i32 %cond1787}1788 1789define i7 @sub_if_uge_C_nsw_i7(i7 %a) {1790; RV32I-LABEL: sub_if_uge_C_nsw_i7:1791; RV32I: # %bb.0:1792; RV32I-NEXT: ori a0, a0, 511793; RV32I-NEXT: andi a1, a0, 1271794; RV32I-NEXT: sltiu a1, a1, 1111795; RV32I-NEXT: addi a1, a1, -11796; RV32I-NEXT: andi a1, a1, 171797; RV32I-NEXT: add a0, a0, a11798; RV32I-NEXT: ret1799;1800; RV32ZBB-LABEL: sub_if_uge_C_nsw_i7:1801; RV32ZBB: # %bb.0:1802; RV32ZBB-NEXT: ori a0, a0, 511803; RV32ZBB-NEXT: andi a1, a0, 1271804; RV32ZBB-NEXT: addi a0, a0, 171805; RV32ZBB-NEXT: andi a0, a0, 921806; RV32ZBB-NEXT: minu a0, a0, a11807; RV32ZBB-NEXT: ret1808 %x = or i7 %a, 511809 %c = icmp ugt i7 %x, -181810 %add = add nsw i7 %x, 171811 %s = select i1 %c, i7 %add, i7 %x1812 ret i7 %s1813}1814 1815define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {1816; RV32I-LABEL: sub_if_uge_C_swapped_nsw_i7:1817; RV32I: # %bb.0:1818; RV32I-NEXT: ori a0, a0, 511819; RV32I-NEXT: andi a1, a0, 1271820; RV32I-NEXT: sltiu a1, a1, 1111821; RV32I-NEXT: addi a1, a1, -11822; RV32I-NEXT: andi a1, a1, 171823; RV32I-NEXT: add a0, a0, a11824; RV32I-NEXT: ret1825;1826; RV32ZBB-LABEL: sub_if_uge_C_swapped_nsw_i7:1827; RV32ZBB: # %bb.0:1828; RV32ZBB-NEXT: ori a0, a0, 511829; RV32ZBB-NEXT: andi a1, a0, 1271830; RV32ZBB-NEXT: addi a0, a0, 171831; RV32ZBB-NEXT: andi a0, a0, 921832; RV32ZBB-NEXT: minu a0, a1, a01833; RV32ZBB-NEXT: ret1834 %x = or i7 %a, 511835 %c = icmp ult i7 %x, -171836 %add = add nsw i7 %x, 171837 %s = select i1 %c, i7 %x, i7 %add1838 ret i7 %s1839}1840