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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBS,RV32ZBSNOZBB6; RUN: llc -mtriple=riscv32 -mattr=+zbs,+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBS,RV32ZBSZBB8 9define i32 @bclr_i32(i32 %a, i32 %b) nounwind {10; RV32I-LABEL: bclr_i32:11; RV32I: # %bb.0:12; RV32I-NEXT: li a2, 113; RV32I-NEXT: sll a1, a2, a114; RV32I-NEXT: not a1, a115; RV32I-NEXT: and a0, a1, a016; RV32I-NEXT: ret17;18; RV32ZBS-LABEL: bclr_i32:19; RV32ZBS: # %bb.0:20; RV32ZBS-NEXT: bclr a0, a0, a121; RV32ZBS-NEXT: ret22 %and = and i32 %b, 3123 %shl = shl nuw i32 1, %and24 %neg = xor i32 %shl, -125 %and1 = and i32 %neg, %a26 ret i32 %and127}28 29define i32 @bclr_i32_no_mask(i32 %a, i32 %b) nounwind {30; RV32I-LABEL: bclr_i32_no_mask:31; RV32I: # %bb.0:32; RV32I-NEXT: li a2, 133; RV32I-NEXT: sll a1, a2, a134; RV32I-NEXT: not a1, a135; RV32I-NEXT: and a0, a1, a036; RV32I-NEXT: ret37;38; RV32ZBS-LABEL: bclr_i32_no_mask:39; RV32ZBS: # %bb.0:40; RV32ZBS-NEXT: bclr a0, a0, a141; RV32ZBS-NEXT: ret42 %shl = shl nuw i32 1, %b43 %neg = xor i32 %shl, -144 %and1 = and i32 %neg, %a45 ret i32 %and146}47 48define i32 @bclr_i32_mask_multiple(i32 %a, i32 %b, i32 %shamt) nounwind {49; RV32I-LABEL: bclr_i32_mask_multiple:50; RV32I: # %bb.0:51; RV32I-NEXT: li a3, 152; RV32I-NEXT: sll a2, a3, a253; RV32I-NEXT: not a3, a254; RV32I-NEXT: and a0, a3, a055; RV32I-NEXT: or a1, a1, a256; RV32I-NEXT: add a0, a0, a157; RV32I-NEXT: ret58;59; RV32ZBS-LABEL: bclr_i32_mask_multiple:60; RV32ZBS: # %bb.0:61; RV32ZBS-NEXT: bclr a0, a0, a262; RV32ZBS-NEXT: bset a1, a1, a263; RV32ZBS-NEXT: add a0, a0, a164; RV32ZBS-NEXT: ret65 %shamt_masked = and i32 %shamt, 6366 %shl = shl nuw i32 1, %shamt_masked67 %neg = xor i32 %shl, -168 %and = and i32 %neg, %a69 %or = or i32 %b, %shl70 %c = add i32 %and, %or71 ret i32 %c72}73 74define i64 @bclr_i64(i64 %a, i64 %b) nounwind {75; RV32I-LABEL: bclr_i64:76; RV32I: # %bb.0:77; RV32I-NEXT: andi a3, a2, 6378; RV32I-NEXT: li a4, 179; RV32I-NEXT: addi a5, a3, -3280; RV32I-NEXT: sll a2, a4, a281; RV32I-NEXT: sll a3, a4, a382; RV32I-NEXT: srli a5, a5, 3183; RV32I-NEXT: neg a4, a584; RV32I-NEXT: addi a5, a5, -185; RV32I-NEXT: and a2, a4, a286; RV32I-NEXT: and a3, a5, a387; RV32I-NEXT: not a2, a288; RV32I-NEXT: not a3, a389; RV32I-NEXT: and a0, a2, a090; RV32I-NEXT: and a1, a3, a191; RV32I-NEXT: ret92;93; RV32ZBSNOZBB-LABEL: bclr_i64:94; RV32ZBSNOZBB: # %bb.0:95; RV32ZBSNOZBB-NEXT: andi a3, a2, 6396; RV32ZBSNOZBB-NEXT: bset a2, zero, a297; RV32ZBSNOZBB-NEXT: addi a4, a3, -3298; RV32ZBSNOZBB-NEXT: bset a3, zero, a399; RV32ZBSNOZBB-NEXT: srli a4, a4, 31100; RV32ZBSNOZBB-NEXT: neg a5, a4101; RV32ZBSNOZBB-NEXT: addi a4, a4, -1102; RV32ZBSNOZBB-NEXT: and a2, a5, a2103; RV32ZBSNOZBB-NEXT: and a3, a4, a3104; RV32ZBSNOZBB-NEXT: not a3, a3105; RV32ZBSNOZBB-NEXT: not a2, a2106; RV32ZBSNOZBB-NEXT: and a0, a2, a0107; RV32ZBSNOZBB-NEXT: and a1, a3, a1108; RV32ZBSNOZBB-NEXT: ret109;110; RV32ZBSZBB-LABEL: bclr_i64:111; RV32ZBSZBB: # %bb.0:112; RV32ZBSZBB-NEXT: andi a3, a2, 63113; RV32ZBSZBB-NEXT: bset a2, zero, a2114; RV32ZBSZBB-NEXT: bset a4, zero, a3115; RV32ZBSZBB-NEXT: addi a3, a3, -32116; RV32ZBSZBB-NEXT: srli a3, a3, 31117; RV32ZBSZBB-NEXT: addi a5, a3, -1118; RV32ZBSZBB-NEXT: neg a3, a3119; RV32ZBSZBB-NEXT: and a4, a5, a4120; RV32ZBSZBB-NEXT: and a2, a3, a2121; RV32ZBSZBB-NEXT: andn a0, a0, a2122; RV32ZBSZBB-NEXT: andn a1, a1, a4123; RV32ZBSZBB-NEXT: ret124 %and = and i64 %b, 63125 %shl = shl nuw i64 1, %and126 %neg = xor i64 %shl, -1127 %and1 = and i64 %neg, %a128 ret i64 %and1129}130 131define i32 @bset_i32(i32 %a, i32 %b) nounwind {132; RV32I-LABEL: bset_i32:133; RV32I: # %bb.0:134; RV32I-NEXT: li a2, 1135; RV32I-NEXT: sll a1, a2, a1136; RV32I-NEXT: or a0, a1, a0137; RV32I-NEXT: ret138;139; RV32ZBS-LABEL: bset_i32:140; RV32ZBS: # %bb.0:141; RV32ZBS-NEXT: bset a0, a0, a1142; RV32ZBS-NEXT: ret143 %and = and i32 %b, 31144 %shl = shl nuw i32 1, %and145 %or = or i32 %shl, %a146 ret i32 %or147}148 149define i32 @bset_i32_no_mask(i32 %a, i32 %b) nounwind {150; RV32I-LABEL: bset_i32_no_mask:151; RV32I: # %bb.0:152; RV32I-NEXT: li a2, 1153; RV32I-NEXT: sll a1, a2, a1154; RV32I-NEXT: or a0, a1, a0155; RV32I-NEXT: ret156;157; RV32ZBS-LABEL: bset_i32_no_mask:158; RV32ZBS: # %bb.0:159; RV32ZBS-NEXT: bset a0, a0, a1160; RV32ZBS-NEXT: ret161 %shl = shl nuw i32 1, %b162 %or = or i32 %shl, %a163 ret i32 %or164}165 166; We can use bsetw for 1 << x by setting the first source to zero.167define signext i32 @bset_i32_zero(i32 signext %a) nounwind {168; RV32I-LABEL: bset_i32_zero:169; RV32I: # %bb.0:170; RV32I-NEXT: li a1, 1171; RV32I-NEXT: sll a0, a1, a0172; RV32I-NEXT: ret173;174; RV32ZBS-LABEL: bset_i32_zero:175; RV32ZBS: # %bb.0:176; RV32ZBS-NEXT: bset a0, zero, a0177; RV32ZBS-NEXT: ret178 %shl = shl i32 1, %a179 ret i32 %shl180}181 182; As we are not matching directly i64 code patterns on RV32 some i64 patterns183; don't have yet any matching bit manipulation instructions on RV32.184; This test is presented here in case future expansions of the Bitmanip185; extensions introduce instructions suitable for this pattern.186 187define i64 @bset_i64(i64 %a, i64 %b) nounwind {188; RV32I-LABEL: bset_i64:189; RV32I: # %bb.0:190; RV32I-NEXT: li a3, 1191; RV32I-NEXT: sll a2, a3, a2192; RV32I-NEXT: srai a3, a2, 31193; RV32I-NEXT: or a0, a2, a0194; RV32I-NEXT: or a1, a3, a1195; RV32I-NEXT: ret196;197; RV32ZBS-LABEL: bset_i64:198; RV32ZBS: # %bb.0:199; RV32ZBS-NEXT: bset a3, zero, a2200; RV32ZBS-NEXT: srai a3, a3, 31201; RV32ZBS-NEXT: bset a0, a0, a2202; RV32ZBS-NEXT: or a1, a3, a1203; RV32ZBS-NEXT: ret204 %1 = trunc i64 %b to i32205 %conv = and i32 %1, 63206 %shl = shl nuw i32 1, %conv207 %conv1 = sext i32 %shl to i64208 %or = or i64 %conv1, %a209 ret i64 %or210}211 212define signext i64 @bset_i64_zero(i64 signext %a) nounwind {213; RV32I-LABEL: bset_i64_zero:214; RV32I: # %bb.0:215; RV32I-NEXT: addi a1, a0, -32216; RV32I-NEXT: li a2, 1217; RV32I-NEXT: srli a1, a1, 31218; RV32I-NEXT: sll a2, a2, a0219; RV32I-NEXT: neg a0, a1220; RV32I-NEXT: addi a1, a1, -1221; RV32I-NEXT: and a0, a0, a2222; RV32I-NEXT: and a1, a1, a2223; RV32I-NEXT: ret224;225; RV32ZBS-LABEL: bset_i64_zero:226; RV32ZBS: # %bb.0:227; RV32ZBS-NEXT: addi a1, a0, -32228; RV32ZBS-NEXT: bset a2, zero, a0229; RV32ZBS-NEXT: srli a1, a1, 31230; RV32ZBS-NEXT: neg a0, a1231; RV32ZBS-NEXT: addi a1, a1, -1232; RV32ZBS-NEXT: and a0, a0, a2233; RV32ZBS-NEXT: and a1, a1, a2234; RV32ZBS-NEXT: ret235 %shl = shl i64 1, %a236 ret i64 %shl237}238 239define i32 @binv_i32(i32 %a, i32 %b) nounwind {240; RV32I-LABEL: binv_i32:241; RV32I: # %bb.0:242; RV32I-NEXT: li a2, 1243; RV32I-NEXT: sll a1, a2, a1244; RV32I-NEXT: xor a0, a1, a0245; RV32I-NEXT: ret246;247; RV32ZBS-LABEL: binv_i32:248; RV32ZBS: # %bb.0:249; RV32ZBS-NEXT: binv a0, a0, a1250; RV32ZBS-NEXT: ret251 %and = and i32 %b, 31252 %shl = shl nuw i32 1, %and253 %xor = xor i32 %shl, %a254 ret i32 %xor255}256 257; As we are not matching directly i64 code patterns on RV32 some i64 patterns258; don't have yet any matching bit manipulation instructions on RV32.259; This test is presented here in case future expansions of the Bitmanip260; extensions introduce instructions suitable for this pattern.261 262define i64 @binv_i64(i64 %a, i64 %b) nounwind {263; RV32I-LABEL: binv_i64:264; RV32I: # %bb.0:265; RV32I-NEXT: li a3, 1266; RV32I-NEXT: sll a2, a3, a2267; RV32I-NEXT: srai a3, a2, 31268; RV32I-NEXT: xor a0, a2, a0269; RV32I-NEXT: xor a1, a3, a1270; RV32I-NEXT: ret271;272; RV32ZBS-LABEL: binv_i64:273; RV32ZBS: # %bb.0:274; RV32ZBS-NEXT: bset a3, zero, a2275; RV32ZBS-NEXT: srai a3, a3, 31276; RV32ZBS-NEXT: binv a0, a0, a2277; RV32ZBS-NEXT: xor a1, a3, a1278; RV32ZBS-NEXT: ret279 %1 = trunc i64 %b to i32280 %conv = and i32 %1, 63281 %shl = shl nuw i32 1, %conv282 %conv1 = sext i32 %shl to i64283 %xor = xor i64 %conv1, %a284 ret i64 %xor285}286 287define i32 @bext_i32(i32 %a, i32 %b) nounwind {288; RV32I-LABEL: bext_i32:289; RV32I: # %bb.0:290; RV32I-NEXT: srl a0, a0, a1291; RV32I-NEXT: andi a0, a0, 1292; RV32I-NEXT: ret293;294; RV32ZBS-LABEL: bext_i32:295; RV32ZBS: # %bb.0:296; RV32ZBS-NEXT: bext a0, a0, a1297; RV32ZBS-NEXT: ret298 %and = and i32 %b, 31299 %shr = lshr i32 %a, %and300 %and1 = and i32 %shr, 1301 ret i32 %and1302}303 304define i32 @bext_i32_no_mask(i32 %a, i32 %b) nounwind {305; RV32I-LABEL: bext_i32_no_mask:306; RV32I: # %bb.0:307; RV32I-NEXT: srl a0, a0, a1308; RV32I-NEXT: andi a0, a0, 1309; RV32I-NEXT: ret310;311; RV32ZBS-LABEL: bext_i32_no_mask:312; RV32ZBS: # %bb.0:313; RV32ZBS-NEXT: bext a0, a0, a1314; RV32ZBS-NEXT: ret315 %shr = lshr i32 %a, %b316 %and1 = and i32 %shr, 1317 ret i32 %and1318}319 320; As we are not matching directly i64 code patterns on RV32 some i64 patterns321; don't have yet any matching bit manipulation instructions on RV32.322; This test is presented here in case future expansions of the Bitmanip323; extensions introduce instructions suitable for this pattern.324 325define i64 @bext_i64(i64 %a, i64 %b) nounwind {326; CHECK-LABEL: bext_i64:327; CHECK: # %bb.0:328; CHECK-NEXT: andi a3, a2, 63329; CHECK-NEXT: addi a4, a3, -32330; CHECK-NEXT: bltz a4, .LBB13_2331; CHECK-NEXT: # %bb.1:332; CHECK-NEXT: srl a0, a1, a3333; CHECK-NEXT: j .LBB13_3334; CHECK-NEXT: .LBB13_2:335; CHECK-NEXT: srl a0, a0, a2336; CHECK-NEXT: slli a1, a1, 1337; CHECK-NEXT: not a2, a3338; CHECK-NEXT: sll a1, a1, a2339; CHECK-NEXT: or a0, a0, a1340; CHECK-NEXT: .LBB13_3:341; CHECK-NEXT: andi a0, a0, 1342; CHECK-NEXT: li a1, 0343; CHECK-NEXT: ret344 %conv = and i64 %b, 63345 %shr = lshr i64 %a, %conv346 %and1 = and i64 %shr, 1347 ret i64 %and1348}349 350define i32 @bexti_i32(i32 %a) nounwind {351; RV32I-LABEL: bexti_i32:352; RV32I: # %bb.0:353; RV32I-NEXT: slli a0, a0, 26354; RV32I-NEXT: srli a0, a0, 31355; RV32I-NEXT: ret356;357; RV32ZBS-LABEL: bexti_i32:358; RV32ZBS: # %bb.0:359; RV32ZBS-NEXT: bexti a0, a0, 5360; RV32ZBS-NEXT: ret361 %shr = lshr i32 %a, 5362 %and = and i32 %shr, 1363 ret i32 %and364}365 366define i64 @bexti_i64(i64 %a) nounwind {367; RV32I-LABEL: bexti_i64:368; RV32I: # %bb.0:369; RV32I-NEXT: slli a0, a0, 26370; RV32I-NEXT: srli a0, a0, 31371; RV32I-NEXT: li a1, 0372; RV32I-NEXT: ret373;374; RV32ZBS-LABEL: bexti_i64:375; RV32ZBS: # %bb.0:376; RV32ZBS-NEXT: bexti a0, a0, 5377; RV32ZBS-NEXT: li a1, 0378; RV32ZBS-NEXT: ret379 %shr = lshr i64 %a, 5380 %and = and i64 %shr, 1381 ret i64 %and382}383 384define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {385; RV32I-LABEL: bexti_i32_cmp:386; RV32I: # %bb.0:387; RV32I-NEXT: slli a0, a0, 26388; RV32I-NEXT: srli a0, a0, 31389; RV32I-NEXT: ret390;391; RV32ZBS-LABEL: bexti_i32_cmp:392; RV32ZBS: # %bb.0:393; RV32ZBS-NEXT: bexti a0, a0, 5394; RV32ZBS-NEXT: ret395 %and = and i32 %a, 32396 %cmp = icmp ne i32 %and, 0397 %zext = zext i1 %cmp to i32398 ret i32 %zext399}400 401define i64 @bexti_i64_cmp(i64 %a) nounwind {402; RV32I-LABEL: bexti_i64_cmp:403; RV32I: # %bb.0:404; RV32I-NEXT: slli a0, a0, 26405; RV32I-NEXT: srli a0, a0, 31406; RV32I-NEXT: li a1, 0407; RV32I-NEXT: ret408;409; RV32ZBS-LABEL: bexti_i64_cmp:410; RV32ZBS: # %bb.0:411; RV32ZBS-NEXT: bexti a0, a0, 5412; RV32ZBS-NEXT: li a1, 0413; RV32ZBS-NEXT: ret414 %and = and i64 %a, 32415 %cmp = icmp ne i64 %and, 0416 %zext = zext i1 %cmp to i64417 ret i64 %zext418}419 420define i32 @bclri_i32_10(i32 %a) nounwind {421; CHECK-LABEL: bclri_i32_10:422; CHECK: # %bb.0:423; CHECK-NEXT: andi a0, a0, -1025424; CHECK-NEXT: ret425 %and = and i32 %a, -1025426 ret i32 %and427}428 429define i32 @bclri_i32_11(i32 %a) nounwind {430; RV32I-LABEL: bclri_i32_11:431; RV32I: # %bb.0:432; RV32I-NEXT: lui a1, 1048575433; RV32I-NEXT: addi a1, a1, 2047434; RV32I-NEXT: and a0, a0, a1435; RV32I-NEXT: ret436;437; RV32ZBS-LABEL: bclri_i32_11:438; RV32ZBS: # %bb.0:439; RV32ZBS-NEXT: bclri a0, a0, 11440; RV32ZBS-NEXT: ret441 %and = and i32 %a, -2049442 ret i32 %and443}444 445define i32 @bclri_i32_30(i32 %a) nounwind {446; RV32I-LABEL: bclri_i32_30:447; RV32I: # %bb.0:448; RV32I-NEXT: lui a1, 786432449; RV32I-NEXT: addi a1, a1, -1450; RV32I-NEXT: and a0, a0, a1451; RV32I-NEXT: ret452;453; RV32ZBS-LABEL: bclri_i32_30:454; RV32ZBS: # %bb.0:455; RV32ZBS-NEXT: bclri a0, a0, 30456; RV32ZBS-NEXT: ret457 %and = and i32 %a, -1073741825458 ret i32 %and459}460 461define i32 @bclri_i32_31(i32 %a) nounwind {462; RV32I-LABEL: bclri_i32_31:463; RV32I: # %bb.0:464; RV32I-NEXT: slli a0, a0, 1465; RV32I-NEXT: srli a0, a0, 1466; RV32I-NEXT: ret467;468; RV32ZBS-LABEL: bclri_i32_31:469; RV32ZBS: # %bb.0:470; RV32ZBS-NEXT: bclri a0, a0, 31471; RV32ZBS-NEXT: ret472 %and = and i32 %a, -2147483649473 ret i32 %and474}475 476define i32 @bclri_i32_large0(i32 %a) nounwind {477; RV32I-LABEL: bclri_i32_large0:478; RV32I: # %bb.0:479; RV32I-NEXT: lui a1, 1044480480; RV32I-NEXT: addi a1, a1, -256481; RV32I-NEXT: and a0, a0, a1482; RV32I-NEXT: ret483;484; RV32ZBS-LABEL: bclri_i32_large0:485; RV32ZBS: # %bb.0:486; RV32ZBS-NEXT: andi a0, a0, -256487; RV32ZBS-NEXT: bclri a0, a0, 24488; RV32ZBS-NEXT: ret489 %and = and i32 %a, -16777472490 ret i32 %and491}492 493define i32 @bclri_i32_large1(i32 %a) nounwind {494; RV32I-LABEL: bclri_i32_large1:495; RV32I: # %bb.0:496; RV32I-NEXT: lui a1, 1044464497; RV32I-NEXT: addi a1, a1, -1498; RV32I-NEXT: and a0, a0, a1499; RV32I-NEXT: ret500;501; RV32ZBS-LABEL: bclri_i32_large1:502; RV32ZBS: # %bb.0:503; RV32ZBS-NEXT: bclri a0, a0, 16504; RV32ZBS-NEXT: bclri a0, a0, 24505; RV32ZBS-NEXT: ret506 %and = and i32 %a, -16842753507 ret i32 %and508}509 510define i32 @bclri_i32_large2(i32 %0) {511; RV32I-LABEL: bclri_i32_large2:512; RV32I: # %bb.0:513; RV32I-NEXT: lui a1, 524288514; RV32I-NEXT: addi a1, a1, -5515; RV32I-NEXT: and a0, a0, a1516; RV32I-NEXT: ret517;518; RV32ZBS-LABEL: bclri_i32_large2:519; RV32ZBS: # %bb.0:520; RV32ZBS-NEXT: bclri a0, a0, 2521; RV32ZBS-NEXT: bclri a0, a0, 31522; RV32ZBS-NEXT: ret523 %2 = and i32 %0, 2147483643524 ret i32 %2525}526 527define i32 @bclri_i32_large3(i32 %0) {528; RV32I-LABEL: bclri_i32_large3:529; RV32I: # %bb.0:530; RV32I-NEXT: lui a1, 524288531; RV32I-NEXT: addi a1, a1, -6532; RV32I-NEXT: and a0, a0, a1533; RV32I-NEXT: ret534;535; RV32ZBS-LABEL: bclri_i32_large3:536; RV32ZBS: # %bb.0:537; RV32ZBS-NEXT: andi a0, a0, -6538; RV32ZBS-NEXT: bclri a0, a0, 31539; RV32ZBS-NEXT: ret540 %2 = and i32 %0, 2147483642541 ret i32 %2542}543 544define i32 @bseti_i32_10(i32 %a) nounwind {545; CHECK-LABEL: bseti_i32_10:546; CHECK: # %bb.0:547; CHECK-NEXT: ori a0, a0, 1024548; CHECK-NEXT: ret549 %or = or i32 %a, 1024550 ret i32 %or551}552 553define i32 @bseti_i32_11(i32 %a) nounwind {554; RV32I-LABEL: bseti_i32_11:555; RV32I: # %bb.0:556; RV32I-NEXT: li a1, 1557; RV32I-NEXT: slli a1, a1, 11558; RV32I-NEXT: or a0, a0, a1559; RV32I-NEXT: ret560;561; RV32ZBS-LABEL: bseti_i32_11:562; RV32ZBS: # %bb.0:563; RV32ZBS-NEXT: bseti a0, a0, 11564; RV32ZBS-NEXT: ret565 %or = or i32 %a, 2048566 ret i32 %or567}568 569define i32 @bseti_i32_30(i32 %a) nounwind {570; RV32I-LABEL: bseti_i32_30:571; RV32I: # %bb.0:572; RV32I-NEXT: lui a1, 262144573; RV32I-NEXT: or a0, a0, a1574; RV32I-NEXT: ret575;576; RV32ZBS-LABEL: bseti_i32_30:577; RV32ZBS: # %bb.0:578; RV32ZBS-NEXT: bseti a0, a0, 30579; RV32ZBS-NEXT: ret580 %or = or i32 %a, 1073741824581 ret i32 %or582}583 584define i32 @bseti_i32_31(i32 %a) nounwind {585; RV32I-LABEL: bseti_i32_31:586; RV32I: # %bb.0:587; RV32I-NEXT: lui a1, 524288588; RV32I-NEXT: or a0, a0, a1589; RV32I-NEXT: ret590;591; RV32ZBS-LABEL: bseti_i32_31:592; RV32ZBS: # %bb.0:593; RV32ZBS-NEXT: bseti a0, a0, 31594; RV32ZBS-NEXT: ret595 %or = or i32 %a, 2147483648596 ret i32 %or597}598 599define i32 @binvi_i32_10(i32 %a) nounwind {600; CHECK-LABEL: binvi_i32_10:601; CHECK: # %bb.0:602; CHECK-NEXT: xori a0, a0, 1024603; CHECK-NEXT: ret604 %xor = xor i32 %a, 1024605 ret i32 %xor606}607 608define i32 @binvi_i32_11(i32 %a) nounwind {609; RV32I-LABEL: binvi_i32_11:610; RV32I: # %bb.0:611; RV32I-NEXT: li a1, 1612; RV32I-NEXT: slli a1, a1, 11613; RV32I-NEXT: xor a0, a0, a1614; RV32I-NEXT: ret615;616; RV32ZBS-LABEL: binvi_i32_11:617; RV32ZBS: # %bb.0:618; RV32ZBS-NEXT: binvi a0, a0, 11619; RV32ZBS-NEXT: ret620 %xor = xor i32 %a, 2048621 ret i32 %xor622}623 624define i32 @binvi_i32_30(i32 %a) nounwind {625; RV32I-LABEL: binvi_i32_30:626; RV32I: # %bb.0:627; RV32I-NEXT: lui a1, 262144628; RV32I-NEXT: xor a0, a0, a1629; RV32I-NEXT: ret630;631; RV32ZBS-LABEL: binvi_i32_30:632; RV32ZBS: # %bb.0:633; RV32ZBS-NEXT: binvi a0, a0, 30634; RV32ZBS-NEXT: ret635 %xor = xor i32 %a, 1073741824636 ret i32 %xor637}638 639define i32 @binvi_i32_31(i32 %a) nounwind {640; RV32I-LABEL: binvi_i32_31:641; RV32I: # %bb.0:642; RV32I-NEXT: lui a1, 524288643; RV32I-NEXT: xor a0, a0, a1644; RV32I-NEXT: ret645;646; RV32ZBS-LABEL: binvi_i32_31:647; RV32ZBS: # %bb.0:648; RV32ZBS-NEXT: binvi a0, a0, 31649; RV32ZBS-NEXT: ret650 %xor = xor i32 %a, 2147483648651 ret i32 %xor652}653 654define i32 @xor_i32_4098(i32 %a) nounwind {655; RV32I-LABEL: xor_i32_4098:656; RV32I: # %bb.0:657; RV32I-NEXT: lui a1, 1658; RV32I-NEXT: addi a1, a1, 2659; RV32I-NEXT: xor a0, a0, a1660; RV32I-NEXT: ret661;662; RV32ZBS-LABEL: xor_i32_4098:663; RV32ZBS: # %bb.0:664; RV32ZBS-NEXT: binvi a0, a0, 1665; RV32ZBS-NEXT: binvi a0, a0, 12666; RV32ZBS-NEXT: ret667 %xor = xor i32 %a, 4098668 ret i32 %xor669}670 671define i32 @xor_i32_4099(i32 %a) nounwind {672; RV32I-LABEL: xor_i32_4099:673; RV32I: # %bb.0:674; RV32I-NEXT: lui a1, 1675; RV32I-NEXT: addi a1, a1, 3676; RV32I-NEXT: xor a0, a0, a1677; RV32I-NEXT: ret678;679; RV32ZBS-LABEL: xor_i32_4099:680; RV32ZBS: # %bb.0:681; RV32ZBS-NEXT: xori a0, a0, 3682; RV32ZBS-NEXT: binvi a0, a0, 12683; RV32ZBS-NEXT: ret684 %xor = xor i32 %a, 4099685 ret i32 %xor686}687 688define i32 @xor_i32_96(i32 %a) nounwind {689; CHECK-LABEL: xor_i32_96:690; CHECK: # %bb.0:691; CHECK-NEXT: xori a0, a0, 96692; CHECK-NEXT: ret693 %xor = xor i32 %a, 96694 ret i32 %xor695}696 697define i32 @xor_i32_66901(i32 %a) nounwind {698; RV32I-LABEL: xor_i32_66901:699; RV32I: # %bb.0:700; RV32I-NEXT: lui a1, 16701; RV32I-NEXT: addi a1, a1, 1365702; RV32I-NEXT: xor a0, a0, a1703; RV32I-NEXT: ret704;705; RV32ZBS-LABEL: xor_i32_66901:706; RV32ZBS: # %bb.0:707; RV32ZBS-NEXT: xori a0, a0, 1365708; RV32ZBS-NEXT: binvi a0, a0, 16709; RV32ZBS-NEXT: ret710 %xor = xor i32 %a, 66901711 ret i32 %xor712}713 714define i32 @or_i32_4098(i32 %a) nounwind {715; RV32I-LABEL: or_i32_4098:716; RV32I: # %bb.0:717; RV32I-NEXT: lui a1, 1718; RV32I-NEXT: addi a1, a1, 2719; RV32I-NEXT: or a0, a0, a1720; RV32I-NEXT: ret721;722; RV32ZBS-LABEL: or_i32_4098:723; RV32ZBS: # %bb.0:724; RV32ZBS-NEXT: bseti a0, a0, 1725; RV32ZBS-NEXT: bseti a0, a0, 12726; RV32ZBS-NEXT: ret727 %or = or i32 %a, 4098728 ret i32 %or729}730 731define i32 @or_i32_4099(i32 %a) nounwind {732; RV32I-LABEL: or_i32_4099:733; RV32I: # %bb.0:734; RV32I-NEXT: lui a1, 1735; RV32I-NEXT: addi a1, a1, 3736; RV32I-NEXT: or a0, a0, a1737; RV32I-NEXT: ret738;739; RV32ZBS-LABEL: or_i32_4099:740; RV32ZBS: # %bb.0:741; RV32ZBS-NEXT: ori a0, a0, 3742; RV32ZBS-NEXT: bseti a0, a0, 12743; RV32ZBS-NEXT: ret744 %or = or i32 %a, 4099745 ret i32 %or746}747 748define i32 @or_i32_96(i32 %a) nounwind {749; CHECK-LABEL: or_i32_96:750; CHECK: # %bb.0:751; CHECK-NEXT: ori a0, a0, 96752; CHECK-NEXT: ret753 %or = or i32 %a, 96754 ret i32 %or755}756 757define i32 @or_i32_66901(i32 %a) nounwind {758; RV32I-LABEL: or_i32_66901:759; RV32I: # %bb.0:760; RV32I-NEXT: lui a1, 16761; RV32I-NEXT: addi a1, a1, 1365762; RV32I-NEXT: or a0, a0, a1763; RV32I-NEXT: ret764;765; RV32ZBS-LABEL: or_i32_66901:766; RV32ZBS: # %bb.0:767; RV32ZBS-NEXT: ori a0, a0, 1365768; RV32ZBS-NEXT: bseti a0, a0, 16769; RV32ZBS-NEXT: ret770 %or = or i32 %a, 66901771 ret i32 %or772}773 774define i32 @bset_trailing_ones_i32_mask(i32 %a) nounwind {775; RV32I-LABEL: bset_trailing_ones_i32_mask:776; RV32I: # %bb.0:777; RV32I-NEXT: li a1, -1778; RV32I-NEXT: sll a0, a1, a0779; RV32I-NEXT: not a0, a0780; RV32I-NEXT: ret781;782; RV32ZBS-LABEL: bset_trailing_ones_i32_mask:783; RV32ZBS: # %bb.0:784; RV32ZBS-NEXT: bset a0, zero, a0785; RV32ZBS-NEXT: addi a0, a0, -1786; RV32ZBS-NEXT: ret787 %and = and i32 %a, 31788 %shift = shl nsw i32 -1, %and789 %not = xor i32 %shift, -1790 ret i32 %not791}792 793define i32 @bset_trailing_ones_i32_no_mask(i32 %a) nounwind {794; RV32I-LABEL: bset_trailing_ones_i32_no_mask:795; RV32I: # %bb.0:796; RV32I-NEXT: li a1, -1797; RV32I-NEXT: sll a0, a1, a0798; RV32I-NEXT: not a0, a0799; RV32I-NEXT: ret800;801; RV32ZBS-LABEL: bset_trailing_ones_i32_no_mask:802; RV32ZBS: # %bb.0:803; RV32ZBS-NEXT: bset a0, zero, a0804; RV32ZBS-NEXT: addi a0, a0, -1805; RV32ZBS-NEXT: ret806 %shift = shl nsw i32 -1, %a807 %not = xor i32 %shift, -1808 ret i32 %not809}810 811define i64 @bset_trailing_ones_i64_mask(i64 %a) nounwind {812; CHECK-LABEL: bset_trailing_ones_i64_mask:813; CHECK: # %bb.0:814; CHECK-NEXT: andi a2, a0, 63815; CHECK-NEXT: li a3, -1816; CHECK-NEXT: addi a1, a2, -32817; CHECK-NEXT: sll a0, a3, a0818; CHECK-NEXT: bltz a1, .LBB44_2819; CHECK-NEXT: # %bb.1:820; CHECK-NEXT: sll a2, a3, a2821; CHECK-NEXT: j .LBB44_3822; CHECK-NEXT: .LBB44_2:823; CHECK-NEXT: not a2, a2824; CHECK-NEXT: lui a3, 524288825; CHECK-NEXT: addi a3, a3, -1826; CHECK-NEXT: srl a2, a3, a2827; CHECK-NEXT: or a2, a0, a2828; CHECK-NEXT: .LBB44_3:829; CHECK-NEXT: srai a1, a1, 31830; CHECK-NEXT: and a0, a1, a0831; CHECK-NEXT: not a1, a2832; CHECK-NEXT: not a0, a0833; CHECK-NEXT: ret834 %and = and i64 %a, 63835 %shift = shl nsw i64 -1, %and836 %not = xor i64 %shift, -1837 ret i64 %not838}839 840define i64 @bset_trailing_ones_i64_no_mask(i64 %a) nounwind {841; CHECK-LABEL: bset_trailing_ones_i64_no_mask:842; CHECK: # %bb.0:843; CHECK-NEXT: li a1, -1844; CHECK-NEXT: addi a2, a0, -32845; CHECK-NEXT: sll a1, a1, a0846; CHECK-NEXT: bltz a2, .LBB45_2847; CHECK-NEXT: # %bb.1:848; CHECK-NEXT: mv a0, a1849; CHECK-NEXT: j .LBB45_3850; CHECK-NEXT: .LBB45_2:851; CHECK-NEXT: not a0, a0852; CHECK-NEXT: lui a3, 524288853; CHECK-NEXT: addi a3, a3, -1854; CHECK-NEXT: srl a0, a3, a0855; CHECK-NEXT: or a0, a1, a0856; CHECK-NEXT: .LBB45_3:857; CHECK-NEXT: srai a2, a2, 31858; CHECK-NEXT: and a2, a2, a1859; CHECK-NEXT: not a1, a0860; CHECK-NEXT: not a0, a2861; CHECK-NEXT: ret862 %shift = shl nsw i64 -1, %a863 %not = xor i64 %shift, -1864 ret i64 %not865}866 867define i1 @icmp_eq_pow2(i32 %x) nounwind {868; RV32I-LABEL: icmp_eq_pow2:869; RV32I: # %bb.0:870; RV32I-NEXT: lui a1, 8871; RV32I-NEXT: xor a0, a0, a1872; RV32I-NEXT: seqz a0, a0873; RV32I-NEXT: ret874;875; RV32ZBS-LABEL: icmp_eq_pow2:876; RV32ZBS: # %bb.0:877; RV32ZBS-NEXT: binvi a0, a0, 15878; RV32ZBS-NEXT: seqz a0, a0879; RV32ZBS-NEXT: ret880 %cmp = icmp eq i32 %x, 32768881 ret i1 %cmp882}883 884define i1 @icmp_ne_pow2(i32 %x) nounwind {885; RV32I-LABEL: icmp_ne_pow2:886; RV32I: # %bb.0:887; RV32I-NEXT: lui a1, 8888; RV32I-NEXT: xor a0, a0, a1889; RV32I-NEXT: seqz a0, a0890; RV32I-NEXT: ret891;892; RV32ZBS-LABEL: icmp_ne_pow2:893; RV32ZBS: # %bb.0:894; RV32ZBS-NEXT: binvi a0, a0, 15895; RV32ZBS-NEXT: seqz a0, a0896; RV32ZBS-NEXT: ret897 %cmp = icmp eq i32 %x, 32768898 ret i1 %cmp899}900 901define i1 @icmp_eq_nonpow2(i32 %x) nounwind {902; CHECK-LABEL: icmp_eq_nonpow2:903; CHECK: # %bb.0:904; CHECK-NEXT: lui a1, 8905; CHECK-NEXT: addi a1, a1, -1906; CHECK-NEXT: xor a0, a0, a1907; CHECK-NEXT: seqz a0, a0908; CHECK-NEXT: ret909 %cmp = icmp eq i32 %x, 32767910 ret i1 %cmp911}912