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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define i128 @test_R_wide_scalar_simple(i128 noundef %0) nounwind {6; CHECK-LABEL: test_R_wide_scalar_simple:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: #APP9; CHECK-NEXT: # a2 <- a010; CHECK-NEXT: #NO_APP11; CHECK-NEXT: mv a0, a212; CHECK-NEXT: mv a1, a313; CHECK-NEXT: ret14entry:15 %1 = call i128 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i128 %0)16 ret i128 %117}18 19define i64 @test_R_wide_scalar_with_ops(i64 noundef %0) nounwind {20; CHECK-LABEL: test_R_wide_scalar_with_ops:21; CHECK: # %bb.0: # %entry22; CHECK-NEXT: mv a1, a023; CHECK-NEXT: #APP24; CHECK-NEXT: # a2 <- a025; CHECK-NEXT: #NO_APP26; CHECK-NEXT: or a0, a2, a327; CHECK-NEXT: ret28entry:29 %1 = zext i64 %0 to i12830 %2 = shl i128 %1, 6431 %3 = or i128 %1, %232 %4 = call i128 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i128 %3)33 %5 = trunc i128 %4 to i6434 %6 = lshr i128 %4, 6435 %7 = trunc i128 %6 to i6436 %8 = or i64 %5, %737 ret i64 %838}39 40define i128 @test_R_wide_scalar_inout(ptr %0, i128 noundef %1) nounwind {41; CHECK-LABEL: test_R_wide_scalar_inout:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: addi sp, sp, -3244; CHECK-NEXT: mv a3, a245; CHECK-NEXT: sd a0, 24(sp)46; CHECK-NEXT: mv a2, a147; CHECK-NEXT: sd a1, 0(sp)48; CHECK-NEXT: sd a3, 8(sp)49; CHECK-NEXT: #APP50; CHECK-NEXT: # a0; a251; CHECK-NEXT: #NO_APP52; CHECK-NEXT: sd a0, 24(sp)53; CHECK-NEXT: sd a2, 0(sp)54; CHECK-NEXT: sd a3, 8(sp)55; CHECK-NEXT: mv a0, a256; CHECK-NEXT: mv a1, a357; CHECK-NEXT: addi sp, sp, 3258; CHECK-NEXT: ret59entry:60 %2 = alloca ptr, align 861 %3 = alloca i128, align 1662 store ptr %0, ptr %2, align 863 store i128 %1, ptr %3, align 1664 %4 = load ptr, ptr %2, align 865 %5 = load i128, ptr %3, align 1666 %6 = call { ptr, i128 } asm sideeffect "/* $0; $1 */", "=r,=R,0,1"(ptr %4, i128 %5)67 %7 = extractvalue { ptr, i128} %6, 068 %8 = extractvalue { ptr, i128 } %6, 169 store ptr %7, ptr %2, align 870 store i128 %8, ptr %3, align 1671 %9 = load i128, ptr %3, align 1672 ret i128 %973}74 75define i128 @test_cR_wide_scalar_simple(i128 noundef %0) nounwind {76; CHECK-LABEL: test_cR_wide_scalar_simple:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: #APP79; CHECK-NEXT: # a2 <- a080; CHECK-NEXT: #NO_APP81; CHECK-NEXT: mv a0, a282; CHECK-NEXT: mv a1, a383; CHECK-NEXT: ret84entry:85 %1 = call i128 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i128 %0)86 ret i128 %187}88 89define i64 @test_cR_wide_scalar_with_ops(i64 noundef %0) nounwind {90; CHECK-LABEL: test_cR_wide_scalar_with_ops:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: mv a1, a093; CHECK-NEXT: #APP94; CHECK-NEXT: # a2 <- a095; CHECK-NEXT: #NO_APP96; CHECK-NEXT: or a0, a2, a397; CHECK-NEXT: ret98entry:99 %1 = zext i64 %0 to i128100 %2 = shl i128 %1, 64101 %3 = or i128 %1, %2102 %4 = call i128 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i128 %3)103 %5 = trunc i128 %4 to i64104 %6 = lshr i128 %4, 64105 %7 = trunc i128 %6 to i64106 %8 = or i64 %5, %7107 ret i64 %8108}109 110define i128 @test_cR_wide_scalar_inout(ptr %0, i128 noundef %1) nounwind {111; CHECK-LABEL: test_cR_wide_scalar_inout:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: addi sp, sp, -32114; CHECK-NEXT: mv a3, a2115; CHECK-NEXT: sd a0, 24(sp)116; CHECK-NEXT: mv a2, a1117; CHECK-NEXT: sd a1, 0(sp)118; CHECK-NEXT: sd a3, 8(sp)119; CHECK-NEXT: #APP120; CHECK-NEXT: # a0; a2121; CHECK-NEXT: #NO_APP122; CHECK-NEXT: sd a0, 24(sp)123; CHECK-NEXT: sd a2, 0(sp)124; CHECK-NEXT: sd a3, 8(sp)125; CHECK-NEXT: mv a0, a2126; CHECK-NEXT: mv a1, a3127; CHECK-NEXT: addi sp, sp, 32128; CHECK-NEXT: ret129entry:130 %2 = alloca ptr, align 8131 %3 = alloca i128, align 16132 store ptr %0, ptr %2, align 8133 store i128 %1, ptr %3, align 16134 %4 = load ptr, ptr %2, align 8135 %5 = load i128, ptr %3, align 16136 %6 = call { ptr, i128 } asm sideeffect "/* $0; $1 */", "=r,=^cR,0,1"(ptr %4, i128 %5)137 %7 = extractvalue { ptr, i128} %6, 0138 %8 = extractvalue { ptr, i128 } %6, 1139 store ptr %7, ptr %2, align 8140 store i128 %8, ptr %3, align 16141 %9 = load i128, ptr %3, align 16142 ret i128 %9143}144