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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s3 4; This test has multiple opportunities for SimplifyDemandedBits after type5; legalization. There are 2 opportunities on the chain feeding the LHS of the6; shl. And one opportunity on the shift amount. We previously weren't managing7; the DAGCombiner worklist correctly and failed to get the RHS.8define i32 @foo(i32 %x, i32 %y, i32 %z) {9; CHECK-LABEL: foo:10; CHECK: # %bb.0:11; CHECK-NEXT: mul a0, a0, a012; CHECK-NEXT: addi a0, a0, 113; CHECK-NEXT: mul a0, a0, a014; CHECK-NEXT: add a0, a0, a215; CHECK-NEXT: addi a0, a0, 116; CHECK-NEXT: sllw a0, a0, a117; CHECK-NEXT: ret18 %b = mul i32 %x, %x19 %c = add i32 %b, 120 %d = mul i32 %c, %c21 %e = add i32 %d, %z22 %f = add i32 %e, 123 %g = shl i32 %f, %y24 ret i32 %g25}26 27; The sign bit of an nsw self multiply is 0. Make sure we can use this to28; convert the AND constant to -8.29define i64 @mul_self_nsw_sign(i64 %x) {30; CHECK-LABEL: mul_self_nsw_sign:31; CHECK: # %bb.0:32; CHECK-NEXT: mul a0, a0, a033; CHECK-NEXT: andi a0, a0, -834; CHECK-NEXT: ret35 %a = mul nsw i64 %x, %x36 %b = and i64 %a, 922337203685477580037 ret i64 %b38}39 40; Make sure we sign extend the constant after type legalization to allow the41; use of ori.42define void @ori(ptr nocapture noundef %0) {43; CHECK-LABEL: ori:44; CHECK: # %bb.0:45; CHECK-NEXT: lw a1, 0(a0)46; CHECK-NEXT: ori a1, a1, -247; CHECK-NEXT: sw a1, 0(a0)48; CHECK-NEXT: ret49 %2 = load i32, ptr %0, align 450 %3 = or i32 %2, -251 store i32 %3, ptr %0, align 452 ret void53}54 55; Make sure we sign extend the constant after type legalization to allow the56; use of xori.57define void @xori(ptr nocapture noundef %0) {58; CHECK-LABEL: xori:59; CHECK: # %bb.0:60; CHECK-NEXT: lw a1, 0(a0)61; CHECK-NEXT: xori a1, a1, -562; CHECK-NEXT: sw a1, 0(a0)63; CHECK-NEXT: ret64 %2 = load i32, ptr %0, align 465 %3 = xor i32 %2, -566 store i32 %3, ptr %0, align 467 ret void68}69 70; Make sure we sign extend the constant after type legalization to allow the71; shorter constant materialization.72define void @or_signbit(ptr nocapture noundef %0) {73; CHECK-LABEL: or_signbit:74; CHECK: # %bb.0:75; CHECK-NEXT: lw a1, 0(a0)76; CHECK-NEXT: lui a2, 52428877; CHECK-NEXT: or a1, a1, a278; CHECK-NEXT: sw a1, 0(a0)79; CHECK-NEXT: ret80 %2 = load i32, ptr %0, align 481 %3 = or i32 %2, -214748364882 store i32 %3, ptr %0, align 483 ret void84}85 86; Make sure we sign extend the constant after type legalization to allow the87; shorter constant materialization.88define void @xor_signbit(ptr nocapture noundef %0) {89; CHECK-LABEL: xor_signbit:90; CHECK: # %bb.0:91; CHECK-NEXT: lw a1, 0(a0)92; CHECK-NEXT: lui a2, 52428893; CHECK-NEXT: xor a1, a1, a294; CHECK-NEXT: sw a1, 0(a0)95; CHECK-NEXT: ret96 %2 = load i32, ptr %0, align 497 %3 = xor i32 %2, -214748364898 store i32 %3, ptr %0, align 499 ret void100}101 102; Type legalization inserts a sext_inreg after the sub. This causes the103; constant for the AND to be turned into 0xfffffff8. Then SimplifyDemandedBits104; removes the sext_inreg from the path to the store. This prevents105; TargetShrinkDemandedConstant from being able to restore the lost upper bits106; from the and mask to allow andi. ISel is able to recover the lost sext_inreg107; using hasAllWUsers. We also use hasAllWUsers to recover the ANDI.108define signext i32 @andi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {109; CHECK-LABEL: andi_sub_cse:110; CHECK: # %bb.0:111; CHECK-NEXT: andi a0, a0, -8112; CHECK-NEXT: subw a0, a0, a1113; CHECK-NEXT: sw a0, 0(a2)114; CHECK-NEXT: ret115 %4 = and i32 %0, -8116 %5 = sub i32 %4, %1117 store i32 %5, ptr %2, align 4118 ret i32 %5119}120 121define signext i32 @addi_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {122; CHECK-LABEL: addi_sub_cse:123; CHECK: # %bb.0:124; CHECK-NEXT: sub a0, a0, a1125; CHECK-NEXT: addiw a0, a0, -8126; CHECK-NEXT: sw a0, 0(a2)127; CHECK-NEXT: ret128 %4 = add i32 %0, -8129 %5 = sub i32 %4, %1130 store i32 %5, ptr %2, align 4131 ret i32 %5132}133 134define signext i32 @xori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {135; CHECK-LABEL: xori_sub_cse:136; CHECK: # %bb.0:137; CHECK-NEXT: xori a0, a0, -8138; CHECK-NEXT: subw a0, a0, a1139; CHECK-NEXT: sw a0, 0(a2)140; CHECK-NEXT: ret141 %4 = xor i32 %0, -8142 %5 = sub i32 %4, %1143 store i32 %5, ptr %2, align 4144 ret i32 %5145}146 147define signext i32 @ori_sub_cse(i32 signext %0, i32 signext %1, ptr %2) {148; CHECK-LABEL: ori_sub_cse:149; CHECK: # %bb.0:150; CHECK-NEXT: ori a0, a0, -8151; CHECK-NEXT: subw a0, a0, a1152; CHECK-NEXT: sw a0, 0(a2)153; CHECK-NEXT: ret154 %4 = or i32 %0, -8155 %5 = sub i32 %4, %1156 store i32 %5, ptr %2, align 4157 ret i32 %5158}159 160; SimplifyDemandedBits breaks the ANDI by turning -8 into 0xfffffff8. This161; gets CSEd with the AND needed for type legalizing the lshr. This increases162; the use count of the AND with 0xfffffff8 making TargetShrinkDemandedConstant163; unable to restore it to 0xffffffff for the lshr and -8 for the AND to use164; ANDI.165; Instead we rely on ISel to form srliw even though the AND has multiple uses166; and the mask has missing 1s where bits will be shifted out. This reduces the167; use count of the AND and we can use hasAllWUsers to form ANDI.168define signext i32 @andi_srliw(i32 signext %0, ptr %1, i32 signext %2) {169; CHECK-LABEL: andi_srliw:170; CHECK: # %bb.0:171; CHECK-NEXT: andi a3, a0, -8172; CHECK-NEXT: srliw a4, a0, 3173; CHECK-NEXT: addw a0, a3, a2174; CHECK-NEXT: sw a4, 0(a1)175; CHECK-NEXT: ret176 %4 = and i32 %0, -8177 %5 = lshr i32 %0, 3178 store i32 %5, ptr %1, align 4179 %6 = add i32 %4, %2180 ret i32 %6181}182 183define i32 @and_or(i32 signext %x) {184; CHECK-LABEL: and_or:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: ori a0, a0, 255187; CHECK-NEXT: slli a0, a0, 48188; CHECK-NEXT: srli a0, a0, 48189; CHECK-NEXT: ret190entry:191 %and = and i32 %x, 65280192 %or = or i32 %and, 255193 ret i32 %or194}195 196define i64 @and_allones(i32 signext %x) {197; CHECK-LABEL: and_allones:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: addi a0, a0, -1200; CHECK-NEXT: li a1, 1201; CHECK-NEXT: sll a0, a1, a0202; CHECK-NEXT: ret203entry:204 %y = zext i32 %x to i64205 %shamt = add nsw i64 %y, -1206 %ret = shl i64 1, %shamt207 ret i64 %ret208}209