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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV64,RV64I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+zba < %s \5; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBA6 7; The patterns for the 'W' suffixed RV64I instructions have the potential of8; missing cases. This file checks all the variants of9; sign-extended/zero-extended/any-extended inputs and outputs.10 11; The 64-bit add instruction can safely be used when the result is anyext.12 13define i32 @aext_addw_aext_aext(i32 %a, i32 %b) nounwind {14; RV64-LABEL: aext_addw_aext_aext:15; RV64: # %bb.0:16; RV64-NEXT: addw a0, a0, a117; RV64-NEXT: ret18 %1 = add i32 %a, %b19 ret i32 %120}21 22define i32 @aext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {23; RV64-LABEL: aext_addw_aext_sext:24; RV64: # %bb.0:25; RV64-NEXT: addw a0, a0, a126; RV64-NEXT: ret27 %1 = add i32 %a, %b28 ret i32 %129}30 31define i32 @aext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {32; RV64-LABEL: aext_addw_aext_zext:33; RV64: # %bb.0:34; RV64-NEXT: addw a0, a0, a135; RV64-NEXT: ret36 %1 = add i32 %a, %b37 ret i32 %138}39 40define i32 @aext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {41; RV64-LABEL: aext_addw_sext_aext:42; RV64: # %bb.0:43; RV64-NEXT: addw a0, a0, a144; RV64-NEXT: ret45 %1 = add i32 %a, %b46 ret i32 %147}48 49define i32 @aext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {50; RV64-LABEL: aext_addw_sext_sext:51; RV64: # %bb.0:52; RV64-NEXT: addw a0, a0, a153; RV64-NEXT: ret54 %1 = add i32 %a, %b55 ret i32 %156}57 58define i32 @aext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {59; RV64-LABEL: aext_addw_sext_zext:60; RV64: # %bb.0:61; RV64-NEXT: addw a0, a0, a162; RV64-NEXT: ret63 %1 = add i32 %a, %b64 ret i32 %165}66 67define i32 @aext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {68; RV64-LABEL: aext_addw_zext_aext:69; RV64: # %bb.0:70; RV64-NEXT: addw a0, a0, a171; RV64-NEXT: ret72 %1 = add i32 %a, %b73 ret i32 %174}75 76define i32 @aext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {77; RV64-LABEL: aext_addw_zext_sext:78; RV64: # %bb.0:79; RV64-NEXT: addw a0, a0, a180; RV64-NEXT: ret81 %1 = add i32 %a, %b82 ret i32 %183}84 85define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {86; RV64-LABEL: aext_addw_zext_zext:87; RV64: # %bb.0:88; RV64-NEXT: addw a0, a0, a189; RV64-NEXT: ret90 %1 = add i32 %a, %b91 ret i32 %192}93 94; Always select addw when a signext result is required.95 96define signext i32 @sext_addw_aext_aext(i32 %a, i32 %b) nounwind {97; RV64-LABEL: sext_addw_aext_aext:98; RV64: # %bb.0:99; RV64-NEXT: addw a0, a0, a1100; RV64-NEXT: ret101 %1 = add i32 %a, %b102 ret i32 %1103}104 105define signext i32 @sext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {106; RV64-LABEL: sext_addw_aext_sext:107; RV64: # %bb.0:108; RV64-NEXT: addw a0, a0, a1109; RV64-NEXT: ret110 %1 = add i32 %a, %b111 ret i32 %1112}113 114define signext i32 @sext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {115; RV64-LABEL: sext_addw_aext_zext:116; RV64: # %bb.0:117; RV64-NEXT: addw a0, a0, a1118; RV64-NEXT: ret119 %1 = add i32 %a, %b120 ret i32 %1121}122 123define signext i32 @sext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {124; RV64-LABEL: sext_addw_sext_aext:125; RV64: # %bb.0:126; RV64-NEXT: addw a0, a0, a1127; RV64-NEXT: ret128 %1 = add i32 %a, %b129 ret i32 %1130}131 132define signext i32 @sext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {133; RV64-LABEL: sext_addw_sext_sext:134; RV64: # %bb.0:135; RV64-NEXT: addw a0, a0, a1136; RV64-NEXT: ret137 %1 = add i32 %a, %b138 ret i32 %1139}140 141define signext i32 @sext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {142; RV64-LABEL: sext_addw_sext_zext:143; RV64: # %bb.0:144; RV64-NEXT: addw a0, a0, a1145; RV64-NEXT: ret146 %1 = add i32 %a, %b147 ret i32 %1148}149 150define signext i32 @sext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {151; RV64-LABEL: sext_addw_zext_aext:152; RV64: # %bb.0:153; RV64-NEXT: addw a0, a0, a1154; RV64-NEXT: ret155 %1 = add i32 %a, %b156 ret i32 %1157}158 159define signext i32 @sext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {160; RV64-LABEL: sext_addw_zext_sext:161; RV64: # %bb.0:162; RV64-NEXT: addw a0, a0, a1163; RV64-NEXT: ret164 %1 = add i32 %a, %b165 ret i32 %1166}167 168define signext i32 @sext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {169; RV64-LABEL: sext_addw_zext_zext:170; RV64: # %bb.0:171; RV64-NEXT: addw a0, a0, a1172; RV64-NEXT: ret173 %1 = add i32 %a, %b174 ret i32 %1175}176 177; 64-bit add followed by zero-extension is a safe option when a zeroext result178; is required.179 180define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {181; RV64I-LABEL: zext_addw_aext_aext:182; RV64I: # %bb.0:183; RV64I-NEXT: add a0, a0, a1184; RV64I-NEXT: slli a0, a0, 32185; RV64I-NEXT: srli a0, a0, 32186; RV64I-NEXT: ret187;188; RV64ZBA-LABEL: zext_addw_aext_aext:189; RV64ZBA: # %bb.0:190; RV64ZBA-NEXT: add a0, a0, a1191; RV64ZBA-NEXT: zext.w a0, a0192; RV64ZBA-NEXT: ret193 %1 = add i32 %a, %b194 ret i32 %1195}196 197define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {198; RV64I-LABEL: zext_addw_aext_sext:199; RV64I: # %bb.0:200; RV64I-NEXT: add a0, a0, a1201; RV64I-NEXT: slli a0, a0, 32202; RV64I-NEXT: srli a0, a0, 32203; RV64I-NEXT: ret204;205; RV64ZBA-LABEL: zext_addw_aext_sext:206; RV64ZBA: # %bb.0:207; RV64ZBA-NEXT: add a0, a0, a1208; RV64ZBA-NEXT: zext.w a0, a0209; RV64ZBA-NEXT: ret210 %1 = add i32 %a, %b211 ret i32 %1212}213 214define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {215; RV64I-LABEL: zext_addw_aext_zext:216; RV64I: # %bb.0:217; RV64I-NEXT: add a0, a0, a1218; RV64I-NEXT: slli a0, a0, 32219; RV64I-NEXT: srli a0, a0, 32220; RV64I-NEXT: ret221;222; RV64ZBA-LABEL: zext_addw_aext_zext:223; RV64ZBA: # %bb.0:224; RV64ZBA-NEXT: add a0, a0, a1225; RV64ZBA-NEXT: zext.w a0, a0226; RV64ZBA-NEXT: ret227 %1 = add i32 %a, %b228 ret i32 %1229}230 231define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {232; RV64I-LABEL: zext_addw_sext_aext:233; RV64I: # %bb.0:234; RV64I-NEXT: add a0, a0, a1235; RV64I-NEXT: slli a0, a0, 32236; RV64I-NEXT: srli a0, a0, 32237; RV64I-NEXT: ret238;239; RV64ZBA-LABEL: zext_addw_sext_aext:240; RV64ZBA: # %bb.0:241; RV64ZBA-NEXT: add a0, a0, a1242; RV64ZBA-NEXT: zext.w a0, a0243; RV64ZBA-NEXT: ret244 %1 = add i32 %a, %b245 ret i32 %1246}247 248define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {249; RV64I-LABEL: zext_addw_sext_sext:250; RV64I: # %bb.0:251; RV64I-NEXT: add a0, a0, a1252; RV64I-NEXT: slli a0, a0, 32253; RV64I-NEXT: srli a0, a0, 32254; RV64I-NEXT: ret255;256; RV64ZBA-LABEL: zext_addw_sext_sext:257; RV64ZBA: # %bb.0:258; RV64ZBA-NEXT: add a0, a0, a1259; RV64ZBA-NEXT: zext.w a0, a0260; RV64ZBA-NEXT: ret261 %1 = add i32 %a, %b262 ret i32 %1263}264 265define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {266; RV64I-LABEL: zext_addw_sext_zext:267; RV64I: # %bb.0:268; RV64I-NEXT: add a0, a0, a1269; RV64I-NEXT: slli a0, a0, 32270; RV64I-NEXT: srli a0, a0, 32271; RV64I-NEXT: ret272;273; RV64ZBA-LABEL: zext_addw_sext_zext:274; RV64ZBA: # %bb.0:275; RV64ZBA-NEXT: add a0, a0, a1276; RV64ZBA-NEXT: zext.w a0, a0277; RV64ZBA-NEXT: ret278 %1 = add i32 %a, %b279 ret i32 %1280}281 282define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {283; RV64I-LABEL: zext_addw_zext_aext:284; RV64I: # %bb.0:285; RV64I-NEXT: add a0, a0, a1286; RV64I-NEXT: slli a0, a0, 32287; RV64I-NEXT: srli a0, a0, 32288; RV64I-NEXT: ret289;290; RV64ZBA-LABEL: zext_addw_zext_aext:291; RV64ZBA: # %bb.0:292; RV64ZBA-NEXT: add a0, a0, a1293; RV64ZBA-NEXT: zext.w a0, a0294; RV64ZBA-NEXT: ret295 %1 = add i32 %a, %b296 ret i32 %1297}298 299define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {300; RV64I-LABEL: zext_addw_zext_sext:301; RV64I: # %bb.0:302; RV64I-NEXT: add a0, a0, a1303; RV64I-NEXT: slli a0, a0, 32304; RV64I-NEXT: srli a0, a0, 32305; RV64I-NEXT: ret306;307; RV64ZBA-LABEL: zext_addw_zext_sext:308; RV64ZBA: # %bb.0:309; RV64ZBA-NEXT: add a0, a0, a1310; RV64ZBA-NEXT: zext.w a0, a0311; RV64ZBA-NEXT: ret312 %1 = add i32 %a, %b313 ret i32 %1314}315 316define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {317; RV64I-LABEL: zext_addw_zext_zext:318; RV64I: # %bb.0:319; RV64I-NEXT: add a0, a0, a1320; RV64I-NEXT: slli a0, a0, 32321; RV64I-NEXT: srli a0, a0, 32322; RV64I-NEXT: ret323;324; RV64ZBA-LABEL: zext_addw_zext_zext:325; RV64ZBA: # %bb.0:326; RV64ZBA-NEXT: add a0, a0, a1327; RV64ZBA-NEXT: zext.w a0, a0328; RV64ZBA-NEXT: ret329 %1 = add i32 %a, %b330 ret i32 %1331}332 333; 64-bit sub is safe for an anyext result.334 335define i32 @aext_subw_aext_aext(i32 %a, i32 %b) nounwind {336; RV64-LABEL: aext_subw_aext_aext:337; RV64: # %bb.0:338; RV64-NEXT: subw a0, a0, a1339; RV64-NEXT: ret340 %1 = sub i32 %a, %b341 ret i32 %1342}343 344define i32 @aext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {345; RV64-LABEL: aext_subw_aext_sext:346; RV64: # %bb.0:347; RV64-NEXT: subw a0, a0, a1348; RV64-NEXT: ret349 %1 = sub i32 %a, %b350 ret i32 %1351}352 353define i32 @aext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {354; RV64-LABEL: aext_subw_aext_zext:355; RV64: # %bb.0:356; RV64-NEXT: subw a0, a0, a1357; RV64-NEXT: ret358 %1 = sub i32 %a, %b359 ret i32 %1360}361 362define i32 @aext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {363; RV64-LABEL: aext_subw_sext_aext:364; RV64: # %bb.0:365; RV64-NEXT: subw a0, a0, a1366; RV64-NEXT: ret367 %1 = sub i32 %a, %b368 ret i32 %1369}370 371define i32 @aext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {372; RV64-LABEL: aext_subw_sext_sext:373; RV64: # %bb.0:374; RV64-NEXT: subw a0, a0, a1375; RV64-NEXT: ret376 %1 = sub i32 %a, %b377 ret i32 %1378}379 380define i32 @aext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {381; RV64-LABEL: aext_subw_sext_zext:382; RV64: # %bb.0:383; RV64-NEXT: subw a0, a0, a1384; RV64-NEXT: ret385 %1 = sub i32 %a, %b386 ret i32 %1387}388 389define i32 @aext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {390; RV64-LABEL: aext_subw_zext_aext:391; RV64: # %bb.0:392; RV64-NEXT: subw a0, a0, a1393; RV64-NEXT: ret394 %1 = sub i32 %a, %b395 ret i32 %1396}397 398define i32 @aext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {399; RV64-LABEL: aext_subw_zext_sext:400; RV64: # %bb.0:401; RV64-NEXT: subw a0, a0, a1402; RV64-NEXT: ret403 %1 = sub i32 %a, %b404 ret i32 %1405}406 407define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {408; RV64-LABEL: aext_subw_zext_zext:409; RV64: # %bb.0:410; RV64-NEXT: subw a0, a0, a1411; RV64-NEXT: ret412 %1 = sub i32 %a, %b413 ret i32 %1414}415 416; Always select subw for a signext result.417 418define signext i32 @sext_subw_aext_aext(i32 %a, i32 %b) nounwind {419; RV64-LABEL: sext_subw_aext_aext:420; RV64: # %bb.0:421; RV64-NEXT: subw a0, a0, a1422; RV64-NEXT: ret423 %1 = sub i32 %a, %b424 ret i32 %1425}426 427define signext i32 @sext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {428; RV64-LABEL: sext_subw_aext_sext:429; RV64: # %bb.0:430; RV64-NEXT: subw a0, a0, a1431; RV64-NEXT: ret432 %1 = sub i32 %a, %b433 ret i32 %1434}435 436define signext i32 @sext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {437; RV64-LABEL: sext_subw_aext_zext:438; RV64: # %bb.0:439; RV64-NEXT: subw a0, a0, a1440; RV64-NEXT: ret441 %1 = sub i32 %a, %b442 ret i32 %1443}444 445define signext i32 @sext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {446; RV64-LABEL: sext_subw_sext_aext:447; RV64: # %bb.0:448; RV64-NEXT: subw a0, a0, a1449; RV64-NEXT: ret450 %1 = sub i32 %a, %b451 ret i32 %1452}453 454define signext i32 @sext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {455; RV64-LABEL: sext_subw_sext_sext:456; RV64: # %bb.0:457; RV64-NEXT: subw a0, a0, a1458; RV64-NEXT: ret459 %1 = sub i32 %a, %b460 ret i32 %1461}462 463define signext i32 @sext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {464; RV64-LABEL: sext_subw_sext_zext:465; RV64: # %bb.0:466; RV64-NEXT: subw a0, a0, a1467; RV64-NEXT: ret468 %1 = sub i32 %a, %b469 ret i32 %1470}471 472define signext i32 @sext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {473; RV64-LABEL: sext_subw_zext_aext:474; RV64: # %bb.0:475; RV64-NEXT: subw a0, a0, a1476; RV64-NEXT: ret477 %1 = sub i32 %a, %b478 ret i32 %1479}480 481define signext i32 @sext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {482; RV64-LABEL: sext_subw_zext_sext:483; RV64: # %bb.0:484; RV64-NEXT: subw a0, a0, a1485; RV64-NEXT: ret486 %1 = sub i32 %a, %b487 ret i32 %1488}489 490define signext i32 @sext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {491; RV64-LABEL: sext_subw_zext_zext:492; RV64: # %bb.0:493; RV64-NEXT: subw a0, a0, a1494; RV64-NEXT: ret495 %1 = sub i32 %a, %b496 ret i32 %1497}498 499; 64-bit sub followed by zero-extension is safe for a zeroext result.500 501define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {502; RV64I-LABEL: zext_subw_aext_aext:503; RV64I: # %bb.0:504; RV64I-NEXT: sub a0, a0, a1505; RV64I-NEXT: slli a0, a0, 32506; RV64I-NEXT: srli a0, a0, 32507; RV64I-NEXT: ret508;509; RV64ZBA-LABEL: zext_subw_aext_aext:510; RV64ZBA: # %bb.0:511; RV64ZBA-NEXT: sub a0, a0, a1512; RV64ZBA-NEXT: zext.w a0, a0513; RV64ZBA-NEXT: ret514 %1 = sub i32 %a, %b515 ret i32 %1516}517 518define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {519; RV64I-LABEL: zext_subw_aext_sext:520; RV64I: # %bb.0:521; RV64I-NEXT: sub a0, a0, a1522; RV64I-NEXT: slli a0, a0, 32523; RV64I-NEXT: srli a0, a0, 32524; RV64I-NEXT: ret525;526; RV64ZBA-LABEL: zext_subw_aext_sext:527; RV64ZBA: # %bb.0:528; RV64ZBA-NEXT: sub a0, a0, a1529; RV64ZBA-NEXT: zext.w a0, a0530; RV64ZBA-NEXT: ret531 %1 = sub i32 %a, %b532 ret i32 %1533}534 535define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {536; RV64I-LABEL: zext_subw_aext_zext:537; RV64I: # %bb.0:538; RV64I-NEXT: sub a0, a0, a1539; RV64I-NEXT: slli a0, a0, 32540; RV64I-NEXT: srli a0, a0, 32541; RV64I-NEXT: ret542;543; RV64ZBA-LABEL: zext_subw_aext_zext:544; RV64ZBA: # %bb.0:545; RV64ZBA-NEXT: sub a0, a0, a1546; RV64ZBA-NEXT: zext.w a0, a0547; RV64ZBA-NEXT: ret548 %1 = sub i32 %a, %b549 ret i32 %1550}551 552define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {553; RV64I-LABEL: zext_subw_sext_aext:554; RV64I: # %bb.0:555; RV64I-NEXT: sub a0, a0, a1556; RV64I-NEXT: slli a0, a0, 32557; RV64I-NEXT: srli a0, a0, 32558; RV64I-NEXT: ret559;560; RV64ZBA-LABEL: zext_subw_sext_aext:561; RV64ZBA: # %bb.0:562; RV64ZBA-NEXT: sub a0, a0, a1563; RV64ZBA-NEXT: zext.w a0, a0564; RV64ZBA-NEXT: ret565 %1 = sub i32 %a, %b566 ret i32 %1567}568 569define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {570; RV64I-LABEL: zext_subw_sext_sext:571; RV64I: # %bb.0:572; RV64I-NEXT: sub a0, a0, a1573; RV64I-NEXT: slli a0, a0, 32574; RV64I-NEXT: srli a0, a0, 32575; RV64I-NEXT: ret576;577; RV64ZBA-LABEL: zext_subw_sext_sext:578; RV64ZBA: # %bb.0:579; RV64ZBA-NEXT: sub a0, a0, a1580; RV64ZBA-NEXT: zext.w a0, a0581; RV64ZBA-NEXT: ret582 %1 = sub i32 %a, %b583 ret i32 %1584}585 586define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {587; RV64I-LABEL: zext_subw_sext_zext:588; RV64I: # %bb.0:589; RV64I-NEXT: sub a0, a0, a1590; RV64I-NEXT: slli a0, a0, 32591; RV64I-NEXT: srli a0, a0, 32592; RV64I-NEXT: ret593;594; RV64ZBA-LABEL: zext_subw_sext_zext:595; RV64ZBA: # %bb.0:596; RV64ZBA-NEXT: sub a0, a0, a1597; RV64ZBA-NEXT: zext.w a0, a0598; RV64ZBA-NEXT: ret599 %1 = sub i32 %a, %b600 ret i32 %1601}602 603define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {604; RV64I-LABEL: zext_subw_zext_aext:605; RV64I: # %bb.0:606; RV64I-NEXT: sub a0, a0, a1607; RV64I-NEXT: slli a0, a0, 32608; RV64I-NEXT: srli a0, a0, 32609; RV64I-NEXT: ret610;611; RV64ZBA-LABEL: zext_subw_zext_aext:612; RV64ZBA: # %bb.0:613; RV64ZBA-NEXT: sub a0, a0, a1614; RV64ZBA-NEXT: zext.w a0, a0615; RV64ZBA-NEXT: ret616 %1 = sub i32 %a, %b617 ret i32 %1618}619 620define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {621; RV64I-LABEL: zext_subw_zext_sext:622; RV64I: # %bb.0:623; RV64I-NEXT: sub a0, a0, a1624; RV64I-NEXT: slli a0, a0, 32625; RV64I-NEXT: srli a0, a0, 32626; RV64I-NEXT: ret627;628; RV64ZBA-LABEL: zext_subw_zext_sext:629; RV64ZBA: # %bb.0:630; RV64ZBA-NEXT: sub a0, a0, a1631; RV64ZBA-NEXT: zext.w a0, a0632; RV64ZBA-NEXT: ret633 %1 = sub i32 %a, %b634 ret i32 %1635}636 637define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {638; RV64I-LABEL: zext_subw_zext_zext:639; RV64I: # %bb.0:640; RV64I-NEXT: sub a0, a0, a1641; RV64I-NEXT: slli a0, a0, 32642; RV64I-NEXT: srli a0, a0, 32643; RV64I-NEXT: ret644;645; RV64ZBA-LABEL: zext_subw_zext_zext:646; RV64ZBA: # %bb.0:647; RV64ZBA-NEXT: sub a0, a0, a1648; RV64ZBA-NEXT: zext.w a0, a0649; RV64ZBA-NEXT: ret650 %1 = sub i32 %a, %b651 ret i32 %1652}653 654; 64-bit sll is a safe choice for an anyext result.655 656define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {657; RV64-LABEL: aext_sllw_aext_aext:658; RV64: # %bb.0:659; RV64-NEXT: sllw a0, a0, a1660; RV64-NEXT: ret661 %1 = shl i32 %a, %b662 ret i32 %1663}664 665define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {666; RV64-LABEL: aext_sllw_aext_sext:667; RV64: # %bb.0:668; RV64-NEXT: sllw a0, a0, a1669; RV64-NEXT: ret670 %1 = shl i32 %a, %b671 ret i32 %1672}673 674define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {675; RV64-LABEL: aext_sllw_aext_zext:676; RV64: # %bb.0:677; RV64-NEXT: sllw a0, a0, a1678; RV64-NEXT: ret679 %1 = shl i32 %a, %b680 ret i32 %1681}682 683define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {684; RV64-LABEL: aext_sllw_sext_aext:685; RV64: # %bb.0:686; RV64-NEXT: sllw a0, a0, a1687; RV64-NEXT: ret688 %1 = shl i32 %a, %b689 ret i32 %1690}691 692define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {693; RV64-LABEL: aext_sllw_sext_sext:694; RV64: # %bb.0:695; RV64-NEXT: sllw a0, a0, a1696; RV64-NEXT: ret697 %1 = shl i32 %a, %b698 ret i32 %1699}700 701define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {702; RV64-LABEL: aext_sllw_sext_zext:703; RV64: # %bb.0:704; RV64-NEXT: sllw a0, a0, a1705; RV64-NEXT: ret706 %1 = shl i32 %a, %b707 ret i32 %1708}709 710define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {711; RV64-LABEL: aext_sllw_zext_aext:712; RV64: # %bb.0:713; RV64-NEXT: sllw a0, a0, a1714; RV64-NEXT: ret715 %1 = shl i32 %a, %b716 ret i32 %1717}718 719define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {720; RV64-LABEL: aext_sllw_zext_sext:721; RV64: # %bb.0:722; RV64-NEXT: sllw a0, a0, a1723; RV64-NEXT: ret724 %1 = shl i32 %a, %b725 ret i32 %1726}727 728define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {729; RV64-LABEL: aext_sllw_zext_zext:730; RV64: # %bb.0:731; RV64-NEXT: sllw a0, a0, a1732; RV64-NEXT: ret733 %1 = shl i32 %a, %b734 ret i32 %1735}736 737define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {738; RV64-LABEL: sext_sllw_aext_aext:739; RV64: # %bb.0:740; RV64-NEXT: sllw a0, a0, a1741; RV64-NEXT: ret742 %1 = shl i32 %a, %b743 ret i32 %1744}745 746define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {747; RV64-LABEL: sext_sllw_aext_sext:748; RV64: # %bb.0:749; RV64-NEXT: sllw a0, a0, a1750; RV64-NEXT: ret751 %1 = shl i32 %a, %b752 ret i32 %1753}754 755define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {756; RV64-LABEL: sext_sllw_aext_zext:757; RV64: # %bb.0:758; RV64-NEXT: sllw a0, a0, a1759; RV64-NEXT: ret760 %1 = shl i32 %a, %b761 ret i32 %1762}763 764define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {765; RV64-LABEL: sext_sllw_sext_aext:766; RV64: # %bb.0:767; RV64-NEXT: sllw a0, a0, a1768; RV64-NEXT: ret769 %1 = shl i32 %a, %b770 ret i32 %1771}772 773define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {774; RV64-LABEL: sext_sllw_sext_sext:775; RV64: # %bb.0:776; RV64-NEXT: sllw a0, a0, a1777; RV64-NEXT: ret778 %1 = shl i32 %a, %b779 ret i32 %1780}781 782define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {783; RV64-LABEL: sext_sllw_sext_zext:784; RV64: # %bb.0:785; RV64-NEXT: sllw a0, a0, a1786; RV64-NEXT: ret787 %1 = shl i32 %a, %b788 ret i32 %1789}790 791define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {792; RV64-LABEL: sext_sllw_zext_aext:793; RV64: # %bb.0:794; RV64-NEXT: sllw a0, a0, a1795; RV64-NEXT: ret796 %1 = shl i32 %a, %b797 ret i32 %1798}799 800define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {801; RV64-LABEL: sext_sllw_zext_sext:802; RV64: # %bb.0:803; RV64-NEXT: sllw a0, a0, a1804; RV64-NEXT: ret805 %1 = shl i32 %a, %b806 ret i32 %1807}808 809define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {810; RV64-LABEL: sext_sllw_zext_zext:811; RV64: # %bb.0:812; RV64-NEXT: sllw a0, a0, a1813; RV64-NEXT: ret814 %1 = shl i32 %a, %b815 ret i32 %1816}817 818; 64-bit sll followed by zero-extension for a zeroext result.819 820define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {821; RV64I-LABEL: zext_sllw_aext_aext:822; RV64I: # %bb.0:823; RV64I-NEXT: sllw a0, a0, a1824; RV64I-NEXT: slli a0, a0, 32825; RV64I-NEXT: srli a0, a0, 32826; RV64I-NEXT: ret827;828; RV64ZBA-LABEL: zext_sllw_aext_aext:829; RV64ZBA: # %bb.0:830; RV64ZBA-NEXT: sllw a0, a0, a1831; RV64ZBA-NEXT: zext.w a0, a0832; RV64ZBA-NEXT: ret833 %1 = shl i32 %a, %b834 ret i32 %1835}836 837define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {838; RV64I-LABEL: zext_sllw_aext_sext:839; RV64I: # %bb.0:840; RV64I-NEXT: sllw a0, a0, a1841; RV64I-NEXT: slli a0, a0, 32842; RV64I-NEXT: srli a0, a0, 32843; RV64I-NEXT: ret844;845; RV64ZBA-LABEL: zext_sllw_aext_sext:846; RV64ZBA: # %bb.0:847; RV64ZBA-NEXT: sllw a0, a0, a1848; RV64ZBA-NEXT: zext.w a0, a0849; RV64ZBA-NEXT: ret850 %1 = shl i32 %a, %b851 ret i32 %1852}853 854define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {855; RV64I-LABEL: zext_sllw_aext_zext:856; RV64I: # %bb.0:857; RV64I-NEXT: sllw a0, a0, a1858; RV64I-NEXT: slli a0, a0, 32859; RV64I-NEXT: srli a0, a0, 32860; RV64I-NEXT: ret861;862; RV64ZBA-LABEL: zext_sllw_aext_zext:863; RV64ZBA: # %bb.0:864; RV64ZBA-NEXT: sllw a0, a0, a1865; RV64ZBA-NEXT: zext.w a0, a0866; RV64ZBA-NEXT: ret867 %1 = shl i32 %a, %b868 ret i32 %1869}870 871define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {872; RV64I-LABEL: zext_sllw_sext_aext:873; RV64I: # %bb.0:874; RV64I-NEXT: sllw a0, a0, a1875; RV64I-NEXT: slli a0, a0, 32876; RV64I-NEXT: srli a0, a0, 32877; RV64I-NEXT: ret878;879; RV64ZBA-LABEL: zext_sllw_sext_aext:880; RV64ZBA: # %bb.0:881; RV64ZBA-NEXT: sllw a0, a0, a1882; RV64ZBA-NEXT: zext.w a0, a0883; RV64ZBA-NEXT: ret884 %1 = shl i32 %a, %b885 ret i32 %1886}887 888define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {889; RV64I-LABEL: zext_sllw_sext_sext:890; RV64I: # %bb.0:891; RV64I-NEXT: sllw a0, a0, a1892; RV64I-NEXT: slli a0, a0, 32893; RV64I-NEXT: srli a0, a0, 32894; RV64I-NEXT: ret895;896; RV64ZBA-LABEL: zext_sllw_sext_sext:897; RV64ZBA: # %bb.0:898; RV64ZBA-NEXT: sllw a0, a0, a1899; RV64ZBA-NEXT: zext.w a0, a0900; RV64ZBA-NEXT: ret901 %1 = shl i32 %a, %b902 ret i32 %1903}904 905define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {906; RV64I-LABEL: zext_sllw_sext_zext:907; RV64I: # %bb.0:908; RV64I-NEXT: sllw a0, a0, a1909; RV64I-NEXT: slli a0, a0, 32910; RV64I-NEXT: srli a0, a0, 32911; RV64I-NEXT: ret912;913; RV64ZBA-LABEL: zext_sllw_sext_zext:914; RV64ZBA: # %bb.0:915; RV64ZBA-NEXT: sllw a0, a0, a1916; RV64ZBA-NEXT: zext.w a0, a0917; RV64ZBA-NEXT: ret918 %1 = shl i32 %a, %b919 ret i32 %1920}921 922define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {923; RV64I-LABEL: zext_sllw_zext_aext:924; RV64I: # %bb.0:925; RV64I-NEXT: sllw a0, a0, a1926; RV64I-NEXT: slli a0, a0, 32927; RV64I-NEXT: srli a0, a0, 32928; RV64I-NEXT: ret929;930; RV64ZBA-LABEL: zext_sllw_zext_aext:931; RV64ZBA: # %bb.0:932; RV64ZBA-NEXT: sllw a0, a0, a1933; RV64ZBA-NEXT: zext.w a0, a0934; RV64ZBA-NEXT: ret935 %1 = shl i32 %a, %b936 ret i32 %1937}938 939define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {940; RV64I-LABEL: zext_sllw_zext_sext:941; RV64I: # %bb.0:942; RV64I-NEXT: sllw a0, a0, a1943; RV64I-NEXT: slli a0, a0, 32944; RV64I-NEXT: srli a0, a0, 32945; RV64I-NEXT: ret946;947; RV64ZBA-LABEL: zext_sllw_zext_sext:948; RV64ZBA: # %bb.0:949; RV64ZBA-NEXT: sllw a0, a0, a1950; RV64ZBA-NEXT: zext.w a0, a0951; RV64ZBA-NEXT: ret952 %1 = shl i32 %a, %b953 ret i32 %1954}955 956define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {957; RV64I-LABEL: zext_sllw_zext_zext:958; RV64I: # %bb.0:959; RV64I-NEXT: sllw a0, a0, a1960; RV64I-NEXT: slli a0, a0, 32961; RV64I-NEXT: srli a0, a0, 32962; RV64I-NEXT: ret963;964; RV64ZBA-LABEL: zext_sllw_zext_zext:965; RV64ZBA: # %bb.0:966; RV64ZBA-NEXT: sllw a0, a0, a1967; RV64ZBA-NEXT: zext.w a0, a0968; RV64ZBA-NEXT: ret969 %1 = shl i32 %a, %b970 ret i32 %1971}972 973define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {974; RV64-LABEL: aext_srlw_aext_aext:975; RV64: # %bb.0:976; RV64-NEXT: srlw a0, a0, a1977; RV64-NEXT: ret978 %1 = lshr i32 %a, %b979 ret i32 %1980}981 982define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {983; RV64-LABEL: aext_srlw_aext_sext:984; RV64: # %bb.0:985; RV64-NEXT: srlw a0, a0, a1986; RV64-NEXT: ret987 %1 = lshr i32 %a, %b988 ret i32 %1989}990 991define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {992; RV64-LABEL: aext_srlw_aext_zext:993; RV64: # %bb.0:994; RV64-NEXT: srlw a0, a0, a1995; RV64-NEXT: ret996 %1 = lshr i32 %a, %b997 ret i32 %1998}999 1000define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {1001; RV64-LABEL: aext_srlw_sext_aext:1002; RV64: # %bb.0:1003; RV64-NEXT: srlw a0, a0, a11004; RV64-NEXT: ret1005 %1 = lshr i32 %a, %b1006 ret i32 %11007}1008 1009define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1010; RV64-LABEL: aext_srlw_sext_sext:1011; RV64: # %bb.0:1012; RV64-NEXT: srlw a0, a0, a11013; RV64-NEXT: ret1014 %1 = lshr i32 %a, %b1015 ret i32 %11016}1017 1018define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1019; RV64-LABEL: aext_srlw_sext_zext:1020; RV64: # %bb.0:1021; RV64-NEXT: srlw a0, a0, a11022; RV64-NEXT: ret1023 %1 = lshr i32 %a, %b1024 ret i32 %11025}1026 1027define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1028; RV64-LABEL: aext_srlw_zext_aext:1029; RV64: # %bb.0:1030; RV64-NEXT: srlw a0, a0, a11031; RV64-NEXT: ret1032 %1 = lshr i32 %a, %b1033 ret i32 %11034}1035 1036define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1037; RV64-LABEL: aext_srlw_zext_sext:1038; RV64: # %bb.0:1039; RV64-NEXT: srlw a0, a0, a11040; RV64-NEXT: ret1041 %1 = lshr i32 %a, %b1042 ret i32 %11043}1044 1045define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1046; RV64-LABEL: aext_srlw_zext_zext:1047; RV64: # %bb.0:1048; RV64-NEXT: srlw a0, a0, a11049; RV64-NEXT: ret1050 %1 = lshr i32 %a, %b1051 ret i32 %11052}1053 1054define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {1055; RV64-LABEL: sext_srlw_aext_aext:1056; RV64: # %bb.0:1057; RV64-NEXT: srlw a0, a0, a11058; RV64-NEXT: ret1059 %1 = lshr i32 %a, %b1060 ret i32 %11061}1062 1063define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {1064; RV64-LABEL: sext_srlw_aext_sext:1065; RV64: # %bb.0:1066; RV64-NEXT: srlw a0, a0, a11067; RV64-NEXT: ret1068 %1 = lshr i32 %a, %b1069 ret i32 %11070}1071 1072define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1073; RV64-LABEL: sext_srlw_aext_zext:1074; RV64: # %bb.0:1075; RV64-NEXT: srlw a0, a0, a11076; RV64-NEXT: ret1077 %1 = lshr i32 %a, %b1078 ret i32 %11079}1080 1081define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {1082; RV64-LABEL: sext_srlw_sext_aext:1083; RV64: # %bb.0:1084; RV64-NEXT: srlw a0, a0, a11085; RV64-NEXT: ret1086 %1 = lshr i32 %a, %b1087 ret i32 %11088}1089 1090define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1091; RV64-LABEL: sext_srlw_sext_sext:1092; RV64: # %bb.0:1093; RV64-NEXT: srlw a0, a0, a11094; RV64-NEXT: ret1095 %1 = lshr i32 %a, %b1096 ret i32 %11097}1098 1099define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1100; RV64-LABEL: sext_srlw_sext_zext:1101; RV64: # %bb.0:1102; RV64-NEXT: srlw a0, a0, a11103; RV64-NEXT: ret1104 %1 = lshr i32 %a, %b1105 ret i32 %11106}1107 1108define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1109; RV64-LABEL: sext_srlw_zext_aext:1110; RV64: # %bb.0:1111; RV64-NEXT: srlw a0, a0, a11112; RV64-NEXT: ret1113 %1 = lshr i32 %a, %b1114 ret i32 %11115}1116 1117define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1118; RV64-LABEL: sext_srlw_zext_sext:1119; RV64: # %bb.0:1120; RV64-NEXT: srlw a0, a0, a11121; RV64-NEXT: ret1122 %1 = lshr i32 %a, %b1123 ret i32 %11124}1125 1126define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1127; RV64-LABEL: sext_srlw_zext_zext:1128; RV64: # %bb.0:1129; RV64-NEXT: srlw a0, a0, a11130; RV64-NEXT: ret1131 %1 = lshr i32 %a, %b1132 ret i32 %11133}1134 1135define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {1136; RV64I-LABEL: zext_srlw_aext_aext:1137; RV64I: # %bb.0:1138; RV64I-NEXT: srlw a0, a0, a11139; RV64I-NEXT: slli a0, a0, 321140; RV64I-NEXT: srli a0, a0, 321141; RV64I-NEXT: ret1142;1143; RV64ZBA-LABEL: zext_srlw_aext_aext:1144; RV64ZBA: # %bb.0:1145; RV64ZBA-NEXT: srlw a0, a0, a11146; RV64ZBA-NEXT: zext.w a0, a01147; RV64ZBA-NEXT: ret1148 %1 = lshr i32 %a, %b1149 ret i32 %11150}1151 1152define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {1153; RV64I-LABEL: zext_srlw_aext_sext:1154; RV64I: # %bb.0:1155; RV64I-NEXT: srlw a0, a0, a11156; RV64I-NEXT: slli a0, a0, 321157; RV64I-NEXT: srli a0, a0, 321158; RV64I-NEXT: ret1159;1160; RV64ZBA-LABEL: zext_srlw_aext_sext:1161; RV64ZBA: # %bb.0:1162; RV64ZBA-NEXT: srlw a0, a0, a11163; RV64ZBA-NEXT: zext.w a0, a01164; RV64ZBA-NEXT: ret1165 %1 = lshr i32 %a, %b1166 ret i32 %11167}1168 1169define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1170; RV64I-LABEL: zext_srlw_aext_zext:1171; RV64I: # %bb.0:1172; RV64I-NEXT: srlw a0, a0, a11173; RV64I-NEXT: slli a0, a0, 321174; RV64I-NEXT: srli a0, a0, 321175; RV64I-NEXT: ret1176;1177; RV64ZBA-LABEL: zext_srlw_aext_zext:1178; RV64ZBA: # %bb.0:1179; RV64ZBA-NEXT: srlw a0, a0, a11180; RV64ZBA-NEXT: zext.w a0, a01181; RV64ZBA-NEXT: ret1182 %1 = lshr i32 %a, %b1183 ret i32 %11184}1185 1186define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {1187; RV64I-LABEL: zext_srlw_sext_aext:1188; RV64I: # %bb.0:1189; RV64I-NEXT: srlw a0, a0, a11190; RV64I-NEXT: slli a0, a0, 321191; RV64I-NEXT: srli a0, a0, 321192; RV64I-NEXT: ret1193;1194; RV64ZBA-LABEL: zext_srlw_sext_aext:1195; RV64ZBA: # %bb.0:1196; RV64ZBA-NEXT: srlw a0, a0, a11197; RV64ZBA-NEXT: zext.w a0, a01198; RV64ZBA-NEXT: ret1199 %1 = lshr i32 %a, %b1200 ret i32 %11201}1202 1203define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1204; RV64I-LABEL: zext_srlw_sext_sext:1205; RV64I: # %bb.0:1206; RV64I-NEXT: srlw a0, a0, a11207; RV64I-NEXT: slli a0, a0, 321208; RV64I-NEXT: srli a0, a0, 321209; RV64I-NEXT: ret1210;1211; RV64ZBA-LABEL: zext_srlw_sext_sext:1212; RV64ZBA: # %bb.0:1213; RV64ZBA-NEXT: srlw a0, a0, a11214; RV64ZBA-NEXT: zext.w a0, a01215; RV64ZBA-NEXT: ret1216 %1 = lshr i32 %a, %b1217 ret i32 %11218}1219 1220define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1221; RV64I-LABEL: zext_srlw_sext_zext:1222; RV64I: # %bb.0:1223; RV64I-NEXT: srlw a0, a0, a11224; RV64I-NEXT: slli a0, a0, 321225; RV64I-NEXT: srli a0, a0, 321226; RV64I-NEXT: ret1227;1228; RV64ZBA-LABEL: zext_srlw_sext_zext:1229; RV64ZBA: # %bb.0:1230; RV64ZBA-NEXT: srlw a0, a0, a11231; RV64ZBA-NEXT: zext.w a0, a01232; RV64ZBA-NEXT: ret1233 %1 = lshr i32 %a, %b1234 ret i32 %11235}1236 1237define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1238; RV64I-LABEL: zext_srlw_zext_aext:1239; RV64I: # %bb.0:1240; RV64I-NEXT: srlw a0, a0, a11241; RV64I-NEXT: slli a0, a0, 321242; RV64I-NEXT: srli a0, a0, 321243; RV64I-NEXT: ret1244;1245; RV64ZBA-LABEL: zext_srlw_zext_aext:1246; RV64ZBA: # %bb.0:1247; RV64ZBA-NEXT: srlw a0, a0, a11248; RV64ZBA-NEXT: zext.w a0, a01249; RV64ZBA-NEXT: ret1250 %1 = lshr i32 %a, %b1251 ret i32 %11252}1253 1254define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1255; RV64I-LABEL: zext_srlw_zext_sext:1256; RV64I: # %bb.0:1257; RV64I-NEXT: srlw a0, a0, a11258; RV64I-NEXT: slli a0, a0, 321259; RV64I-NEXT: srli a0, a0, 321260; RV64I-NEXT: ret1261;1262; RV64ZBA-LABEL: zext_srlw_zext_sext:1263; RV64ZBA: # %bb.0:1264; RV64ZBA-NEXT: srlw a0, a0, a11265; RV64ZBA-NEXT: zext.w a0, a01266; RV64ZBA-NEXT: ret1267 %1 = lshr i32 %a, %b1268 ret i32 %11269}1270 1271define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1272; RV64I-LABEL: zext_srlw_zext_zext:1273; RV64I: # %bb.0:1274; RV64I-NEXT: srlw a0, a0, a11275; RV64I-NEXT: slli a0, a0, 321276; RV64I-NEXT: srli a0, a0, 321277; RV64I-NEXT: ret1278;1279; RV64ZBA-LABEL: zext_srlw_zext_zext:1280; RV64ZBA: # %bb.0:1281; RV64ZBA-NEXT: srlw a0, a0, a11282; RV64ZBA-NEXT: zext.w a0, a01283; RV64ZBA-NEXT: ret1284 %1 = lshr i32 %a, %b1285 ret i32 %11286}1287 1288define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {1289; RV64-LABEL: aext_sraw_aext_aext:1290; RV64: # %bb.0:1291; RV64-NEXT: sraw a0, a0, a11292; RV64-NEXT: ret1293 %1 = ashr i32 %a, %b1294 ret i32 %11295}1296 1297define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {1298; RV64-LABEL: aext_sraw_aext_sext:1299; RV64: # %bb.0:1300; RV64-NEXT: sraw a0, a0, a11301; RV64-NEXT: ret1302 %1 = ashr i32 %a, %b1303 ret i32 %11304}1305 1306define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1307; RV64-LABEL: aext_sraw_aext_zext:1308; RV64: # %bb.0:1309; RV64-NEXT: sraw a0, a0, a11310; RV64-NEXT: ret1311 %1 = ashr i32 %a, %b1312 ret i32 %11313}1314 1315define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {1316; RV64-LABEL: aext_sraw_sext_aext:1317; RV64: # %bb.0:1318; RV64-NEXT: sraw a0, a0, a11319; RV64-NEXT: ret1320 %1 = ashr i32 %a, %b1321 ret i32 %11322}1323 1324define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1325; RV64-LABEL: aext_sraw_sext_sext:1326; RV64: # %bb.0:1327; RV64-NEXT: sraw a0, a0, a11328; RV64-NEXT: ret1329 %1 = ashr i32 %a, %b1330 ret i32 %11331}1332 1333define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1334; RV64-LABEL: aext_sraw_sext_zext:1335; RV64: # %bb.0:1336; RV64-NEXT: sraw a0, a0, a11337; RV64-NEXT: ret1338 %1 = ashr i32 %a, %b1339 ret i32 %11340}1341 1342define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1343; RV64-LABEL: aext_sraw_zext_aext:1344; RV64: # %bb.0:1345; RV64-NEXT: sraw a0, a0, a11346; RV64-NEXT: ret1347 %1 = ashr i32 %a, %b1348 ret i32 %11349}1350 1351define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1352; RV64-LABEL: aext_sraw_zext_sext:1353; RV64: # %bb.0:1354; RV64-NEXT: sraw a0, a0, a11355; RV64-NEXT: ret1356 %1 = ashr i32 %a, %b1357 ret i32 %11358}1359 1360define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1361; RV64-LABEL: aext_sraw_zext_zext:1362; RV64: # %bb.0:1363; RV64-NEXT: sraw a0, a0, a11364; RV64-NEXT: ret1365 %1 = ashr i32 %a, %b1366 ret i32 %11367}1368 1369define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {1370; RV64-LABEL: sext_sraw_aext_aext:1371; RV64: # %bb.0:1372; RV64-NEXT: sraw a0, a0, a11373; RV64-NEXT: ret1374 %1 = ashr i32 %a, %b1375 ret i32 %11376}1377 1378define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {1379; RV64-LABEL: sext_sraw_aext_sext:1380; RV64: # %bb.0:1381; RV64-NEXT: sraw a0, a0, a11382; RV64-NEXT: ret1383 %1 = ashr i32 %a, %b1384 ret i32 %11385}1386 1387define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1388; RV64-LABEL: sext_sraw_aext_zext:1389; RV64: # %bb.0:1390; RV64-NEXT: sraw a0, a0, a11391; RV64-NEXT: ret1392 %1 = ashr i32 %a, %b1393 ret i32 %11394}1395 1396define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {1397; RV64-LABEL: sext_sraw_sext_aext:1398; RV64: # %bb.0:1399; RV64-NEXT: sraw a0, a0, a11400; RV64-NEXT: ret1401 %1 = ashr i32 %a, %b1402 ret i32 %11403}1404 1405define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1406; RV64-LABEL: sext_sraw_sext_sext:1407; RV64: # %bb.0:1408; RV64-NEXT: sraw a0, a0, a11409; RV64-NEXT: ret1410 %1 = ashr i32 %a, %b1411 ret i32 %11412}1413 1414define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1415; RV64-LABEL: sext_sraw_sext_zext:1416; RV64: # %bb.0:1417; RV64-NEXT: sraw a0, a0, a11418; RV64-NEXT: ret1419 %1 = ashr i32 %a, %b1420 ret i32 %11421}1422 1423define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1424; RV64-LABEL: sext_sraw_zext_aext:1425; RV64: # %bb.0:1426; RV64-NEXT: sraw a0, a0, a11427; RV64-NEXT: ret1428 %1 = ashr i32 %a, %b1429 ret i32 %11430}1431 1432define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1433; RV64-LABEL: sext_sraw_zext_sext:1434; RV64: # %bb.0:1435; RV64-NEXT: sraw a0, a0, a11436; RV64-NEXT: ret1437 %1 = ashr i32 %a, %b1438 ret i32 %11439}1440 1441define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1442; RV64-LABEL: sext_sraw_zext_zext:1443; RV64: # %bb.0:1444; RV64-NEXT: sraw a0, a0, a11445; RV64-NEXT: ret1446 %1 = ashr i32 %a, %b1447 ret i32 %11448}1449 1450define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {1451; RV64I-LABEL: zext_sraw_aext_aext:1452; RV64I: # %bb.0:1453; RV64I-NEXT: sraw a0, a0, a11454; RV64I-NEXT: slli a0, a0, 321455; RV64I-NEXT: srli a0, a0, 321456; RV64I-NEXT: ret1457;1458; RV64ZBA-LABEL: zext_sraw_aext_aext:1459; RV64ZBA: # %bb.0:1460; RV64ZBA-NEXT: sraw a0, a0, a11461; RV64ZBA-NEXT: zext.w a0, a01462; RV64ZBA-NEXT: ret1463 %1 = ashr i32 %a, %b1464 ret i32 %11465}1466 1467define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {1468; RV64I-LABEL: zext_sraw_aext_sext:1469; RV64I: # %bb.0:1470; RV64I-NEXT: sraw a0, a0, a11471; RV64I-NEXT: slli a0, a0, 321472; RV64I-NEXT: srli a0, a0, 321473; RV64I-NEXT: ret1474;1475; RV64ZBA-LABEL: zext_sraw_aext_sext:1476; RV64ZBA: # %bb.0:1477; RV64ZBA-NEXT: sraw a0, a0, a11478; RV64ZBA-NEXT: zext.w a0, a01479; RV64ZBA-NEXT: ret1480 %1 = ashr i32 %a, %b1481 ret i32 %11482}1483 1484define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1485; RV64I-LABEL: zext_sraw_aext_zext:1486; RV64I: # %bb.0:1487; RV64I-NEXT: sraw a0, a0, a11488; RV64I-NEXT: slli a0, a0, 321489; RV64I-NEXT: srli a0, a0, 321490; RV64I-NEXT: ret1491;1492; RV64ZBA-LABEL: zext_sraw_aext_zext:1493; RV64ZBA: # %bb.0:1494; RV64ZBA-NEXT: sraw a0, a0, a11495; RV64ZBA-NEXT: zext.w a0, a01496; RV64ZBA-NEXT: ret1497 %1 = ashr i32 %a, %b1498 ret i32 %11499}1500 1501define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {1502; RV64I-LABEL: zext_sraw_sext_aext:1503; RV64I: # %bb.0:1504; RV64I-NEXT: sraw a0, a0, a11505; RV64I-NEXT: slli a0, a0, 321506; RV64I-NEXT: srli a0, a0, 321507; RV64I-NEXT: ret1508;1509; RV64ZBA-LABEL: zext_sraw_sext_aext:1510; RV64ZBA: # %bb.0:1511; RV64ZBA-NEXT: sraw a0, a0, a11512; RV64ZBA-NEXT: zext.w a0, a01513; RV64ZBA-NEXT: ret1514 %1 = ashr i32 %a, %b1515 ret i32 %11516}1517 1518define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1519; RV64I-LABEL: zext_sraw_sext_sext:1520; RV64I: # %bb.0:1521; RV64I-NEXT: sraw a0, a0, a11522; RV64I-NEXT: slli a0, a0, 321523; RV64I-NEXT: srli a0, a0, 321524; RV64I-NEXT: ret1525;1526; RV64ZBA-LABEL: zext_sraw_sext_sext:1527; RV64ZBA: # %bb.0:1528; RV64ZBA-NEXT: sraw a0, a0, a11529; RV64ZBA-NEXT: zext.w a0, a01530; RV64ZBA-NEXT: ret1531 %1 = ashr i32 %a, %b1532 ret i32 %11533}1534 1535define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1536; RV64I-LABEL: zext_sraw_sext_zext:1537; RV64I: # %bb.0:1538; RV64I-NEXT: sraw a0, a0, a11539; RV64I-NEXT: slli a0, a0, 321540; RV64I-NEXT: srli a0, a0, 321541; RV64I-NEXT: ret1542;1543; RV64ZBA-LABEL: zext_sraw_sext_zext:1544; RV64ZBA: # %bb.0:1545; RV64ZBA-NEXT: sraw a0, a0, a11546; RV64ZBA-NEXT: zext.w a0, a01547; RV64ZBA-NEXT: ret1548 %1 = ashr i32 %a, %b1549 ret i32 %11550}1551 1552define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1553; RV64I-LABEL: zext_sraw_zext_aext:1554; RV64I: # %bb.0:1555; RV64I-NEXT: sraw a0, a0, a11556; RV64I-NEXT: slli a0, a0, 321557; RV64I-NEXT: srli a0, a0, 321558; RV64I-NEXT: ret1559;1560; RV64ZBA-LABEL: zext_sraw_zext_aext:1561; RV64ZBA: # %bb.0:1562; RV64ZBA-NEXT: sraw a0, a0, a11563; RV64ZBA-NEXT: zext.w a0, a01564; RV64ZBA-NEXT: ret1565 %1 = ashr i32 %a, %b1566 ret i32 %11567}1568 1569define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1570; RV64I-LABEL: zext_sraw_zext_sext:1571; RV64I: # %bb.0:1572; RV64I-NEXT: sraw a0, a0, a11573; RV64I-NEXT: slli a0, a0, 321574; RV64I-NEXT: srli a0, a0, 321575; RV64I-NEXT: ret1576;1577; RV64ZBA-LABEL: zext_sraw_zext_sext:1578; RV64ZBA: # %bb.0:1579; RV64ZBA-NEXT: sraw a0, a0, a11580; RV64ZBA-NEXT: zext.w a0, a01581; RV64ZBA-NEXT: ret1582 %1 = ashr i32 %a, %b1583 ret i32 %11584}1585 1586define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1587; RV64I-LABEL: zext_sraw_zext_zext:1588; RV64I: # %bb.0:1589; RV64I-NEXT: sraw a0, a0, a11590; RV64I-NEXT: slli a0, a0, 321591; RV64I-NEXT: srli a0, a0, 321592; RV64I-NEXT: ret1593;1594; RV64ZBA-LABEL: zext_sraw_zext_zext:1595; RV64ZBA: # %bb.0:1596; RV64ZBA-NEXT: sraw a0, a0, a11597; RV64ZBA-NEXT: zext.w a0, a01598; RV64ZBA-NEXT: ret1599 %1 = ashr i32 %a, %b1600 ret i32 %11601}1602 1603; addiw should be selected when there is a signext result.1604 1605define i32 @aext_addiw_aext(i32 %a) nounwind {1606; RV64-LABEL: aext_addiw_aext:1607; RV64: # %bb.0:1608; RV64-NEXT: addiw a0, a0, 11609; RV64-NEXT: ret1610 %1 = add i32 %a, 11611 ret i32 %11612}1613 1614define i32 @aext_addiw_sext(i32 signext %a) nounwind {1615; RV64-LABEL: aext_addiw_sext:1616; RV64: # %bb.0:1617; RV64-NEXT: addiw a0, a0, 21618; RV64-NEXT: ret1619 %1 = add i32 %a, 21620 ret i32 %11621}1622 1623define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {1624; RV64-LABEL: aext_addiw_zext:1625; RV64: # %bb.0:1626; RV64-NEXT: addiw a0, a0, 31627; RV64-NEXT: ret1628 %1 = add i32 %a, 31629 ret i32 %11630}1631 1632define signext i32 @sext_addiw_aext(i32 %a) nounwind {1633; RV64-LABEL: sext_addiw_aext:1634; RV64: # %bb.0:1635; RV64-NEXT: addiw a0, a0, 41636; RV64-NEXT: ret1637 %1 = add i32 %a, 41638 ret i32 %11639}1640 1641define signext i32 @sext_addiw_sext(i32 signext %a) nounwind {1642; RV64-LABEL: sext_addiw_sext:1643; RV64: # %bb.0:1644; RV64-NEXT: addiw a0, a0, 51645; RV64-NEXT: ret1646 %1 = add i32 %a, 51647 ret i32 %11648}1649 1650define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {1651; RV64-LABEL: sext_addiw_zext:1652; RV64: # %bb.0:1653; RV64-NEXT: addiw a0, a0, 61654; RV64-NEXT: ret1655 %1 = add i32 %a, 61656 ret i32 %11657}1658 1659define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {1660; RV64I-LABEL: zext_addiw_aext:1661; RV64I: # %bb.0:1662; RV64I-NEXT: addi a0, a0, 71663; RV64I-NEXT: slli a0, a0, 321664; RV64I-NEXT: srli a0, a0, 321665; RV64I-NEXT: ret1666;1667; RV64ZBA-LABEL: zext_addiw_aext:1668; RV64ZBA: # %bb.0:1669; RV64ZBA-NEXT: addi a0, a0, 71670; RV64ZBA-NEXT: zext.w a0, a01671; RV64ZBA-NEXT: ret1672 %1 = add i32 %a, 71673 ret i32 %11674}1675 1676define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {1677; RV64I-LABEL: zext_addiw_sext:1678; RV64I: # %bb.0:1679; RV64I-NEXT: addi a0, a0, 81680; RV64I-NEXT: slli a0, a0, 321681; RV64I-NEXT: srli a0, a0, 321682; RV64I-NEXT: ret1683;1684; RV64ZBA-LABEL: zext_addiw_sext:1685; RV64ZBA: # %bb.0:1686; RV64ZBA-NEXT: addi a0, a0, 81687; RV64ZBA-NEXT: zext.w a0, a01688; RV64ZBA-NEXT: ret1689 %1 = add i32 %a, 81690 ret i32 %11691}1692 1693define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {1694; RV64I-LABEL: zext_addiw_zext:1695; RV64I: # %bb.0:1696; RV64I-NEXT: addi a0, a0, 91697; RV64I-NEXT: slli a0, a0, 321698; RV64I-NEXT: srli a0, a0, 321699; RV64I-NEXT: ret1700;1701; RV64ZBA-LABEL: zext_addiw_zext:1702; RV64ZBA: # %bb.0:1703; RV64ZBA-NEXT: addi a0, a0, 91704; RV64ZBA-NEXT: zext.w a0, a01705; RV64ZBA-NEXT: ret1706 %1 = add i32 %a, 91707 ret i32 %11708}1709 1710; slliw should be selected whenever the return is signext.1711 1712define i32 @aext_slliw_aext(i32 %a) nounwind {1713; RV64-LABEL: aext_slliw_aext:1714; RV64: # %bb.0:1715; RV64-NEXT: slliw a0, a0, 11716; RV64-NEXT: ret1717 %1 = shl i32 %a, 11718 ret i32 %11719}1720 1721define i32 @aext_slliw_sext(i32 signext %a) nounwind {1722; RV64-LABEL: aext_slliw_sext:1723; RV64: # %bb.0:1724; RV64-NEXT: slliw a0, a0, 21725; RV64-NEXT: ret1726 %1 = shl i32 %a, 21727 ret i32 %11728}1729 1730define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {1731; RV64-LABEL: aext_slliw_zext:1732; RV64: # %bb.0:1733; RV64-NEXT: slliw a0, a0, 31734; RV64-NEXT: ret1735 %1 = shl i32 %a, 31736 ret i32 %11737}1738 1739define signext i32 @sext_slliw_aext(i32 %a) nounwind {1740; RV64-LABEL: sext_slliw_aext:1741; RV64: # %bb.0:1742; RV64-NEXT: slliw a0, a0, 41743; RV64-NEXT: ret1744 %1 = shl i32 %a, 41745 ret i32 %11746}1747 1748define signext i32 @sext_slliw_sext(i32 signext %a) nounwind {1749; RV64-LABEL: sext_slliw_sext:1750; RV64: # %bb.0:1751; RV64-NEXT: slliw a0, a0, 51752; RV64-NEXT: ret1753 %1 = shl i32 %a, 51754 ret i32 %11755}1756 1757define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {1758; RV64-LABEL: sext_slliw_zext:1759; RV64: # %bb.0:1760; RV64-NEXT: slliw a0, a0, 61761; RV64-NEXT: ret1762 %1 = shl i32 %a, 61763 ret i32 %11764}1765 1766define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {1767; RV64-LABEL: zext_slliw_aext:1768; RV64: # %bb.0:1769; RV64-NEXT: slli a0, a0, 391770; RV64-NEXT: srli a0, a0, 321771; RV64-NEXT: ret1772 %1 = shl i32 %a, 71773 ret i32 %11774}1775 1776define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {1777; RV64-LABEL: zext_slliw_sext:1778; RV64: # %bb.0:1779; RV64-NEXT: slli a0, a0, 401780; RV64-NEXT: srli a0, a0, 321781; RV64-NEXT: ret1782 %1 = shl i32 %a, 81783 ret i32 %11784}1785 1786define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {1787; RV64-LABEL: zext_slliw_zext:1788; RV64: # %bb.0:1789; RV64-NEXT: slli a0, a0, 411790; RV64-NEXT: srli a0, a0, 321791; RV64-NEXT: ret1792 %1 = shl i32 %a, 91793 ret i32 %11794}1795 1796; srliw should be selected unless the first operand is zeroext, when srli is1797; equivalent.1798 1799define i32 @aext_srliw_aext(i32 %a) nounwind {1800; RV64-LABEL: aext_srliw_aext:1801; RV64: # %bb.0:1802; RV64-NEXT: srliw a0, a0, 11803; RV64-NEXT: ret1804 %1 = lshr i32 %a, 11805 ret i32 %11806}1807 1808define i32 @aext_srliw_sext(i32 signext %a) nounwind {1809; RV64-LABEL: aext_srliw_sext:1810; RV64: # %bb.0:1811; RV64-NEXT: srliw a0, a0, 21812; RV64-NEXT: ret1813 %1 = lshr i32 %a, 21814 ret i32 %11815}1816 1817define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {1818; RV64-LABEL: aext_srliw_zext:1819; RV64: # %bb.0:1820; RV64-NEXT: srli a0, a0, 31821; RV64-NEXT: ret1822 %1 = lshr i32 %a, 31823 ret i32 %11824}1825 1826define signext i32 @sext_srliw_aext(i32 %a) nounwind {1827; RV64-LABEL: sext_srliw_aext:1828; RV64: # %bb.0:1829; RV64-NEXT: srliw a0, a0, 41830; RV64-NEXT: ret1831 %1 = lshr i32 %a, 41832 ret i32 %11833}1834 1835define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {1836; RV64-LABEL: sext_srliw_sext:1837; RV64: # %bb.0:1838; RV64-NEXT: srliw a0, a0, 51839; RV64-NEXT: ret1840 %1 = lshr i32 %a, 51841 ret i32 %11842}1843 1844define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {1845; RV64-LABEL: sext_srliw_zext:1846; RV64: # %bb.0:1847; RV64-NEXT: srli a0, a0, 61848; RV64-NEXT: ret1849 %1 = lshr i32 %a, 61850 ret i32 %11851}1852 1853define zeroext i32 @zext_srliw_aext(i32 %a) nounwind {1854; RV64-LABEL: zext_srliw_aext:1855; RV64: # %bb.0:1856; RV64-NEXT: srliw a0, a0, 71857; RV64-NEXT: ret1858 %1 = lshr i32 %a, 71859 ret i32 %11860}1861 1862define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {1863; RV64-LABEL: zext_srliw_sext:1864; RV64: # %bb.0:1865; RV64-NEXT: srliw a0, a0, 81866; RV64-NEXT: ret1867 %1 = lshr i32 %a, 81868 ret i32 %11869}1870 1871define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {1872; RV64-LABEL: zext_srliw_zext:1873; RV64: # %bb.0:1874; RV64-NEXT: srli a0, a0, 91875; RV64-NEXT: ret1876 %1 = lshr i32 %a, 91877 ret i32 %11878}1879 1880; srai is equivalent to sraiw if the first operand is sign-extended.1881 1882define i32 @aext_sraiw_aext(i32 %a) nounwind {1883; RV64-LABEL: aext_sraiw_aext:1884; RV64: # %bb.0:1885; RV64-NEXT: sraiw a0, a0, 11886; RV64-NEXT: ret1887 %1 = ashr i32 %a, 11888 ret i32 %11889}1890 1891define i32 @aext_sraiw_sext(i32 signext %a) nounwind {1892; RV64-LABEL: aext_sraiw_sext:1893; RV64: # %bb.0:1894; RV64-NEXT: srai a0, a0, 21895; RV64-NEXT: ret1896 %1 = ashr i32 %a, 21897 ret i32 %11898}1899 1900define i32 @aext_sraiw_zext(i32 zeroext %a) nounwind {1901; RV64-LABEL: aext_sraiw_zext:1902; RV64: # %bb.0:1903; RV64-NEXT: sraiw a0, a0, 31904; RV64-NEXT: ret1905 %1 = ashr i32 %a, 31906 ret i32 %11907}1908 1909define signext i32 @sext_sraiw_aext(i32 %a) nounwind {1910; RV64-LABEL: sext_sraiw_aext:1911; RV64: # %bb.0:1912; RV64-NEXT: sraiw a0, a0, 41913; RV64-NEXT: ret1914 %1 = ashr i32 %a, 41915 ret i32 %11916}1917 1918define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {1919; RV64-LABEL: sext_sraiw_sext:1920; RV64: # %bb.0:1921; RV64-NEXT: srai a0, a0, 51922; RV64-NEXT: ret1923 %1 = ashr i32 %a, 51924 ret i32 %11925}1926 1927define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {1928; RV64-LABEL: sext_sraiw_zext:1929; RV64: # %bb.0:1930; RV64-NEXT: sraiw a0, a0, 61931; RV64-NEXT: ret1932 %1 = ashr i32 %a, 61933 ret i32 %11934}1935 1936define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {1937; RV64I-LABEL: zext_sraiw_aext:1938; RV64I: # %bb.0:1939; RV64I-NEXT: sext.w a0, a01940; RV64I-NEXT: slli a0, a0, 251941; RV64I-NEXT: srli a0, a0, 321942; RV64I-NEXT: ret1943;1944; RV64ZBA-LABEL: zext_sraiw_aext:1945; RV64ZBA: # %bb.0:1946; RV64ZBA-NEXT: sraiw a0, a0, 71947; RV64ZBA-NEXT: zext.w a0, a01948; RV64ZBA-NEXT: ret1949 %1 = ashr i32 %a, 71950 ret i32 %11951}1952 1953define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {1954; RV64-LABEL: zext_sraiw_sext:1955; RV64: # %bb.0:1956; RV64-NEXT: slli a0, a0, 241957; RV64-NEXT: srli a0, a0, 321958; RV64-NEXT: ret1959 %1 = ashr i32 %a, 81960 ret i32 %11961}1962 1963define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {1964; RV64I-LABEL: zext_sraiw_zext:1965; RV64I: # %bb.0:1966; RV64I-NEXT: sext.w a0, a01967; RV64I-NEXT: slli a0, a0, 231968; RV64I-NEXT: srli a0, a0, 321969; RV64I-NEXT: ret1970;1971; RV64ZBA-LABEL: zext_sraiw_zext:1972; RV64ZBA: # %bb.0:1973; RV64ZBA-NEXT: sraiw a0, a0, 91974; RV64ZBA-NEXT: zext.w a0, a01975; RV64ZBA-NEXT: ret1976 %1 = ashr i32 %a, 91977 ret i32 %11978}1979