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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64I4 5; These tests must not compile to sllw/srlw/sraw, as this would be semantically6; incorrect in the case that %b holds a value between 32 and 63. Selection7; patterns might make the mistake of assuming that a (sext_inreg foo, i32) can8; only be produced when sign-extending an i32 type.9 10define i64 @tricky_shl(i64 %a, i64 %b) nounwind {11; RV64I-LABEL: tricky_shl:12; RV64I: # %bb.0:13; RV64I-NEXT: sll a0, a0, a114; RV64I-NEXT: sext.w a0, a015; RV64I-NEXT: ret16 %1 = shl i64 %a, %b17 %2 = shl i64 %1, 3218 %3 = ashr i64 %2, 3219 ret i64 %320}21 22define i64 @tricky_lshr(i64 %a, i64 %b) nounwind {23; RV64I-LABEL: tricky_lshr:24; RV64I: # %bb.0:25; RV64I-NEXT: slli a0, a0, 3226; RV64I-NEXT: srli a0, a0, 3227; RV64I-NEXT: srl a0, a0, a128; RV64I-NEXT: ret29 %1 = and i64 %a, 429496729530 %2 = lshr i64 %1, %b31 ret i64 %232}33 34define i64 @tricky_ashr(i64 %a, i64 %b) nounwind {35; RV64I-LABEL: tricky_ashr:36; RV64I: # %bb.0:37; RV64I-NEXT: sext.w a0, a038; RV64I-NEXT: sra a0, a0, a139; RV64I-NEXT: ret40 %1 = shl i64 %a, 3241 %2 = ashr i64 %1, 3242 %3 = ashr i64 %2, %b43 ret i64 %344}45