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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64IM4 5; The patterns for the 'W' suffixed RV64M instructions have the potential of6; missing cases. This file checks all the variants of7; sign-extended/zero-extended/any-extended inputs and outputs.8 9define i32 @aext_mulw_aext_aext(i32 %a, i32 %b) nounwind {10; RV64IM-LABEL: aext_mulw_aext_aext:11; RV64IM: # %bb.0:12; RV64IM-NEXT: mulw a0, a0, a113; RV64IM-NEXT: ret14 %1 = mul i32 %a, %b15 ret i32 %116}17 18define i32 @aext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {19; RV64IM-LABEL: aext_mulw_aext_sext:20; RV64IM: # %bb.0:21; RV64IM-NEXT: mulw a0, a0, a122; RV64IM-NEXT: ret23 %1 = mul i32 %a, %b24 ret i32 %125}26 27define i32 @aext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {28; RV64IM-LABEL: aext_mulw_aext_zext:29; RV64IM: # %bb.0:30; RV64IM-NEXT: mulw a0, a0, a131; RV64IM-NEXT: ret32 %1 = mul i32 %a, %b33 ret i32 %134}35 36define i32 @aext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {37; RV64IM-LABEL: aext_mulw_sext_aext:38; RV64IM: # %bb.0:39; RV64IM-NEXT: mulw a0, a0, a140; RV64IM-NEXT: ret41 %1 = mul i32 %a, %b42 ret i32 %143}44 45define i32 @aext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {46; RV64IM-LABEL: aext_mulw_sext_sext:47; RV64IM: # %bb.0:48; RV64IM-NEXT: mulw a0, a0, a149; RV64IM-NEXT: ret50 %1 = mul i32 %a, %b51 ret i32 %152}53 54define i32 @aext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {55; RV64IM-LABEL: aext_mulw_sext_zext:56; RV64IM: # %bb.0:57; RV64IM-NEXT: mulw a0, a0, a158; RV64IM-NEXT: ret59 %1 = mul i32 %a, %b60 ret i32 %161}62 63define i32 @aext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {64; RV64IM-LABEL: aext_mulw_zext_aext:65; RV64IM: # %bb.0:66; RV64IM-NEXT: mulw a0, a0, a167; RV64IM-NEXT: ret68 %1 = mul i32 %a, %b69 ret i32 %170}71 72define i32 @aext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {73; RV64IM-LABEL: aext_mulw_zext_sext:74; RV64IM: # %bb.0:75; RV64IM-NEXT: mulw a0, a0, a176; RV64IM-NEXT: ret77 %1 = mul i32 %a, %b78 ret i32 %179}80 81define i32 @aext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {82; RV64IM-LABEL: aext_mulw_zext_zext:83; RV64IM: # %bb.0:84; RV64IM-NEXT: mulw a0, a0, a185; RV64IM-NEXT: ret86 %1 = mul i32 %a, %b87 ret i32 %188}89 90define signext i32 @sext_mulw_aext_aext(i32 %a, i32 %b) nounwind {91; RV64IM-LABEL: sext_mulw_aext_aext:92; RV64IM: # %bb.0:93; RV64IM-NEXT: mulw a0, a0, a194; RV64IM-NEXT: ret95 %1 = mul i32 %a, %b96 ret i32 %197}98 99define signext i32 @sext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {100; RV64IM-LABEL: sext_mulw_aext_sext:101; RV64IM: # %bb.0:102; RV64IM-NEXT: mulw a0, a0, a1103; RV64IM-NEXT: ret104 %1 = mul i32 %a, %b105 ret i32 %1106}107 108define signext i32 @sext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {109; RV64IM-LABEL: sext_mulw_aext_zext:110; RV64IM: # %bb.0:111; RV64IM-NEXT: mulw a0, a0, a1112; RV64IM-NEXT: ret113 %1 = mul i32 %a, %b114 ret i32 %1115}116 117define signext i32 @sext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {118; RV64IM-LABEL: sext_mulw_sext_aext:119; RV64IM: # %bb.0:120; RV64IM-NEXT: mulw a0, a0, a1121; RV64IM-NEXT: ret122 %1 = mul i32 %a, %b123 ret i32 %1124}125 126define signext i32 @sext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {127; RV64IM-LABEL: sext_mulw_sext_sext:128; RV64IM: # %bb.0:129; RV64IM-NEXT: mulw a0, a0, a1130; RV64IM-NEXT: ret131 %1 = mul i32 %a, %b132 ret i32 %1133}134 135define signext i32 @sext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {136; RV64IM-LABEL: sext_mulw_sext_zext:137; RV64IM: # %bb.0:138; RV64IM-NEXT: mulw a0, a0, a1139; RV64IM-NEXT: ret140 %1 = mul i32 %a, %b141 ret i32 %1142}143 144define signext i32 @sext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {145; RV64IM-LABEL: sext_mulw_zext_aext:146; RV64IM: # %bb.0:147; RV64IM-NEXT: mulw a0, a0, a1148; RV64IM-NEXT: ret149 %1 = mul i32 %a, %b150 ret i32 %1151}152 153define signext i32 @sext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {154; RV64IM-LABEL: sext_mulw_zext_sext:155; RV64IM: # %bb.0:156; RV64IM-NEXT: mulw a0, a0, a1157; RV64IM-NEXT: ret158 %1 = mul i32 %a, %b159 ret i32 %1160}161 162define signext i32 @sext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {163; RV64IM-LABEL: sext_mulw_zext_zext:164; RV64IM: # %bb.0:165; RV64IM-NEXT: mulw a0, a0, a1166; RV64IM-NEXT: ret167 %1 = mul i32 %a, %b168 ret i32 %1169}170 171define zeroext i32 @zext_mulw_aext_aext(i32 %a, i32 %b) nounwind {172; RV64IM-LABEL: zext_mulw_aext_aext:173; RV64IM: # %bb.0:174; RV64IM-NEXT: mul a0, a0, a1175; RV64IM-NEXT: slli a0, a0, 32176; RV64IM-NEXT: srli a0, a0, 32177; RV64IM-NEXT: ret178 %1 = mul i32 %a, %b179 ret i32 %1180}181 182define zeroext i32 @zext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {183; RV64IM-LABEL: zext_mulw_aext_sext:184; RV64IM: # %bb.0:185; RV64IM-NEXT: mul a0, a0, a1186; RV64IM-NEXT: slli a0, a0, 32187; RV64IM-NEXT: srli a0, a0, 32188; RV64IM-NEXT: ret189 %1 = mul i32 %a, %b190 ret i32 %1191}192 193define zeroext i32 @zext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {194; RV64IM-LABEL: zext_mulw_aext_zext:195; RV64IM: # %bb.0:196; RV64IM-NEXT: mul a0, a0, a1197; RV64IM-NEXT: slli a0, a0, 32198; RV64IM-NEXT: srli a0, a0, 32199; RV64IM-NEXT: ret200 %1 = mul i32 %a, %b201 ret i32 %1202}203 204define zeroext i32 @zext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {205; RV64IM-LABEL: zext_mulw_sext_aext:206; RV64IM: # %bb.0:207; RV64IM-NEXT: mul a0, a0, a1208; RV64IM-NEXT: slli a0, a0, 32209; RV64IM-NEXT: srli a0, a0, 32210; RV64IM-NEXT: ret211 %1 = mul i32 %a, %b212 ret i32 %1213}214 215define zeroext i32 @zext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {216; RV64IM-LABEL: zext_mulw_sext_sext:217; RV64IM: # %bb.0:218; RV64IM-NEXT: mul a0, a0, a1219; RV64IM-NEXT: slli a0, a0, 32220; RV64IM-NEXT: srli a0, a0, 32221; RV64IM-NEXT: ret222 %1 = mul i32 %a, %b223 ret i32 %1224}225 226define zeroext i32 @zext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {227; RV64IM-LABEL: zext_mulw_sext_zext:228; RV64IM: # %bb.0:229; RV64IM-NEXT: mul a0, a0, a1230; RV64IM-NEXT: slli a0, a0, 32231; RV64IM-NEXT: srli a0, a0, 32232; RV64IM-NEXT: ret233 %1 = mul i32 %a, %b234 ret i32 %1235}236 237define zeroext i32 @zext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {238; RV64IM-LABEL: zext_mulw_zext_aext:239; RV64IM: # %bb.0:240; RV64IM-NEXT: mul a0, a0, a1241; RV64IM-NEXT: slli a0, a0, 32242; RV64IM-NEXT: srli a0, a0, 32243; RV64IM-NEXT: ret244 %1 = mul i32 %a, %b245 ret i32 %1246}247 248define zeroext i32 @zext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {249; RV64IM-LABEL: zext_mulw_zext_sext:250; RV64IM: # %bb.0:251; RV64IM-NEXT: mul a0, a0, a1252; RV64IM-NEXT: slli a0, a0, 32253; RV64IM-NEXT: srli a0, a0, 32254; RV64IM-NEXT: ret255 %1 = mul i32 %a, %b256 ret i32 %1257}258 259define zeroext i32 @zext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {260; RV64IM-LABEL: zext_mulw_zext_zext:261; RV64IM: # %bb.0:262; RV64IM-NEXT: mul a0, a0, a1263; RV64IM-NEXT: slli a0, a0, 32264; RV64IM-NEXT: srli a0, a0, 32265; RV64IM-NEXT: ret266 %1 = mul i32 %a, %b267 ret i32 %1268}269 270define i32 @aext_divuw_aext_aext(i32 %a, i32 %b) nounwind {271; RV64IM-LABEL: aext_divuw_aext_aext:272; RV64IM: # %bb.0:273; RV64IM-NEXT: divuw a0, a0, a1274; RV64IM-NEXT: ret275 %1 = udiv i32 %a, %b276 ret i32 %1277}278 279define i32 @aext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {280; RV64IM-LABEL: aext_divuw_aext_sext:281; RV64IM: # %bb.0:282; RV64IM-NEXT: divuw a0, a0, a1283; RV64IM-NEXT: ret284 %1 = udiv i32 %a, %b285 ret i32 %1286}287 288define i32 @aext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {289; RV64IM-LABEL: aext_divuw_aext_zext:290; RV64IM: # %bb.0:291; RV64IM-NEXT: divuw a0, a0, a1292; RV64IM-NEXT: ret293 %1 = udiv i32 %a, %b294 ret i32 %1295}296 297define i32 @aext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {298; RV64IM-LABEL: aext_divuw_sext_aext:299; RV64IM: # %bb.0:300; RV64IM-NEXT: divuw a0, a0, a1301; RV64IM-NEXT: ret302 %1 = udiv i32 %a, %b303 ret i32 %1304}305 306define i32 @aext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {307; RV64IM-LABEL: aext_divuw_sext_sext:308; RV64IM: # %bb.0:309; RV64IM-NEXT: divuw a0, a0, a1310; RV64IM-NEXT: ret311 %1 = udiv i32 %a, %b312 ret i32 %1313}314 315define i32 @aext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {316; RV64IM-LABEL: aext_divuw_sext_zext:317; RV64IM: # %bb.0:318; RV64IM-NEXT: divuw a0, a0, a1319; RV64IM-NEXT: ret320 %1 = udiv i32 %a, %b321 ret i32 %1322}323 324define i32 @aext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {325; RV64IM-LABEL: aext_divuw_zext_aext:326; RV64IM: # %bb.0:327; RV64IM-NEXT: divuw a0, a0, a1328; RV64IM-NEXT: ret329 %1 = udiv i32 %a, %b330 ret i32 %1331}332 333define i32 @aext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {334; RV64IM-LABEL: aext_divuw_zext_sext:335; RV64IM: # %bb.0:336; RV64IM-NEXT: divuw a0, a0, a1337; RV64IM-NEXT: ret338 %1 = udiv i32 %a, %b339 ret i32 %1340}341 342define i32 @aext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {343; RV64IM-LABEL: aext_divuw_zext_zext:344; RV64IM: # %bb.0:345; RV64IM-NEXT: divuw a0, a0, a1346; RV64IM-NEXT: ret347 %1 = udiv i32 %a, %b348 ret i32 %1349}350 351define signext i32 @sext_divuw_aext_aext(i32 %a, i32 %b) nounwind {352; RV64IM-LABEL: sext_divuw_aext_aext:353; RV64IM: # %bb.0:354; RV64IM-NEXT: divuw a0, a0, a1355; RV64IM-NEXT: ret356 %1 = udiv i32 %a, %b357 ret i32 %1358}359 360define signext i32 @sext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {361; RV64IM-LABEL: sext_divuw_aext_sext:362; RV64IM: # %bb.0:363; RV64IM-NEXT: divuw a0, a0, a1364; RV64IM-NEXT: ret365 %1 = udiv i32 %a, %b366 ret i32 %1367}368 369define signext i32 @sext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {370; RV64IM-LABEL: sext_divuw_aext_zext:371; RV64IM: # %bb.0:372; RV64IM-NEXT: divuw a0, a0, a1373; RV64IM-NEXT: ret374 %1 = udiv i32 %a, %b375 ret i32 %1376}377 378define signext i32 @sext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {379; RV64IM-LABEL: sext_divuw_sext_aext:380; RV64IM: # %bb.0:381; RV64IM-NEXT: divuw a0, a0, a1382; RV64IM-NEXT: ret383 %1 = udiv i32 %a, %b384 ret i32 %1385}386 387define signext i32 @sext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {388; RV64IM-LABEL: sext_divuw_sext_sext:389; RV64IM: # %bb.0:390; RV64IM-NEXT: divuw a0, a0, a1391; RV64IM-NEXT: ret392 %1 = udiv i32 %a, %b393 ret i32 %1394}395 396define signext i32 @sext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {397; RV64IM-LABEL: sext_divuw_sext_zext:398; RV64IM: # %bb.0:399; RV64IM-NEXT: divuw a0, a0, a1400; RV64IM-NEXT: ret401 %1 = udiv i32 %a, %b402 ret i32 %1403}404 405define signext i32 @sext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {406; RV64IM-LABEL: sext_divuw_zext_aext:407; RV64IM: # %bb.0:408; RV64IM-NEXT: divuw a0, a0, a1409; RV64IM-NEXT: ret410 %1 = udiv i32 %a, %b411 ret i32 %1412}413 414define signext i32 @sext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {415; RV64IM-LABEL: sext_divuw_zext_sext:416; RV64IM: # %bb.0:417; RV64IM-NEXT: divuw a0, a0, a1418; RV64IM-NEXT: ret419 %1 = udiv i32 %a, %b420 ret i32 %1421}422 423define signext i32 @sext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {424; RV64IM-LABEL: sext_divuw_zext_zext:425; RV64IM: # %bb.0:426; RV64IM-NEXT: divuw a0, a0, a1427; RV64IM-NEXT: ret428 %1 = udiv i32 %a, %b429 ret i32 %1430}431 432define zeroext i32 @zext_divuw_aext_aext(i32 %a, i32 %b) nounwind {433; RV64IM-LABEL: zext_divuw_aext_aext:434; RV64IM: # %bb.0:435; RV64IM-NEXT: divuw a0, a0, a1436; RV64IM-NEXT: slli a0, a0, 32437; RV64IM-NEXT: srli a0, a0, 32438; RV64IM-NEXT: ret439 %1 = udiv i32 %a, %b440 ret i32 %1441}442 443define zeroext i32 @zext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {444; RV64IM-LABEL: zext_divuw_aext_sext:445; RV64IM: # %bb.0:446; RV64IM-NEXT: divuw a0, a0, a1447; RV64IM-NEXT: slli a0, a0, 32448; RV64IM-NEXT: srli a0, a0, 32449; RV64IM-NEXT: ret450 %1 = udiv i32 %a, %b451 ret i32 %1452}453 454define zeroext i32 @zext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {455; RV64IM-LABEL: zext_divuw_aext_zext:456; RV64IM: # %bb.0:457; RV64IM-NEXT: divuw a0, a0, a1458; RV64IM-NEXT: slli a0, a0, 32459; RV64IM-NEXT: srli a0, a0, 32460; RV64IM-NEXT: ret461 %1 = udiv i32 %a, %b462 ret i32 %1463}464 465define zeroext i32 @zext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {466; RV64IM-LABEL: zext_divuw_sext_aext:467; RV64IM: # %bb.0:468; RV64IM-NEXT: divuw a0, a0, a1469; RV64IM-NEXT: slli a0, a0, 32470; RV64IM-NEXT: srli a0, a0, 32471; RV64IM-NEXT: ret472 %1 = udiv i32 %a, %b473 ret i32 %1474}475 476define zeroext i32 @zext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {477; RV64IM-LABEL: zext_divuw_sext_sext:478; RV64IM: # %bb.0:479; RV64IM-NEXT: divuw a0, a0, a1480; RV64IM-NEXT: slli a0, a0, 32481; RV64IM-NEXT: srli a0, a0, 32482; RV64IM-NEXT: ret483 %1 = udiv i32 %a, %b484 ret i32 %1485}486 487define zeroext i32 @zext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {488; RV64IM-LABEL: zext_divuw_sext_zext:489; RV64IM: # %bb.0:490; RV64IM-NEXT: divuw a0, a0, a1491; RV64IM-NEXT: slli a0, a0, 32492; RV64IM-NEXT: srli a0, a0, 32493; RV64IM-NEXT: ret494 %1 = udiv i32 %a, %b495 ret i32 %1496}497 498define zeroext i32 @zext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {499; RV64IM-LABEL: zext_divuw_zext_aext:500; RV64IM: # %bb.0:501; RV64IM-NEXT: divuw a0, a0, a1502; RV64IM-NEXT: slli a0, a0, 32503; RV64IM-NEXT: srli a0, a0, 32504; RV64IM-NEXT: ret505 %1 = udiv i32 %a, %b506 ret i32 %1507}508 509define zeroext i32 @zext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {510; RV64IM-LABEL: zext_divuw_zext_sext:511; RV64IM: # %bb.0:512; RV64IM-NEXT: divuw a0, a0, a1513; RV64IM-NEXT: slli a0, a0, 32514; RV64IM-NEXT: srli a0, a0, 32515; RV64IM-NEXT: ret516 %1 = udiv i32 %a, %b517 ret i32 %1518}519 520define zeroext i32 @zext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {521; RV64IM-LABEL: zext_divuw_zext_zext:522; RV64IM: # %bb.0:523; RV64IM-NEXT: divu a0, a0, a1524; RV64IM-NEXT: ret525 %1 = udiv i32 %a, %b526 ret i32 %1527}528 529define zeroext i8 @zext_divuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b) nounwind {530; RV64IM-LABEL: zext_divuw_zext_zext_i8:531; RV64IM: # %bb.0:532; RV64IM-NEXT: divuw a0, a0, a1533; RV64IM-NEXT: ret534 %1 = udiv i8 %a, %b535 ret i8 %1536}537 538define zeroext i16 @zext_divuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b) nounwind {539; RV64IM-LABEL: zext_divuw_zext_zext_i16:540; RV64IM: # %bb.0:541; RV64IM-NEXT: divuw a0, a0, a1542; RV64IM-NEXT: ret543 %1 = udiv i16 %a, %b544 ret i16 %1545}546 547define i32 @aext_divw_aext_aext(i32 %a, i32 %b) nounwind {548; RV64IM-LABEL: aext_divw_aext_aext:549; RV64IM: # %bb.0:550; RV64IM-NEXT: divw a0, a0, a1551; RV64IM-NEXT: ret552 %1 = sdiv i32 %a, %b553 ret i32 %1554}555 556define i32 @aext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {557; RV64IM-LABEL: aext_divw_aext_sext:558; RV64IM: # %bb.0:559; RV64IM-NEXT: divw a0, a0, a1560; RV64IM-NEXT: ret561 %1 = sdiv i32 %a, %b562 ret i32 %1563}564 565define i32 @aext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {566; RV64IM-LABEL: aext_divw_aext_zext:567; RV64IM: # %bb.0:568; RV64IM-NEXT: divw a0, a0, a1569; RV64IM-NEXT: ret570 %1 = sdiv i32 %a, %b571 ret i32 %1572}573 574define i32 @aext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {575; RV64IM-LABEL: aext_divw_sext_aext:576; RV64IM: # %bb.0:577; RV64IM-NEXT: divw a0, a0, a1578; RV64IM-NEXT: ret579 %1 = sdiv i32 %a, %b580 ret i32 %1581}582 583define i32 @aext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {584; RV64IM-LABEL: aext_divw_sext_sext:585; RV64IM: # %bb.0:586; RV64IM-NEXT: divw a0, a0, a1587; RV64IM-NEXT: ret588 %1 = sdiv i32 %a, %b589 ret i32 %1590}591 592define i32 @aext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {593; RV64IM-LABEL: aext_divw_sext_zext:594; RV64IM: # %bb.0:595; RV64IM-NEXT: divw a0, a0, a1596; RV64IM-NEXT: ret597 %1 = sdiv i32 %a, %b598 ret i32 %1599}600 601define i32 @aext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {602; RV64IM-LABEL: aext_divw_zext_aext:603; RV64IM: # %bb.0:604; RV64IM-NEXT: divw a0, a0, a1605; RV64IM-NEXT: ret606 %1 = sdiv i32 %a, %b607 ret i32 %1608}609 610define i32 @aext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {611; RV64IM-LABEL: aext_divw_zext_sext:612; RV64IM: # %bb.0:613; RV64IM-NEXT: divw a0, a0, a1614; RV64IM-NEXT: ret615 %1 = sdiv i32 %a, %b616 ret i32 %1617}618 619define i32 @aext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {620; RV64IM-LABEL: aext_divw_zext_zext:621; RV64IM: # %bb.0:622; RV64IM-NEXT: divw a0, a0, a1623; RV64IM-NEXT: ret624 %1 = sdiv i32 %a, %b625 ret i32 %1626}627 628define signext i32 @sext_divw_aext_aext(i32 %a, i32 %b) nounwind {629; RV64IM-LABEL: sext_divw_aext_aext:630; RV64IM: # %bb.0:631; RV64IM-NEXT: divw a0, a0, a1632; RV64IM-NEXT: ret633 %1 = sdiv i32 %a, %b634 ret i32 %1635}636 637define signext i32 @sext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {638; RV64IM-LABEL: sext_divw_aext_sext:639; RV64IM: # %bb.0:640; RV64IM-NEXT: divw a0, a0, a1641; RV64IM-NEXT: ret642 %1 = sdiv i32 %a, %b643 ret i32 %1644}645 646define signext i32 @sext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {647; RV64IM-LABEL: sext_divw_aext_zext:648; RV64IM: # %bb.0:649; RV64IM-NEXT: divw a0, a0, a1650; RV64IM-NEXT: ret651 %1 = sdiv i32 %a, %b652 ret i32 %1653}654 655define signext i32 @sext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {656; RV64IM-LABEL: sext_divw_sext_aext:657; RV64IM: # %bb.0:658; RV64IM-NEXT: divw a0, a0, a1659; RV64IM-NEXT: ret660 %1 = sdiv i32 %a, %b661 ret i32 %1662}663 664define signext i32 @sext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {665; RV64IM-LABEL: sext_divw_sext_sext:666; RV64IM: # %bb.0:667; RV64IM-NEXT: divw a0, a0, a1668; RV64IM-NEXT: ret669 %1 = sdiv i32 %a, %b670 ret i32 %1671}672 673define signext i32 @sext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {674; RV64IM-LABEL: sext_divw_sext_zext:675; RV64IM: # %bb.0:676; RV64IM-NEXT: divw a0, a0, a1677; RV64IM-NEXT: ret678 %1 = sdiv i32 %a, %b679 ret i32 %1680}681 682define signext i32 @sext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {683; RV64IM-LABEL: sext_divw_zext_aext:684; RV64IM: # %bb.0:685; RV64IM-NEXT: divw a0, a0, a1686; RV64IM-NEXT: ret687 %1 = sdiv i32 %a, %b688 ret i32 %1689}690 691define signext i32 @sext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {692; RV64IM-LABEL: sext_divw_zext_sext:693; RV64IM: # %bb.0:694; RV64IM-NEXT: divw a0, a0, a1695; RV64IM-NEXT: ret696 %1 = sdiv i32 %a, %b697 ret i32 %1698}699 700define signext i32 @sext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {701; RV64IM-LABEL: sext_divw_zext_zext:702; RV64IM: # %bb.0:703; RV64IM-NEXT: divw a0, a0, a1704; RV64IM-NEXT: ret705 %1 = sdiv i32 %a, %b706 ret i32 %1707}708 709define zeroext i32 @zext_divw_aext_aext(i32 %a, i32 %b) nounwind {710; RV64IM-LABEL: zext_divw_aext_aext:711; RV64IM: # %bb.0:712; RV64IM-NEXT: divw a0, a0, a1713; RV64IM-NEXT: slli a0, a0, 32714; RV64IM-NEXT: srli a0, a0, 32715; RV64IM-NEXT: ret716 %1 = sdiv i32 %a, %b717 ret i32 %1718}719 720define zeroext i32 @zext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {721; RV64IM-LABEL: zext_divw_aext_sext:722; RV64IM: # %bb.0:723; RV64IM-NEXT: divw a0, a0, a1724; RV64IM-NEXT: slli a0, a0, 32725; RV64IM-NEXT: srli a0, a0, 32726; RV64IM-NEXT: ret727 %1 = sdiv i32 %a, %b728 ret i32 %1729}730 731define zeroext i32 @zext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {732; RV64IM-LABEL: zext_divw_aext_zext:733; RV64IM: # %bb.0:734; RV64IM-NEXT: divw a0, a0, a1735; RV64IM-NEXT: slli a0, a0, 32736; RV64IM-NEXT: srli a0, a0, 32737; RV64IM-NEXT: ret738 %1 = sdiv i32 %a, %b739 ret i32 %1740}741 742define zeroext i32 @zext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {743; RV64IM-LABEL: zext_divw_sext_aext:744; RV64IM: # %bb.0:745; RV64IM-NEXT: divw a0, a0, a1746; RV64IM-NEXT: slli a0, a0, 32747; RV64IM-NEXT: srli a0, a0, 32748; RV64IM-NEXT: ret749 %1 = sdiv i32 %a, %b750 ret i32 %1751}752 753define zeroext i32 @zext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {754; RV64IM-LABEL: zext_divw_sext_sext:755; RV64IM: # %bb.0:756; RV64IM-NEXT: divw a0, a0, a1757; RV64IM-NEXT: slli a0, a0, 32758; RV64IM-NEXT: srli a0, a0, 32759; RV64IM-NEXT: ret760 %1 = sdiv i32 %a, %b761 ret i32 %1762}763 764define zeroext i32 @zext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {765; RV64IM-LABEL: zext_divw_sext_zext:766; RV64IM: # %bb.0:767; RV64IM-NEXT: divw a0, a0, a1768; RV64IM-NEXT: slli a0, a0, 32769; RV64IM-NEXT: srli a0, a0, 32770; RV64IM-NEXT: ret771 %1 = sdiv i32 %a, %b772 ret i32 %1773}774 775define zeroext i32 @zext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {776; RV64IM-LABEL: zext_divw_zext_aext:777; RV64IM: # %bb.0:778; RV64IM-NEXT: divw a0, a0, a1779; RV64IM-NEXT: slli a0, a0, 32780; RV64IM-NEXT: srli a0, a0, 32781; RV64IM-NEXT: ret782 %1 = sdiv i32 %a, %b783 ret i32 %1784}785 786define zeroext i32 @zext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {787; RV64IM-LABEL: zext_divw_zext_sext:788; RV64IM: # %bb.0:789; RV64IM-NEXT: divw a0, a0, a1790; RV64IM-NEXT: slli a0, a0, 32791; RV64IM-NEXT: srli a0, a0, 32792; RV64IM-NEXT: ret793 %1 = sdiv i32 %a, %b794 ret i32 %1795}796 797define zeroext i32 @zext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {798; RV64IM-LABEL: zext_divw_zext_zext:799; RV64IM: # %bb.0:800; RV64IM-NEXT: divw a0, a0, a1801; RV64IM-NEXT: slli a0, a0, 32802; RV64IM-NEXT: srli a0, a0, 32803; RV64IM-NEXT: ret804 %1 = sdiv i32 %a, %b805 ret i32 %1806}807 808define signext i8 @sext_divw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind {809; RV64IM-LABEL: sext_divw_sext_sext_i8:810; RV64IM: # %bb.0:811; RV64IM-NEXT: divw a0, a0, a1812; RV64IM-NEXT: slli a0, a0, 56813; RV64IM-NEXT: srai a0, a0, 56814; RV64IM-NEXT: ret815 %1 = sdiv i8 %a, %b816 ret i8 %1817}818 819define signext i16 @sext_divw_sext_sext_i16(i16 signext %a, i16 signext %b) nounwind {820; RV64IM-LABEL: sext_divw_sext_sext_i16:821; RV64IM: # %bb.0:822; RV64IM-NEXT: divw a0, a0, a1823; RV64IM-NEXT: slli a0, a0, 48824; RV64IM-NEXT: srai a0, a0, 48825; RV64IM-NEXT: ret826 %1 = sdiv i16 %a, %b827 ret i16 %1828}829 830define i32 @aext_remw_aext_aext(i32 %a, i32 %b) nounwind {831; RV64IM-LABEL: aext_remw_aext_aext:832; RV64IM: # %bb.0:833; RV64IM-NEXT: remw a0, a0, a1834; RV64IM-NEXT: ret835 %1 = srem i32 %a, %b836 ret i32 %1837}838 839define i32 @aext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {840; RV64IM-LABEL: aext_remw_aext_sext:841; RV64IM: # %bb.0:842; RV64IM-NEXT: remw a0, a0, a1843; RV64IM-NEXT: ret844 %1 = srem i32 %a, %b845 ret i32 %1846}847 848define i32 @aext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {849; RV64IM-LABEL: aext_remw_aext_zext:850; RV64IM: # %bb.0:851; RV64IM-NEXT: remw a0, a0, a1852; RV64IM-NEXT: ret853 %1 = srem i32 %a, %b854 ret i32 %1855}856 857define i32 @aext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {858; RV64IM-LABEL: aext_remw_sext_aext:859; RV64IM: # %bb.0:860; RV64IM-NEXT: remw a0, a0, a1861; RV64IM-NEXT: ret862 %1 = srem i32 %a, %b863 ret i32 %1864}865 866define i32 @aext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {867; RV64IM-LABEL: aext_remw_sext_sext:868; RV64IM: # %bb.0:869; RV64IM-NEXT: remw a0, a0, a1870; RV64IM-NEXT: ret871 %1 = srem i32 %a, %b872 ret i32 %1873}874 875define i32 @aext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {876; RV64IM-LABEL: aext_remw_sext_zext:877; RV64IM: # %bb.0:878; RV64IM-NEXT: remw a0, a0, a1879; RV64IM-NEXT: ret880 %1 = srem i32 %a, %b881 ret i32 %1882}883 884define i32 @aext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {885; RV64IM-LABEL: aext_remw_zext_aext:886; RV64IM: # %bb.0:887; RV64IM-NEXT: remw a0, a0, a1888; RV64IM-NEXT: ret889 %1 = srem i32 %a, %b890 ret i32 %1891}892 893define i32 @aext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {894; RV64IM-LABEL: aext_remw_zext_sext:895; RV64IM: # %bb.0:896; RV64IM-NEXT: remw a0, a0, a1897; RV64IM-NEXT: ret898 %1 = srem i32 %a, %b899 ret i32 %1900}901 902define i32 @aext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {903; RV64IM-LABEL: aext_remw_zext_zext:904; RV64IM: # %bb.0:905; RV64IM-NEXT: remw a0, a0, a1906; RV64IM-NEXT: ret907 %1 = srem i32 %a, %b908 ret i32 %1909}910 911define signext i32 @sext_remw_aext_aext(i32 %a, i32 %b) nounwind {912; RV64IM-LABEL: sext_remw_aext_aext:913; RV64IM: # %bb.0:914; RV64IM-NEXT: remw a0, a0, a1915; RV64IM-NEXT: ret916 %1 = srem i32 %a, %b917 ret i32 %1918}919 920define signext i32 @sext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {921; RV64IM-LABEL: sext_remw_aext_sext:922; RV64IM: # %bb.0:923; RV64IM-NEXT: remw a0, a0, a1924; RV64IM-NEXT: ret925 %1 = srem i32 %a, %b926 ret i32 %1927}928 929define signext i32 @sext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {930; RV64IM-LABEL: sext_remw_aext_zext:931; RV64IM: # %bb.0:932; RV64IM-NEXT: remw a0, a0, a1933; RV64IM-NEXT: ret934 %1 = srem i32 %a, %b935 ret i32 %1936}937 938define signext i32 @sext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {939; RV64IM-LABEL: sext_remw_sext_aext:940; RV64IM: # %bb.0:941; RV64IM-NEXT: remw a0, a0, a1942; RV64IM-NEXT: ret943 %1 = srem i32 %a, %b944 ret i32 %1945}946 947define signext i32 @sext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {948; RV64IM-LABEL: sext_remw_sext_sext:949; RV64IM: # %bb.0:950; RV64IM-NEXT: remw a0, a0, a1951; RV64IM-NEXT: ret952 %1 = srem i32 %a, %b953 ret i32 %1954}955 956define signext i32 @sext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {957; RV64IM-LABEL: sext_remw_sext_zext:958; RV64IM: # %bb.0:959; RV64IM-NEXT: remw a0, a0, a1960; RV64IM-NEXT: ret961 %1 = srem i32 %a, %b962 ret i32 %1963}964 965define signext i32 @sext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {966; RV64IM-LABEL: sext_remw_zext_aext:967; RV64IM: # %bb.0:968; RV64IM-NEXT: remw a0, a0, a1969; RV64IM-NEXT: ret970 %1 = srem i32 %a, %b971 ret i32 %1972}973 974define signext i32 @sext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {975; RV64IM-LABEL: sext_remw_zext_sext:976; RV64IM: # %bb.0:977; RV64IM-NEXT: remw a0, a0, a1978; RV64IM-NEXT: ret979 %1 = srem i32 %a, %b980 ret i32 %1981}982 983define signext i32 @sext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {984; RV64IM-LABEL: sext_remw_zext_zext:985; RV64IM: # %bb.0:986; RV64IM-NEXT: remw a0, a0, a1987; RV64IM-NEXT: ret988 %1 = srem i32 %a, %b989 ret i32 %1990}991 992define zeroext i32 @zext_remw_aext_aext(i32 %a, i32 %b) nounwind {993; RV64IM-LABEL: zext_remw_aext_aext:994; RV64IM: # %bb.0:995; RV64IM-NEXT: remw a0, a0, a1996; RV64IM-NEXT: slli a0, a0, 32997; RV64IM-NEXT: srli a0, a0, 32998; RV64IM-NEXT: ret999 %1 = srem i32 %a, %b1000 ret i32 %11001}1002 1003define zeroext i32 @zext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {1004; RV64IM-LABEL: zext_remw_aext_sext:1005; RV64IM: # %bb.0:1006; RV64IM-NEXT: remw a0, a0, a11007; RV64IM-NEXT: slli a0, a0, 321008; RV64IM-NEXT: srli a0, a0, 321009; RV64IM-NEXT: ret1010 %1 = srem i32 %a, %b1011 ret i32 %11012}1013 1014define zeroext i32 @zext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1015; RV64IM-LABEL: zext_remw_aext_zext:1016; RV64IM: # %bb.0:1017; RV64IM-NEXT: remw a0, a0, a11018; RV64IM-NEXT: slli a0, a0, 321019; RV64IM-NEXT: srli a0, a0, 321020; RV64IM-NEXT: ret1021 %1 = srem i32 %a, %b1022 ret i32 %11023}1024 1025define zeroext i32 @zext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {1026; RV64IM-LABEL: zext_remw_sext_aext:1027; RV64IM: # %bb.0:1028; RV64IM-NEXT: remw a0, a0, a11029; RV64IM-NEXT: slli a0, a0, 321030; RV64IM-NEXT: srli a0, a0, 321031; RV64IM-NEXT: ret1032 %1 = srem i32 %a, %b1033 ret i32 %11034}1035 1036define zeroext i32 @zext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1037; RV64IM-LABEL: zext_remw_sext_sext:1038; RV64IM: # %bb.0:1039; RV64IM-NEXT: remw a0, a0, a11040; RV64IM-NEXT: slli a0, a0, 321041; RV64IM-NEXT: srli a0, a0, 321042; RV64IM-NEXT: ret1043 %1 = srem i32 %a, %b1044 ret i32 %11045}1046 1047define zeroext i32 @zext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1048; RV64IM-LABEL: zext_remw_sext_zext:1049; RV64IM: # %bb.0:1050; RV64IM-NEXT: remw a0, a0, a11051; RV64IM-NEXT: slli a0, a0, 321052; RV64IM-NEXT: srli a0, a0, 321053; RV64IM-NEXT: ret1054 %1 = srem i32 %a, %b1055 ret i32 %11056}1057 1058define zeroext i32 @zext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1059; RV64IM-LABEL: zext_remw_zext_aext:1060; RV64IM: # %bb.0:1061; RV64IM-NEXT: remw a0, a0, a11062; RV64IM-NEXT: slli a0, a0, 321063; RV64IM-NEXT: srli a0, a0, 321064; RV64IM-NEXT: ret1065 %1 = srem i32 %a, %b1066 ret i32 %11067}1068 1069define zeroext i32 @zext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1070; RV64IM-LABEL: zext_remw_zext_sext:1071; RV64IM: # %bb.0:1072; RV64IM-NEXT: remw a0, a0, a11073; RV64IM-NEXT: slli a0, a0, 321074; RV64IM-NEXT: srli a0, a0, 321075; RV64IM-NEXT: ret1076 %1 = srem i32 %a, %b1077 ret i32 %11078}1079 1080define zeroext i32 @zext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1081; RV64IM-LABEL: zext_remw_zext_zext:1082; RV64IM: # %bb.0:1083; RV64IM-NEXT: remw a0, a0, a11084; RV64IM-NEXT: slli a0, a0, 321085; RV64IM-NEXT: srli a0, a0, 321086; RV64IM-NEXT: ret1087 %1 = srem i32 %a, %b1088 ret i32 %11089}1090 1091define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind {1092; RV64IM-LABEL: sext_remw_sext_sext_i8:1093; RV64IM: # %bb.0:1094; RV64IM-NEXT: remw a0, a0, a11095; RV64IM-NEXT: ret1096 %1 = srem i8 %a, %b1097 ret i8 %11098}1099 1100define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b) nounwind {1101; RV64IM-LABEL: sext_remw_sext_sext_i16:1102; RV64IM: # %bb.0:1103; RV64IM-NEXT: remw a0, a0, a11104; RV64IM-NEXT: ret1105 %1 = srem i16 %a, %b1106 ret i16 %11107}1108 1109define signext i32 @sext_i32_remw_zext_sext_i16(i16 zeroext %0, i16 signext %1) nounwind {1110; RV64IM-LABEL: sext_i32_remw_zext_sext_i16:1111; RV64IM: # %bb.0:1112; RV64IM-NEXT: remw a0, a0, a11113; RV64IM-NEXT: ret1114 %3 = sext i16 %1 to i321115 %4 = zext i16 %0 to i321116 %5 = srem i32 %4, %31117 ret i32 %51118}1119 1120define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b) nounwind {1121; RV64IM-LABEL: sext_i32_remw_sext_zext_i16:1122; RV64IM: # %bb.0:1123; RV64IM-NEXT: remw a0, a0, a11124; RV64IM-NEXT: ret1125 %1 = sext i16 %a to i321126 %2 = zext i16 %b to i321127 %3 = srem i32 %1, %21128 ret i32 %31129}1130 1131define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {1132; RV64IM-LABEL: aext_remuw_aext_aext:1133; RV64IM: # %bb.0:1134; RV64IM-NEXT: remuw a0, a0, a11135; RV64IM-NEXT: ret1136 %1 = urem i32 %a, %b1137 ret i32 %11138}1139 1140define i32 @aext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {1141; RV64IM-LABEL: aext_remuw_aext_sext:1142; RV64IM: # %bb.0:1143; RV64IM-NEXT: remuw a0, a0, a11144; RV64IM-NEXT: ret1145 %1 = urem i32 %a, %b1146 ret i32 %11147}1148 1149define i32 @aext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1150; RV64IM-LABEL: aext_remuw_aext_zext:1151; RV64IM: # %bb.0:1152; RV64IM-NEXT: remuw a0, a0, a11153; RV64IM-NEXT: ret1154 %1 = urem i32 %a, %b1155 ret i32 %11156}1157 1158define i32 @aext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {1159; RV64IM-LABEL: aext_remuw_sext_aext:1160; RV64IM: # %bb.0:1161; RV64IM-NEXT: remuw a0, a0, a11162; RV64IM-NEXT: ret1163 %1 = urem i32 %a, %b1164 ret i32 %11165}1166 1167define i32 @aext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1168; RV64IM-LABEL: aext_remuw_sext_sext:1169; RV64IM: # %bb.0:1170; RV64IM-NEXT: remuw a0, a0, a11171; RV64IM-NEXT: ret1172 %1 = urem i32 %a, %b1173 ret i32 %11174}1175 1176define i32 @aext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1177; RV64IM-LABEL: aext_remuw_sext_zext:1178; RV64IM: # %bb.0:1179; RV64IM-NEXT: remuw a0, a0, a11180; RV64IM-NEXT: ret1181 %1 = urem i32 %a, %b1182 ret i32 %11183}1184 1185define i32 @aext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1186; RV64IM-LABEL: aext_remuw_zext_aext:1187; RV64IM: # %bb.0:1188; RV64IM-NEXT: remuw a0, a0, a11189; RV64IM-NEXT: ret1190 %1 = urem i32 %a, %b1191 ret i32 %11192}1193 1194define i32 @aext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1195; RV64IM-LABEL: aext_remuw_zext_sext:1196; RV64IM: # %bb.0:1197; RV64IM-NEXT: remuw a0, a0, a11198; RV64IM-NEXT: ret1199 %1 = urem i32 %a, %b1200 ret i32 %11201}1202 1203define i32 @aext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1204; RV64IM-LABEL: aext_remuw_zext_zext:1205; RV64IM: # %bb.0:1206; RV64IM-NEXT: remuw a0, a0, a11207; RV64IM-NEXT: ret1208 %1 = urem i32 %a, %b1209 ret i32 %11210}1211 1212define signext i32 @sext_remuw_aext_aext(i32 %a, i32 %b) nounwind {1213; RV64IM-LABEL: sext_remuw_aext_aext:1214; RV64IM: # %bb.0:1215; RV64IM-NEXT: remuw a0, a0, a11216; RV64IM-NEXT: ret1217 %1 = urem i32 %a, %b1218 ret i32 %11219}1220 1221define signext i32 @sext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {1222; RV64IM-LABEL: sext_remuw_aext_sext:1223; RV64IM: # %bb.0:1224; RV64IM-NEXT: remuw a0, a0, a11225; RV64IM-NEXT: ret1226 %1 = urem i32 %a, %b1227 ret i32 %11228}1229 1230define signext i32 @sext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1231; RV64IM-LABEL: sext_remuw_aext_zext:1232; RV64IM: # %bb.0:1233; RV64IM-NEXT: remuw a0, a0, a11234; RV64IM-NEXT: ret1235 %1 = urem i32 %a, %b1236 ret i32 %11237}1238 1239define signext i32 @sext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {1240; RV64IM-LABEL: sext_remuw_sext_aext:1241; RV64IM: # %bb.0:1242; RV64IM-NEXT: remuw a0, a0, a11243; RV64IM-NEXT: ret1244 %1 = urem i32 %a, %b1245 ret i32 %11246}1247 1248define signext i32 @sext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1249; RV64IM-LABEL: sext_remuw_sext_sext:1250; RV64IM: # %bb.0:1251; RV64IM-NEXT: remuw a0, a0, a11252; RV64IM-NEXT: ret1253 %1 = urem i32 %a, %b1254 ret i32 %11255}1256 1257define signext i32 @sext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1258; RV64IM-LABEL: sext_remuw_sext_zext:1259; RV64IM: # %bb.0:1260; RV64IM-NEXT: remuw a0, a0, a11261; RV64IM-NEXT: ret1262 %1 = urem i32 %a, %b1263 ret i32 %11264}1265 1266define signext i32 @sext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1267; RV64IM-LABEL: sext_remuw_zext_aext:1268; RV64IM: # %bb.0:1269; RV64IM-NEXT: remuw a0, a0, a11270; RV64IM-NEXT: ret1271 %1 = urem i32 %a, %b1272 ret i32 %11273}1274 1275define signext i32 @sext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1276; RV64IM-LABEL: sext_remuw_zext_sext:1277; RV64IM: # %bb.0:1278; RV64IM-NEXT: remuw a0, a0, a11279; RV64IM-NEXT: ret1280 %1 = urem i32 %a, %b1281 ret i32 %11282}1283 1284define signext i32 @sext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1285; RV64IM-LABEL: sext_remuw_zext_zext:1286; RV64IM: # %bb.0:1287; RV64IM-NEXT: remuw a0, a0, a11288; RV64IM-NEXT: ret1289 %1 = urem i32 %a, %b1290 ret i32 %11291}1292 1293define zeroext i32 @zext_remuw_aext_aext(i32 %a, i32 %b) nounwind {1294; RV64IM-LABEL: zext_remuw_aext_aext:1295; RV64IM: # %bb.0:1296; RV64IM-NEXT: remuw a0, a0, a11297; RV64IM-NEXT: slli a0, a0, 321298; RV64IM-NEXT: srli a0, a0, 321299; RV64IM-NEXT: ret1300 %1 = urem i32 %a, %b1301 ret i32 %11302}1303 1304define zeroext i32 @zext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {1305; RV64IM-LABEL: zext_remuw_aext_sext:1306; RV64IM: # %bb.0:1307; RV64IM-NEXT: remuw a0, a0, a11308; RV64IM-NEXT: slli a0, a0, 321309; RV64IM-NEXT: srli a0, a0, 321310; RV64IM-NEXT: ret1311 %1 = urem i32 %a, %b1312 ret i32 %11313}1314 1315define zeroext i32 @zext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {1316; RV64IM-LABEL: zext_remuw_aext_zext:1317; RV64IM: # %bb.0:1318; RV64IM-NEXT: remuw a0, a0, a11319; RV64IM-NEXT: slli a0, a0, 321320; RV64IM-NEXT: srli a0, a0, 321321; RV64IM-NEXT: ret1322 %1 = urem i32 %a, %b1323 ret i32 %11324}1325 1326define zeroext i32 @zext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {1327; RV64IM-LABEL: zext_remuw_sext_aext:1328; RV64IM: # %bb.0:1329; RV64IM-NEXT: remuw a0, a0, a11330; RV64IM-NEXT: slli a0, a0, 321331; RV64IM-NEXT: srli a0, a0, 321332; RV64IM-NEXT: ret1333 %1 = urem i32 %a, %b1334 ret i32 %11335}1336 1337define zeroext i32 @zext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {1338; RV64IM-LABEL: zext_remuw_sext_sext:1339; RV64IM: # %bb.0:1340; RV64IM-NEXT: remuw a0, a0, a11341; RV64IM-NEXT: slli a0, a0, 321342; RV64IM-NEXT: srli a0, a0, 321343; RV64IM-NEXT: ret1344 %1 = urem i32 %a, %b1345 ret i32 %11346}1347 1348define zeroext i32 @zext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {1349; RV64IM-LABEL: zext_remuw_sext_zext:1350; RV64IM: # %bb.0:1351; RV64IM-NEXT: remuw a0, a0, a11352; RV64IM-NEXT: slli a0, a0, 321353; RV64IM-NEXT: srli a0, a0, 321354; RV64IM-NEXT: ret1355 %1 = urem i32 %a, %b1356 ret i32 %11357}1358 1359define zeroext i32 @zext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {1360; RV64IM-LABEL: zext_remuw_zext_aext:1361; RV64IM: # %bb.0:1362; RV64IM-NEXT: remuw a0, a0, a11363; RV64IM-NEXT: slli a0, a0, 321364; RV64IM-NEXT: srli a0, a0, 321365; RV64IM-NEXT: ret1366 %1 = urem i32 %a, %b1367 ret i32 %11368}1369 1370define zeroext i32 @zext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {1371; RV64IM-LABEL: zext_remuw_zext_sext:1372; RV64IM: # %bb.0:1373; RV64IM-NEXT: remuw a0, a0, a11374; RV64IM-NEXT: slli a0, a0, 321375; RV64IM-NEXT: srli a0, a0, 321376; RV64IM-NEXT: ret1377 %1 = urem i32 %a, %b1378 ret i32 %11379}1380 1381define zeroext i32 @zext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {1382; RV64IM-LABEL: zext_remuw_zext_zext:1383; RV64IM: # %bb.0:1384; RV64IM-NEXT: remu a0, a0, a11385; RV64IM-NEXT: ret1386 %1 = urem i32 %a, %b1387 ret i32 %11388}1389 1390define zeroext i8 @zext_remuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b) nounwind {1391; RV64IM-LABEL: zext_remuw_zext_zext_i8:1392; RV64IM: # %bb.0:1393; RV64IM-NEXT: remuw a0, a0, a11394; RV64IM-NEXT: ret1395 %1 = urem i8 %a, %b1396 ret i8 %11397}1398 1399define zeroext i16 @zext_remuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b) nounwind {1400; RV64IM-LABEL: zext_remuw_zext_zext_i16:1401; RV64IM: # %bb.0:1402; RV64IM-NEXT: remuw a0, a0, a11403; RV64IM-NEXT: ret1404 %1 = urem i16 %a, %b1405 ret i16 %11406}1407