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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define signext i32 @ctlz_i32(i32 signext %a) nounwind {6; CHECK-LABEL: ctlz_i32:7; CHECK: # %bb.0:8; CHECK-NEXT: clzw a0, a09; CHECK-NEXT: ret10 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)11 ret i32 %112}13 14define signext i32 @log2_i32(i32 signext %a) nounwind {15; CHECK-LABEL: log2_i32:16; CHECK: # %bb.0:17; CHECK-NEXT: clzw a0, a018; CHECK-NEXT: li a1, 3119; CHECK-NEXT: sub a0, a1, a020; CHECK-NEXT: ret21 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)22 %2 = sub i32 31, %123 ret i32 %224}25 26define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {27; CHECK-LABEL: log2_ceil_i32:28; CHECK: # %bb.0:29; CHECK-NEXT: addi a0, a0, -130; CHECK-NEXT: clzw a0, a031; CHECK-NEXT: li a1, 3232; CHECK-NEXT: sub a0, a1, a033; CHECK-NEXT: ret34 %1 = sub i32 %a, 135 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)36 %3 = sub i32 32, %237 ret i32 %338}39 40define signext i32 @findLastSet_i32(i32 signext %a) nounwind {41; CHECK-LABEL: findLastSet_i32:42; CHECK: # %bb.0:43; CHECK-NEXT: clzw a1, a044; CHECK-NEXT: snez a0, a045; CHECK-NEXT: xori a1, a1, 3146; CHECK-NEXT: addi a0, a0, -147; CHECK-NEXT: or a0, a0, a148; CHECK-NEXT: ret49 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)50 %2 = xor i32 31, %151 %3 = icmp eq i32 %a, 052 %4 = select i1 %3, i32 -1, i32 %253 ret i32 %454}55 56define i32 @ctlz_lshr_i32(i32 signext %a) {57; CHECK-LABEL: ctlz_lshr_i32:58; CHECK: # %bb.0:59; CHECK-NEXT: srliw a0, a0, 160; CHECK-NEXT: clzw a0, a061; CHECK-NEXT: ret62 %1 = lshr i32 %a, 163 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)64 ret i32 %265}66 67define i64 @ctlz_i64(i64 %a) nounwind {68; CHECK-LABEL: ctlz_i64:69; CHECK: # %bb.0:70; CHECK-NEXT: clz a0, a071; CHECK-NEXT: ret72 %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)73 ret i64 %174}75 76define signext i32 @cttz_i32(i32 signext %a) nounwind {77; CHECK-LABEL: cttz_i32:78; CHECK: # %bb.0:79; CHECK-NEXT: beqz a0, .LBB6_280; CHECK-NEXT: # %bb.1: # %cond.false81; CHECK-NEXT: addi a1, a0, -182; CHECK-NEXT: not a0, a083; CHECK-NEXT: and a0, a0, a184; CHECK-NEXT: clzw a0, a085; CHECK-NEXT: li a1, 3286; CHECK-NEXT: sub a0, a1, a087; CHECK-NEXT: ret88; CHECK-NEXT: .LBB6_2:89; CHECK-NEXT: li a0, 3290; CHECK-NEXT: ret91 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)92 ret i32 %193}94 95define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {96; CHECK-LABEL: cttz_zero_undef_i32:97; CHECK: # %bb.0:98; CHECK-NEXT: addi a1, a0, -199; CHECK-NEXT: not a0, a0100; CHECK-NEXT: and a0, a0, a1101; CHECK-NEXT: clzw a0, a0102; CHECK-NEXT: li a1, 32103; CHECK-NEXT: sub a0, a1, a0104; CHECK-NEXT: ret105 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)106 ret i32 %1107}108 109define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {110; CHECK-LABEL: findFirstSet_i32:111; CHECK: # %bb.0:112; CHECK-NEXT: addi a1, a0, -1113; CHECK-NEXT: not a2, a0114; CHECK-NEXT: and a1, a2, a1115; CHECK-NEXT: li a2, 32116; CHECK-NEXT: snez a0, a0117; CHECK-NEXT: clzw a1, a1118; CHECK-NEXT: sub a2, a2, a1119; CHECK-NEXT: addi a0, a0, -1120; CHECK-NEXT: or a0, a0, a2121; CHECK-NEXT: ret122 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)123 %2 = icmp eq i32 %a, 0124 %3 = select i1 %2, i32 -1, i32 %1125 ret i32 %3126}127 128define signext i32 @ffs_i32(i32 signext %a) nounwind {129; CHECK-LABEL: ffs_i32:130; CHECK: # %bb.0:131; CHECK-NEXT: addi a1, a0, -1132; CHECK-NEXT: not a2, a0133; CHECK-NEXT: and a1, a2, a1134; CHECK-NEXT: li a2, 33135; CHECK-NEXT: seqz a0, a0136; CHECK-NEXT: clzw a1, a1137; CHECK-NEXT: sub a2, a2, a1138; CHECK-NEXT: addi a0, a0, -1139; CHECK-NEXT: and a0, a0, a2140; CHECK-NEXT: ret141 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)142 %2 = add i32 %1, 1143 %3 = icmp eq i32 %a, 0144 %4 = select i1 %3, i32 0, i32 %2145 ret i32 %4146}147 148define i64 @cttz_i64(i64 %a) nounwind {149; CHECK-LABEL: cttz_i64:150; CHECK: # %bb.0:151; CHECK-NEXT: beqz a0, .LBB10_2152; CHECK-NEXT: # %bb.1: # %cond.false153; CHECK-NEXT: addi a1, a0, -1154; CHECK-NEXT: not a0, a0155; CHECK-NEXT: and a0, a0, a1156; CHECK-NEXT: clz a0, a0157; CHECK-NEXT: li a1, 64158; CHECK-NEXT: sub a0, a1, a0159; CHECK-NEXT: ret160; CHECK-NEXT: .LBB10_2:161; CHECK-NEXT: li a0, 64162; CHECK-NEXT: ret163 %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)164 ret i64 %1165}166 167define signext i32 @sextb_i32(i32 signext %a) nounwind {168; CHECK-LABEL: sextb_i32:169; CHECK: # %bb.0:170; CHECK-NEXT: sext.b a0, a0171; CHECK-NEXT: ret172 %shl = shl i32 %a, 24173 %shr = ashr exact i32 %shl, 24174 ret i32 %shr175}176 177define i64 @sextb_i64(i64 %a) nounwind {178; CHECK-LABEL: sextb_i64:179; CHECK: # %bb.0:180; CHECK-NEXT: sext.b a0, a0181; CHECK-NEXT: ret182 %shl = shl i64 %a, 56183 %shr = ashr exact i64 %shl, 56184 ret i64 %shr185}186 187define signext i32 @sexth_i32(i32 signext %a) nounwind {188; CHECK-LABEL: sexth_i32:189; CHECK: # %bb.0:190; CHECK-NEXT: sext.h a0, a0191; CHECK-NEXT: ret192 %shl = shl i32 %a, 16193 %shr = ashr exact i32 %shl, 16194 ret i32 %shr195}196 197define i64 @sexth_i64(i64 %a) nounwind {198; CHECK-LABEL: sexth_i64:199; CHECK: # %bb.0:200; CHECK-NEXT: sext.h a0, a0201; CHECK-NEXT: ret202 %shl = shl i64 %a, 48203 %shr = ashr exact i64 %shl, 48204 ret i64 %shr205}206 207define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {208; CHECK-LABEL: min_i32:209; CHECK: # %bb.0:210; CHECK-NEXT: min a0, a0, a1211; CHECK-NEXT: ret212 %cmp = icmp slt i32 %a, %b213 %cond = select i1 %cmp, i32 %a, i32 %b214 ret i32 %cond215}216 217define i64 @min_i64(i64 %a, i64 %b) nounwind {218; CHECK-LABEL: min_i64:219; CHECK: # %bb.0:220; CHECK-NEXT: min a0, a0, a1221; CHECK-NEXT: ret222 %cmp = icmp slt i64 %a, %b223 %cond = select i1 %cmp, i64 %a, i64 %b224 ret i64 %cond225}226 227define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {228; CHECK-LABEL: max_i32:229; CHECK: # %bb.0:230; CHECK-NEXT: max a0, a0, a1231; CHECK-NEXT: ret232 %cmp = icmp sgt i32 %a, %b233 %cond = select i1 %cmp, i32 %a, i32 %b234 ret i32 %cond235}236 237define i64 @max_i64(i64 %a, i64 %b) nounwind {238; CHECK-LABEL: max_i64:239; CHECK: # %bb.0:240; CHECK-NEXT: max a0, a0, a1241; CHECK-NEXT: ret242 %cmp = icmp sgt i64 %a, %b243 %cond = select i1 %cmp, i64 %a, i64 %b244 ret i64 %cond245}246 247define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {248; CHECK-LABEL: minu_i32:249; CHECK: # %bb.0:250; CHECK-NEXT: minu a0, a0, a1251; CHECK-NEXT: ret252 %cmp = icmp ult i32 %a, %b253 %cond = select i1 %cmp, i32 %a, i32 %b254 ret i32 %cond255}256 257define i64 @minu_i64(i64 %a, i64 %b) nounwind {258; CHECK-LABEL: minu_i64:259; CHECK: # %bb.0:260; CHECK-NEXT: minu a0, a0, a1261; CHECK-NEXT: ret262 %cmp = icmp ult i64 %a, %b263 %cond = select i1 %cmp, i64 %a, i64 %b264 ret i64 %cond265}266 267define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {268; CHECK-LABEL: maxu_i32:269; CHECK: # %bb.0:270; CHECK-NEXT: maxu a0, a0, a1271; CHECK-NEXT: ret272 %cmp = icmp ugt i32 %a, %b273 %cond = select i1 %cmp, i32 %a, i32 %b274 ret i32 %cond275}276 277define i64 @maxu_i64(i64 %a, i64 %b) nounwind {278; CHECK-LABEL: maxu_i64:279; CHECK: # %bb.0:280; CHECK-NEXT: maxu a0, a0, a1281; CHECK-NEXT: ret282 %cmp = icmp ugt i64 %a, %b283 %cond = select i1 %cmp, i64 %a, i64 %b284 ret i64 %cond285}286 287define i32 @abs_i32(i32 %x) {288; CHECK-LABEL: abs_i32:289; CHECK: # %bb.0:290; CHECK-NEXT: absw a0, a0291; CHECK-NEXT: ret292 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)293 ret i32 %abs294}295 296define signext i32 @abs_i32_sext(i32 signext %x) {297; CHECK-LABEL: abs_i32_sext:298; CHECK: # %bb.0:299; CHECK-NEXT: absw a0, a0300; CHECK-NEXT: ret301 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)302 ret i32 %abs303}304 305define i64 @abs_i64(i64 %x) {306; CHECK-LABEL: abs_i64:307; CHECK: # %bb.0:308; CHECK-NEXT: abs a0, a0309; CHECK-NEXT: ret310 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)311 ret i64 %abs312}313 314define signext i32 @bswap_i32(i32 signext %a) nounwind {315; CHECK-LABEL: bswap_i32:316; CHECK: # %bb.0:317; CHECK-NEXT: rev8 a0, a0318; CHECK-NEXT: srai a0, a0, 32319; CHECK-NEXT: ret320 %1 = tail call i32 @llvm.bswap.i32(i32 %a)321 ret i32 %1322}323 324; Similar to bswap_i32 but the result is not sign extended.325define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {326; CHECK-LABEL: bswap_i32_nosext:327; CHECK: # %bb.0:328; CHECK-NEXT: rev8 a0, a0329; CHECK-NEXT: srli a0, a0, 32330; CHECK-NEXT: sw a0, 0(a1)331; CHECK-NEXT: ret332 %1 = tail call i32 @llvm.bswap.i32(i32 %a)333 store i32 %1, ptr %x334 ret void335}336 337define i64 @bswap_i64(i64 %a) {338; CHECK-LABEL: bswap_i64:339; CHECK: # %bb.0:340; CHECK-NEXT: rev8 a0, a0341; CHECK-NEXT: ret342 %1 = call i64 @llvm.bswap.i64(i64 %a)343 ret i64 %1344}345 346define i64 @srai_slli(i16 signext %0) {347; CHECK-LABEL: srai_slli:348; CHECK: # %bb.0:349; CHECK-NEXT: slli a0, a0, 57350; CHECK-NEXT: srai a0, a0, 63351; CHECK-NEXT: ret352 %2 = shl i16 %0, 9353 %sext = ashr i16 %2, 15354 %3 = sext i16 %sext to i64355 ret i64 %3356}357 358define i64 @srai_slli2(i16 signext %0) {359; CHECK-LABEL: srai_slli2:360; CHECK: # %bb.0:361; CHECK-NEXT: slli a0, a0, 57362; CHECK-NEXT: srai a0, a0, 62363; CHECK-NEXT: ret364 %2 = shl i16 %0, 9365 %sext = ashr i16 %2, 14366 %3 = sext i16 %sext to i64367 ret i64 %3368}369 370define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 {371; CHECK-LABEL: func0000000000000001:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: slli a1, a1, 59374; CHECK-NEXT: srai a1, a1, 63375; CHECK-NEXT: addw a0, a1, a0376; CHECK-NEXT: ret377entry:378 %2 = shl i8 %1, 3379 %3 = ashr i8 %2, 7380 %4 = sext i8 %3 to i32381 %5 = add nsw i32 %4, %0382 ret i32 %5383}384 385define i8 @sub_if_uge_i8(i8 %x, i8 %y) {386; CHECK-LABEL: sub_if_uge_i8:387; CHECK: # %bb.0:388; CHECK-NEXT: zext.b a2, a0389; CHECK-NEXT: sub a0, a0, a1390; CHECK-NEXT: zext.b a0, a0391; CHECK-NEXT: minu a0, a2, a0392; CHECK-NEXT: ret393 %cmp = icmp ult i8 %x, %y394 %select = select i1 %cmp, i8 0, i8 %y395 %sub = sub nuw i8 %x, %select396 ret i8 %sub397}398 399define i16 @sub_if_uge_i16(i16 %x, i16 %y) {400; CHECK-LABEL: sub_if_uge_i16:401; CHECK: # %bb.0:402; CHECK-NEXT: lui a2, 16403; CHECK-NEXT: sub a1, a0, a1404; CHECK-NEXT: addi a2, a2, -1405; CHECK-NEXT: and a0, a0, a2406; CHECK-NEXT: and a1, a1, a2407; CHECK-NEXT: minu a0, a0, a1408; CHECK-NEXT: ret409 %cmp = icmp ult i16 %x, %y410 %select = select i1 %cmp, i16 0, i16 %y411 %sub = sub nuw i16 %x, %select412 ret i16 %sub413}414 415define i32 @sub_if_uge_i32(i32 %x, i32 %y) {416; CHECK-LABEL: sub_if_uge_i32:417; CHECK: # %bb.0:418; CHECK-NEXT: sext.w a2, a0419; CHECK-NEXT: subw a0, a0, a1420; CHECK-NEXT: minu a0, a2, a0421; CHECK-NEXT: ret422 %cmp = icmp ult i32 %x, %y423 %select = select i1 %cmp, i32 0, i32 %y424 %sub = sub nuw i32 %x, %select425 ret i32 %sub426}427 428define i64 @sub_if_uge_i64(i64 %x, i64 %y) {429; CHECK-LABEL: sub_if_uge_i64:430; CHECK: # %bb.0:431; CHECK-NEXT: sub a1, a0, a1432; CHECK-NEXT: minu a0, a0, a1433; CHECK-NEXT: ret434 %cmp = icmp ult i64 %x, %y435 %select = select i1 %cmp, i64 0, i64 %y436 %sub = sub nuw i64 %x, %select437 ret i64 %sub438}439 440define i128 @sub_if_uge_i128(i128 %x, i128 %y) {441; CHECK-LABEL: sub_if_uge_i128:442; CHECK: # %bb.0:443; CHECK-NEXT: beq a1, a3, .LBB36_2444; CHECK-NEXT: # %bb.1:445; CHECK-NEXT: sltu a4, a1, a3446; CHECK-NEXT: j .LBB36_3447; CHECK-NEXT: .LBB36_2:448; CHECK-NEXT: sltu a4, a0, a2449; CHECK-NEXT: .LBB36_3:450; CHECK-NEXT: addi a4, a4, -1451; CHECK-NEXT: and a3, a4, a3452; CHECK-NEXT: and a2, a4, a2453; CHECK-NEXT: sltu a4, a0, a2454; CHECK-NEXT: sub a1, a1, a3455; CHECK-NEXT: sub a1, a1, a4456; CHECK-NEXT: sub a0, a0, a2457; CHECK-NEXT: ret458 %cmp = icmp ult i128 %x, %y459 %select = select i1 %cmp, i128 0, i128 %y460 %sub = sub nuw i128 %x, %select461 ret i128 %sub462}463 464define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {465; CHECK-LABEL: sub_if_uge_multiuse_select_i32:466; CHECK: # %bb.0:467; CHECK-NEXT: sext.w a2, a1468; CHECK-NEXT: sext.w a3, a0469; CHECK-NEXT: sltu a2, a3, a2470; CHECK-NEXT: addi a2, a2, -1471; CHECK-NEXT: and a1, a2, a1472; CHECK-NEXT: sub a0, a0, a1473; CHECK-NEXT: sllw a0, a0, a1474; CHECK-NEXT: ret475 %cmp = icmp ult i32 %x, %y476 %select = select i1 %cmp, i32 0, i32 %y477 %sub = sub nuw i32 %x, %select478 %shl = shl i32 %sub, %select479 ret i32 %shl480}481 482define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {483; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:484; CHECK: # %bb.0:485; CHECK-NEXT: sext.w a2, a1486; CHECK-NEXT: sext.w a3, a0487; CHECK-NEXT: subw a0, a0, a1488; CHECK-NEXT: minu a0, a3, a0489; CHECK-NEXT: bltu a3, a2, .LBB38_2490; CHECK-NEXT: # %bb.1:491; CHECK-NEXT: li a1, 4492; CHECK-NEXT: sllw a0, a0, a1493; CHECK-NEXT: ret494; CHECK-NEXT: .LBB38_2:495; CHECK-NEXT: li a1, 2496; CHECK-NEXT: sllw a0, a0, a1497; CHECK-NEXT: ret498 %cmp = icmp ult i32 %x, %y499 %select = select i1 %cmp, i32 0, i32 %y500 %sub = sub nuw i32 %x, %select501 %select2 = select i1 %cmp, i32 2, i32 4502 %shl = shl i32 %sub, %select2503 ret i32 %shl504}505 506define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) {507; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32:508; CHECK: # %bb.0:509; CHECK-NEXT: sltu a3, a0, a1510; CHECK-NEXT: subw a1, a0, a1511; CHECK-NEXT: xori a3, a3, 1512; CHECK-NEXT: minu a0, a0, a1513; CHECK-NEXT: sw a3, 0(a2)514; CHECK-NEXT: ret515 %cmp = icmp uge i32 %x, %y516 %conv = zext i1 %cmp to i32517 store i32 %conv, ptr %z, align 4518 %select = select i1 %cmp, i32 %y, i32 0519 %sub = sub nuw i32 %x, %select520 ret i32 %sub521}522 523define i8 @sub_if_uge_C_i8(i8 zeroext %x) {524; CHECK-LABEL: sub_if_uge_C_i8:525; CHECK: # %bb.0:526; CHECK-NEXT: addi a1, a0, -13527; CHECK-NEXT: zext.b a1, a1528; CHECK-NEXT: minu a0, a1, a0529; CHECK-NEXT: ret530 %cmp = icmp ugt i8 %x, 12531 %sub = add i8 %x, -13532 %conv4 = select i1 %cmp, i8 %sub, i8 %x533 ret i8 %conv4534}535 536define i16 @sub_if_uge_C_i16(i16 zeroext %x) {537; CHECK-LABEL: sub_if_uge_C_i16:538; CHECK: # %bb.0:539; CHECK-NEXT: addi a1, a0, -251540; CHECK-NEXT: slli a1, a1, 48541; CHECK-NEXT: srli a1, a1, 48542; CHECK-NEXT: minu a0, a1, a0543; CHECK-NEXT: ret544 %cmp = icmp ugt i16 %x, 250545 %sub = add i16 %x, -251546 %conv4 = select i1 %cmp, i16 %sub, i16 %x547 ret i16 %conv4548}549 550define i32 @sub_if_uge_C_i32(i32 signext %x) {551; CHECK-LABEL: sub_if_uge_C_i32:552; CHECK: # %bb.0:553; CHECK-NEXT: lui a1, 1048560554; CHECK-NEXT: addi a1, a1, 15555; CHECK-NEXT: addw a1, a0, a1556; CHECK-NEXT: minu a0, a1, a0557; CHECK-NEXT: ret558 %cmp = icmp ugt i32 %x, 65520559 %sub = add i32 %x, -65521560 %cond = select i1 %cmp, i32 %sub, i32 %x561 ret i32 %cond562}563 564define i64 @sub_if_uge_C_i64(i64 %x) {565; CHECK-LABEL: sub_if_uge_C_i64:566; CHECK: # %bb.0:567; CHECK-NEXT: lui a1, 1046192568; CHECK-NEXT: addi a1, a1, -761569; CHECK-NEXT: slli a1, a1, 9570; CHECK-NEXT: add a1, a0, a1571; CHECK-NEXT: minu a0, a1, a0572; CHECK-NEXT: ret573 %cmp = icmp ugt i64 %x, 4999999999574 %sub = add i64 %x, -5000000000575 %cond = select i1 %cmp, i64 %sub, i64 %x576 ret i64 %cond577}578 579define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {580; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:581; CHECK: # %bb.0:582; CHECK-NEXT: lui a2, 16583; CHECK-NEXT: lui a3, 1048560584; CHECK-NEXT: addi a2, a2, -16585; CHECK-NEXT: addi a3, a3, 15586; CHECK-NEXT: sltu a2, a2, a0587; CHECK-NEXT: addw a3, a0, a3588; CHECK-NEXT: minu a0, a3, a0589; CHECK-NEXT: sw a2, 0(a1)590; CHECK-NEXT: ret591 %cmp = icmp ugt i32 %x, 65520592 %conv = zext i1 %cmp to i32593 store i32 %conv, ptr %z, align 4594 %sub = add i32 %x, -65521595 %cond = select i1 %cmp, i32 %sub, i32 %x596 ret i32 %cond597}598 599define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {600; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:601; CHECK: # %bb.0:602; CHECK-NEXT: lui a2, 1048560603; CHECK-NEXT: addi a2, a2, 15604; CHECK-NEXT: addw a2, a0, a2605; CHECK-NEXT: minu a0, a2, a0606; CHECK-NEXT: sw a2, 0(a1)607; CHECK-NEXT: ret608 %sub = add i32 %x, -65521609 store i32 %sub, ptr %z, align 4610 %cmp = icmp ugt i32 %x, 65520611 %cond = select i1 %cmp, i32 %sub, i32 %x612 ret i32 %cond613}614 615define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {616; CHECK-LABEL: sub_if_uge_C_swapped_i32:617; CHECK: # %bb.0:618; CHECK-NEXT: lui a1, 1048560619; CHECK-NEXT: addi a1, a1, 15620; CHECK-NEXT: addw a1, a0, a1621; CHECK-NEXT: minu a0, a0, a1622; CHECK-NEXT: ret623 %cmp = icmp ult i32 %x, 65521624 %sub = add i32 %x, -65521625 %cond = select i1 %cmp, i32 %x, i32 %sub626 ret i32 %cond627}628 629define i7 @sub_if_uge_C_nsw_i7(i7 %a) {630; CHECK-LABEL: sub_if_uge_C_nsw_i7:631; CHECK: # %bb.0:632; CHECK-NEXT: ori a0, a0, 51633; CHECK-NEXT: andi a1, a0, 127634; CHECK-NEXT: addi a0, a0, 17635; CHECK-NEXT: andi a0, a0, 92636; CHECK-NEXT: minu a0, a0, a1637; CHECK-NEXT: ret638 %x = or i7 %a, 51639 %c = icmp ugt i7 %x, -18640 %add = add nsw i7 %x, 17641 %s = select i1 %c, i7 %add, i7 %x642 ret i7 %s643}644 645define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {646; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7:647; CHECK: # %bb.0:648; CHECK-NEXT: ori a0, a0, 51649; CHECK-NEXT: andi a1, a0, 127650; CHECK-NEXT: addi a0, a0, 17651; CHECK-NEXT: andi a0, a0, 92652; CHECK-NEXT: minu a0, a1, a0653; CHECK-NEXT: ret654 %x = or i7 %a, 51655 %c = icmp ult i7 %x, -17656 %add = add nsw i7 %x, 17657 %s = select i1 %c, i7 %x, i7 %add658 ret i7 %s659}660