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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=RV64I4; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=RV64XTHEADBS6 7define signext i32 @th_tst_i32(i32 signext %a) nounwind {8; RV64I-LABEL: th_tst_i32:9; RV64I: # %bb.0:10; RV64I-NEXT: slli a0, a0, 5811; RV64I-NEXT: srli a0, a0, 6312; RV64I-NEXT: ret13;14; RV64XTHEADBS-LABEL: th_tst_i32:15; RV64XTHEADBS: # %bb.0:16; RV64XTHEADBS-NEXT: th.tst a0, a0, 517; RV64XTHEADBS-NEXT: ret18 %shr = lshr i32 %a, 519 %and = and i32 %shr, 120 ret i32 %and21}22 23define i64 @the_tst_i64(i64 %a) nounwind {24; RV64I-LABEL: the_tst_i64:25; RV64I: # %bb.0:26; RV64I-NEXT: slli a0, a0, 5827; RV64I-NEXT: srli a0, a0, 6328; RV64I-NEXT: ret29;30; RV64XTHEADBS-LABEL: the_tst_i64:31; RV64XTHEADBS: # %bb.0:32; RV64XTHEADBS-NEXT: th.tst a0, a0, 533; RV64XTHEADBS-NEXT: ret34 %shr = lshr i64 %a, 535 %and = and i64 %shr, 136 ret i64 %and37}38 39define signext i32 @th_tst_i32_cmp(i32 signext %a) nounwind {40; RV64I-LABEL: th_tst_i32_cmp:41; RV64I: # %bb.0:42; RV64I-NEXT: slli a0, a0, 5843; RV64I-NEXT: srli a0, a0, 6344; RV64I-NEXT: ret45;46; RV64XTHEADBS-LABEL: th_tst_i32_cmp:47; RV64XTHEADBS: # %bb.0:48; RV64XTHEADBS-NEXT: th.tst a0, a0, 549; RV64XTHEADBS-NEXT: ret50 %and = and i32 %a, 3251 %cmp = icmp ne i32 %and, 052 %zext = zext i1 %cmp to i3253 ret i32 %zext54}55 56define i64 @th_tst_i64_cmp(i64 %a) nounwind {57; RV64I-LABEL: th_tst_i64_cmp:58; RV64I: # %bb.0:59; RV64I-NEXT: slli a0, a0, 5860; RV64I-NEXT: srli a0, a0, 6361; RV64I-NEXT: ret62;63; RV64XTHEADBS-LABEL: th_tst_i64_cmp:64; RV64XTHEADBS: # %bb.0:65; RV64XTHEADBS-NEXT: th.tst a0, a0, 566; RV64XTHEADBS-NEXT: ret67 %and = and i64 %a, 3268 %cmp = icmp ne i64 %and, 069 %zext = zext i1 %cmp to i6470 ret i64 %zext71}72