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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I4; RUN: llc -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBANOZBB6; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBAZBB,RV64ZBAZBBNOZBS8; RUN: llc -mtriple=riscv64 -mattr=+m,+zba,+zbb,+zbs -verify-machineinstrs < %s \9; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBAZBB,RV64ZBAZBBZBS10; RUN: llc -mtriple=riscv64 -mattr=+m,+xandesperf -verify-machineinstrs < %s \11; RUN: | FileCheck %s -check-prefixes=CHECK,RV64XANDESPERF12 13define i64 @slliuw(i64 %a) nounwind {14; RV64I-LABEL: slliuw:15; RV64I: # %bb.0:16; RV64I-NEXT: slli a0, a0, 3217; RV64I-NEXT: srli a0, a0, 3118; RV64I-NEXT: ret19;20; RV64ZBA-LABEL: slliuw:21; RV64ZBA: # %bb.0:22; RV64ZBA-NEXT: slli.uw a0, a0, 123; RV64ZBA-NEXT: ret24;25; RV64XANDESPERF-LABEL: slliuw:26; RV64XANDESPERF: # %bb.0:27; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 1, 3228; RV64XANDESPERF-NEXT: ret29 %conv1 = shl i64 %a, 130 %shl = and i64 %conv1, 858993459031 ret i64 %shl32}33 34define i128 @slliuw_2(i32 signext %0, ptr %1) {35; RV64I-LABEL: slliuw_2:36; RV64I: # %bb.0:37; RV64I-NEXT: slli a0, a0, 3238; RV64I-NEXT: srli a0, a0, 2839; RV64I-NEXT: add a1, a1, a040; RV64I-NEXT: ld a0, 0(a1)41; RV64I-NEXT: ld a1, 8(a1)42; RV64I-NEXT: ret43;44; RV64ZBA-LABEL: slliuw_2:45; RV64ZBA: # %bb.0:46; RV64ZBA-NEXT: slli.uw a0, a0, 447; RV64ZBA-NEXT: add a1, a1, a048; RV64ZBA-NEXT: ld a0, 0(a1)49; RV64ZBA-NEXT: ld a1, 8(a1)50; RV64ZBA-NEXT: ret51;52; RV64XANDESPERF-LABEL: slliuw_2:53; RV64XANDESPERF: # %bb.0:54; RV64XANDESPERF-NEXT: slli a0, a0, 3255; RV64XANDESPERF-NEXT: srli a0, a0, 2856; RV64XANDESPERF-NEXT: add a1, a1, a057; RV64XANDESPERF-NEXT: ld a0, 0(a1)58; RV64XANDESPERF-NEXT: ld a1, 8(a1)59; RV64XANDESPERF-NEXT: ret60 %3 = zext i32 %0 to i6461 %4 = getelementptr inbounds i128, ptr %1, i64 %362 %5 = load i128, ptr %463 ret i128 %564}65 66define i64 @adduw(i64 %a, i64 %b) nounwind {67; RV64I-LABEL: adduw:68; RV64I: # %bb.0:69; RV64I-NEXT: slli a1, a1, 3270; RV64I-NEXT: srli a1, a1, 3271; RV64I-NEXT: add a0, a1, a072; RV64I-NEXT: ret73;74; RV64ZBA-LABEL: adduw:75; RV64ZBA: # %bb.0:76; RV64ZBA-NEXT: add.uw a0, a1, a077; RV64ZBA-NEXT: ret78;79; RV64XANDESPERF-LABEL: adduw:80; RV64XANDESPERF: # %bb.0:81; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a182; RV64XANDESPERF-NEXT: ret83 %and = and i64 %b, 429496729584 %add = add i64 %and, %a85 ret i64 %add86}87 88define signext i8 @adduw_2(i32 signext %0, ptr %1) {89; RV64I-LABEL: adduw_2:90; RV64I: # %bb.0:91; RV64I-NEXT: slli a0, a0, 3292; RV64I-NEXT: srli a0, a0, 3293; RV64I-NEXT: add a0, a1, a094; RV64I-NEXT: lb a0, 0(a0)95; RV64I-NEXT: ret96;97; RV64ZBA-LABEL: adduw_2:98; RV64ZBA: # %bb.0:99; RV64ZBA-NEXT: add.uw a0, a0, a1100; RV64ZBA-NEXT: lb a0, 0(a0)101; RV64ZBA-NEXT: ret102;103; RV64XANDESPERF-LABEL: adduw_2:104; RV64XANDESPERF: # %bb.0:105; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a0106; RV64XANDESPERF-NEXT: lb a0, 0(a0)107; RV64XANDESPERF-NEXT: ret108 %3 = zext i32 %0 to i64109 %4 = getelementptr inbounds i8, ptr %1, i64 %3110 %5 = load i8, ptr %4111 ret i8 %5112}113 114define i64 @zextw_i64(i64 %a) nounwind {115; RV64I-LABEL: zextw_i64:116; RV64I: # %bb.0:117; RV64I-NEXT: slli a0, a0, 32118; RV64I-NEXT: srli a0, a0, 32119; RV64I-NEXT: ret120;121; RV64ZBA-LABEL: zextw_i64:122; RV64ZBA: # %bb.0:123; RV64ZBA-NEXT: zext.w a0, a0124; RV64ZBA-NEXT: ret125;126; RV64XANDESPERF-LABEL: zextw_i64:127; RV64XANDESPERF: # %bb.0:128; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 31, 0129; RV64XANDESPERF-NEXT: ret130 %and = and i64 %a, 4294967295131 ret i64 %and132}133 134; This makes sure targetShrinkDemandedConstant changes the and immmediate to135; allow zext.w or slli+srli.136define i64 @zextw_demandedbits_i64(i64 %0) {137; RV64I-LABEL: zextw_demandedbits_i64:138; RV64I: # %bb.0:139; RV64I-NEXT: ori a0, a0, 1140; RV64I-NEXT: slli a0, a0, 32141; RV64I-NEXT: srli a0, a0, 32142; RV64I-NEXT: ret143;144; RV64ZBA-LABEL: zextw_demandedbits_i64:145; RV64ZBA: # %bb.0:146; RV64ZBA-NEXT: ori a0, a0, 1147; RV64ZBA-NEXT: zext.w a0, a0148; RV64ZBA-NEXT: ret149;150; RV64XANDESPERF-LABEL: zextw_demandedbits_i64:151; RV64XANDESPERF: # %bb.0:152; RV64XANDESPERF-NEXT: ori a0, a0, 1153; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 31, 0154; RV64XANDESPERF-NEXT: ret155 %2 = and i64 %0, 4294967294156 %3 = or i64 %2, 1157 ret i64 %3158}159 160define signext i16 @sh1add(i64 %0, ptr %1) {161; RV64I-LABEL: sh1add:162; RV64I: # %bb.0:163; RV64I-NEXT: slli a0, a0, 1164; RV64I-NEXT: add a0, a1, a0165; RV64I-NEXT: lh a0, 0(a0)166; RV64I-NEXT: ret167;168; RV64ZBA-LABEL: sh1add:169; RV64ZBA: # %bb.0:170; RV64ZBA-NEXT: sh1add a0, a0, a1171; RV64ZBA-NEXT: lh a0, 0(a0)172; RV64ZBA-NEXT: ret173;174; RV64XANDESPERF-LABEL: sh1add:175; RV64XANDESPERF: # %bb.0:176; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0177; RV64XANDESPERF-NEXT: lh a0, 0(a0)178; RV64XANDESPERF-NEXT: ret179 %3 = getelementptr inbounds i16, ptr %1, i64 %0180 %4 = load i16, ptr %3181 ret i16 %4182}183 184define signext i32 @sh2add(i64 %0, ptr %1) {185; RV64I-LABEL: sh2add:186; RV64I: # %bb.0:187; RV64I-NEXT: slli a0, a0, 2188; RV64I-NEXT: add a0, a1, a0189; RV64I-NEXT: lw a0, 0(a0)190; RV64I-NEXT: ret191;192; RV64ZBA-LABEL: sh2add:193; RV64ZBA: # %bb.0:194; RV64ZBA-NEXT: sh2add a0, a0, a1195; RV64ZBA-NEXT: lw a0, 0(a0)196; RV64ZBA-NEXT: ret197;198; RV64XANDESPERF-LABEL: sh2add:199; RV64XANDESPERF: # %bb.0:200; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a0201; RV64XANDESPERF-NEXT: lw a0, 0(a0)202; RV64XANDESPERF-NEXT: ret203 %3 = getelementptr inbounds i32, ptr %1, i64 %0204 %4 = load i32, ptr %3205 ret i32 %4206}207 208define i64 @sh3add(i64 %0, ptr %1) {209; RV64I-LABEL: sh3add:210; RV64I: # %bb.0:211; RV64I-NEXT: slli a0, a0, 3212; RV64I-NEXT: add a0, a1, a0213; RV64I-NEXT: ld a0, 0(a0)214; RV64I-NEXT: ret215;216; RV64ZBA-LABEL: sh3add:217; RV64ZBA: # %bb.0:218; RV64ZBA-NEXT: sh3add a0, a0, a1219; RV64ZBA-NEXT: ld a0, 0(a0)220; RV64ZBA-NEXT: ret221;222; RV64XANDESPERF-LABEL: sh3add:223; RV64XANDESPERF: # %bb.0:224; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a0225; RV64XANDESPERF-NEXT: ld a0, 0(a0)226; RV64XANDESPERF-NEXT: ret227 %3 = getelementptr inbounds i64, ptr %1, i64 %0228 %4 = load i64, ptr %3229 ret i64 %4230}231 232define signext i16 @sh1adduw(i32 signext %0, ptr %1) {233; RV64I-LABEL: sh1adduw:234; RV64I: # %bb.0:235; RV64I-NEXT: slli a0, a0, 32236; RV64I-NEXT: srli a0, a0, 31237; RV64I-NEXT: add a0, a1, a0238; RV64I-NEXT: lh a0, 0(a0)239; RV64I-NEXT: ret240;241; RV64ZBA-LABEL: sh1adduw:242; RV64ZBA: # %bb.0:243; RV64ZBA-NEXT: sh1add.uw a0, a0, a1244; RV64ZBA-NEXT: lh a0, 0(a0)245; RV64ZBA-NEXT: ret246;247; RV64XANDESPERF-LABEL: sh1adduw:248; RV64XANDESPERF: # %bb.0:249; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a1, a0250; RV64XANDESPERF-NEXT: lh a0, 0(a0)251; RV64XANDESPERF-NEXT: ret252 %3 = zext i32 %0 to i64253 %4 = getelementptr inbounds i16, ptr %1, i64 %3254 %5 = load i16, ptr %4255 ret i16 %5256}257 258define i64 @sh1adduw_2(i64 %0, i64 %1) {259; RV64I-LABEL: sh1adduw_2:260; RV64I: # %bb.0:261; RV64I-NEXT: slli a0, a0, 32262; RV64I-NEXT: srli a0, a0, 31263; RV64I-NEXT: add a0, a0, a1264; RV64I-NEXT: ret265;266; RV64ZBA-LABEL: sh1adduw_2:267; RV64ZBA: # %bb.0:268; RV64ZBA-NEXT: sh1add.uw a0, a0, a1269; RV64ZBA-NEXT: ret270;271; RV64XANDESPERF-LABEL: sh1adduw_2:272; RV64XANDESPERF: # %bb.0:273; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a1, a0274; RV64XANDESPERF-NEXT: ret275 %3 = shl i64 %0, 1276 %4 = and i64 %3, 8589934590277 %5 = add i64 %4, %1278 ret i64 %5279}280 281define i64 @sh1adduw_3(i64 %0, i64 %1) {282; RV64I-LABEL: sh1adduw_3:283; RV64I: # %bb.0:284; RV64I-NEXT: slli a0, a0, 32285; RV64I-NEXT: srli a0, a0, 31286; RV64I-NEXT: or a0, a0, a1287; RV64I-NEXT: ret288;289; RV64ZBA-LABEL: sh1adduw_3:290; RV64ZBA: # %bb.0:291; RV64ZBA-NEXT: sh1add.uw a0, a0, a1292; RV64ZBA-NEXT: ret293;294; RV64XANDESPERF-LABEL: sh1adduw_3:295; RV64XANDESPERF: # %bb.0:296; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a1, a0297; RV64XANDESPERF-NEXT: ret298 %3 = shl i64 %0, 1299 %4 = and i64 %3, 8589934590300 %5 = or disjoint i64 %4, %1301 ret i64 %5302}303 304define signext i32 @sh2adduw(i32 signext %0, ptr %1) {305; RV64I-LABEL: sh2adduw:306; RV64I: # %bb.0:307; RV64I-NEXT: slli a0, a0, 32308; RV64I-NEXT: srli a0, a0, 30309; RV64I-NEXT: add a0, a1, a0310; RV64I-NEXT: lw a0, 0(a0)311; RV64I-NEXT: ret312;313; RV64ZBA-LABEL: sh2adduw:314; RV64ZBA: # %bb.0:315; RV64ZBA-NEXT: sh2add.uw a0, a0, a1316; RV64ZBA-NEXT: lw a0, 0(a0)317; RV64ZBA-NEXT: ret318;319; RV64XANDESPERF-LABEL: sh2adduw:320; RV64XANDESPERF: # %bb.0:321; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a1, a0322; RV64XANDESPERF-NEXT: lw a0, 0(a0)323; RV64XANDESPERF-NEXT: ret324 %3 = zext i32 %0 to i64325 %4 = getelementptr inbounds i32, ptr %1, i64 %3326 %5 = load i32, ptr %4327 ret i32 %5328}329 330define i64 @sh2adduw_2(i64 %0, i64 %1) {331; RV64I-LABEL: sh2adduw_2:332; RV64I: # %bb.0:333; RV64I-NEXT: slli a0, a0, 32334; RV64I-NEXT: srli a0, a0, 30335; RV64I-NEXT: add a0, a0, a1336; RV64I-NEXT: ret337;338; RV64ZBA-LABEL: sh2adduw_2:339; RV64ZBA: # %bb.0:340; RV64ZBA-NEXT: sh2add.uw a0, a0, a1341; RV64ZBA-NEXT: ret342;343; RV64XANDESPERF-LABEL: sh2adduw_2:344; RV64XANDESPERF: # %bb.0:345; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a1, a0346; RV64XANDESPERF-NEXT: ret347 %3 = shl i64 %0, 2348 %4 = and i64 %3, 17179869180349 %5 = add i64 %4, %1350 ret i64 %5351}352 353define i64 @sh2adduw_3(i64 %0, i64 %1) {354; RV64I-LABEL: sh2adduw_3:355; RV64I: # %bb.0:356; RV64I-NEXT: slli a0, a0, 32357; RV64I-NEXT: srli a0, a0, 30358; RV64I-NEXT: or a0, a0, a1359; RV64I-NEXT: ret360;361; RV64ZBA-LABEL: sh2adduw_3:362; RV64ZBA: # %bb.0:363; RV64ZBA-NEXT: sh2add.uw a0, a0, a1364; RV64ZBA-NEXT: ret365;366; RV64XANDESPERF-LABEL: sh2adduw_3:367; RV64XANDESPERF: # %bb.0:368; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a1, a0369; RV64XANDESPERF-NEXT: ret370 %3 = shl i64 %0, 2371 %4 = and i64 %3, 17179869180372 %5 = or disjoint i64 %4, %1373 ret i64 %5374}375 376define i64 @sh3adduw(i32 signext %0, ptr %1) {377; RV64I-LABEL: sh3adduw:378; RV64I: # %bb.0:379; RV64I-NEXT: slli a0, a0, 32380; RV64I-NEXT: srli a0, a0, 29381; RV64I-NEXT: add a0, a1, a0382; RV64I-NEXT: ld a0, 0(a0)383; RV64I-NEXT: ret384;385; RV64ZBA-LABEL: sh3adduw:386; RV64ZBA: # %bb.0:387; RV64ZBA-NEXT: sh3add.uw a0, a0, a1388; RV64ZBA-NEXT: ld a0, 0(a0)389; RV64ZBA-NEXT: ret390;391; RV64XANDESPERF-LABEL: sh3adduw:392; RV64XANDESPERF: # %bb.0:393; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a0394; RV64XANDESPERF-NEXT: ld a0, 0(a0)395; RV64XANDESPERF-NEXT: ret396 %3 = zext i32 %0 to i64397 %4 = getelementptr inbounds i64, ptr %1, i64 %3398 %5 = load i64, ptr %4399 ret i64 %5400}401 402define i64 @sh3adduw_2(i64 %0, i64 %1) {403; RV64I-LABEL: sh3adduw_2:404; RV64I: # %bb.0:405; RV64I-NEXT: slli a0, a0, 32406; RV64I-NEXT: srli a0, a0, 29407; RV64I-NEXT: add a0, a0, a1408; RV64I-NEXT: ret409;410; RV64ZBA-LABEL: sh3adduw_2:411; RV64ZBA: # %bb.0:412; RV64ZBA-NEXT: sh3add.uw a0, a0, a1413; RV64ZBA-NEXT: ret414;415; RV64XANDESPERF-LABEL: sh3adduw_2:416; RV64XANDESPERF: # %bb.0:417; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a0418; RV64XANDESPERF-NEXT: ret419 %3 = shl i64 %0, 3420 %4 = and i64 %3, 34359738360421 %5 = add i64 %4, %1422 ret i64 %5423}424 425define i64 @sh3adduw_3(i64 %0, i64 %1) {426; RV64I-LABEL: sh3adduw_3:427; RV64I: # %bb.0:428; RV64I-NEXT: slli a0, a0, 32429; RV64I-NEXT: srli a0, a0, 29430; RV64I-NEXT: or a0, a0, a1431; RV64I-NEXT: ret432;433; RV64ZBA-LABEL: sh3adduw_3:434; RV64ZBA: # %bb.0:435; RV64ZBA-NEXT: sh3add.uw a0, a0, a1436; RV64ZBA-NEXT: ret437;438; RV64XANDESPERF-LABEL: sh3adduw_3:439; RV64XANDESPERF: # %bb.0:440; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a0441; RV64XANDESPERF-NEXT: ret442 %3 = shl i64 %0, 3443 %4 = and i64 %3, 34359738360444 %5 = or disjoint i64 %4, %1445 ret i64 %5446}447 448; Type legalization inserts a sext_inreg after the first add. That add will be449; selected as sh2add which does not sign extend. SimplifyDemandedBits is unable450; to remove the sext_inreg because it has multiple uses. The ashr will use the451; sext_inreg to become sraiw. This leaves the sext_inreg only used by the shl.452; If the shl is selected as sllw, we don't need the sext_inreg.453define i64 @sh2add_extra_sext(i32 %x, i32 %y, i32 %z) {454; RV64I-LABEL: sh2add_extra_sext:455; RV64I: # %bb.0:456; RV64I-NEXT: slli a0, a0, 2457; RV64I-NEXT: add a0, a0, a1458; RV64I-NEXT: sllw a1, a2, a0459; RV64I-NEXT: sraiw a0, a0, 2460; RV64I-NEXT: mul a0, a1, a0461; RV64I-NEXT: ret462;463; RV64ZBA-LABEL: sh2add_extra_sext:464; RV64ZBA: # %bb.0:465; RV64ZBA-NEXT: sh2add a0, a0, a1466; RV64ZBA-NEXT: sllw a1, a2, a0467; RV64ZBA-NEXT: sraiw a0, a0, 2468; RV64ZBA-NEXT: mul a0, a1, a0469; RV64ZBA-NEXT: ret470;471; RV64XANDESPERF-LABEL: sh2add_extra_sext:472; RV64XANDESPERF: # %bb.0:473; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a0474; RV64XANDESPERF-NEXT: sllw a1, a2, a0475; RV64XANDESPERF-NEXT: sraiw a0, a0, 2476; RV64XANDESPERF-NEXT: mul a0, a1, a0477; RV64XANDESPERF-NEXT: ret478 %a = shl i32 %x, 2479 %b = add i32 %a, %y480 %c = shl i32 %z, %b481 %d = ashr i32 %b, 2482 %e = sext i32 %c to i64483 %f = sext i32 %d to i64484 %g = mul i64 %e, %f485 ret i64 %g486}487 488define i64 @addmul6(i64 %a, i64 %b) {489; RV64I-LABEL: addmul6:490; RV64I: # %bb.0:491; RV64I-NEXT: slli a2, a0, 1492; RV64I-NEXT: slli a0, a0, 2493; RV64I-NEXT: add a0, a0, a2494; RV64I-NEXT: add a0, a0, a1495; RV64I-NEXT: ret496;497; RV64ZBA-LABEL: addmul6:498; RV64ZBA: # %bb.0:499; RV64ZBA-NEXT: sh1add a0, a0, a0500; RV64ZBA-NEXT: sh1add a0, a0, a1501; RV64ZBA-NEXT: ret502;503; RV64XANDESPERF-LABEL: addmul6:504; RV64XANDESPERF: # %bb.0:505; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a0506; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0507; RV64XANDESPERF-NEXT: ret508 %c = mul i64 %a, 6509 %d = add i64 %c, %b510 ret i64 %d511}512 513define i64 @disjointormul6(i64 %a, i64 %b) {514; RV64I-LABEL: disjointormul6:515; RV64I: # %bb.0:516; RV64I-NEXT: slli a2, a0, 1517; RV64I-NEXT: slli a0, a0, 2518; RV64I-NEXT: add a0, a0, a2519; RV64I-NEXT: or a0, a0, a1520; RV64I-NEXT: ret521;522; RV64ZBA-LABEL: disjointormul6:523; RV64ZBA: # %bb.0:524; RV64ZBA-NEXT: sh1add a0, a0, a0525; RV64ZBA-NEXT: sh1add a0, a0, a1526; RV64ZBA-NEXT: ret527;528; RV64XANDESPERF-LABEL: disjointormul6:529; RV64XANDESPERF: # %bb.0:530; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a0531; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0532; RV64XANDESPERF-NEXT: ret533 %c = mul i64 %a, 6534 %d = or disjoint i64 %c, %b535 ret i64 %d536}537 538define i64 @addmul10(i64 %a, i64 %b) {539; RV64I-LABEL: addmul10:540; RV64I: # %bb.0:541; RV64I-NEXT: slli a2, a0, 1542; RV64I-NEXT: slli a0, a0, 3543; RV64I-NEXT: add a0, a0, a2544; RV64I-NEXT: add a0, a0, a1545; RV64I-NEXT: ret546;547; RV64ZBA-LABEL: addmul10:548; RV64ZBA: # %bb.0:549; RV64ZBA-NEXT: sh2add a0, a0, a0550; RV64ZBA-NEXT: sh1add a0, a0, a1551; RV64ZBA-NEXT: ret552;553; RV64XANDESPERF-LABEL: addmul10:554; RV64XANDESPERF: # %bb.0:555; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a0556; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0557; RV64XANDESPERF-NEXT: ret558 %c = mul i64 %a, 10559 %d = add i64 %c, %b560 ret i64 %d561}562 563define i64 @addmul12(i64 %a, i64 %b) {564; RV64I-LABEL: addmul12:565; RV64I: # %bb.0:566; RV64I-NEXT: slli a2, a0, 2567; RV64I-NEXT: slli a0, a0, 3568; RV64I-NEXT: add a0, a0, a2569; RV64I-NEXT: add a0, a0, a1570; RV64I-NEXT: ret571;572; RV64ZBA-LABEL: addmul12:573; RV64ZBA: # %bb.0:574; RV64ZBA-NEXT: sh1add a0, a0, a0575; RV64ZBA-NEXT: sh2add a0, a0, a1576; RV64ZBA-NEXT: ret577;578; RV64XANDESPERF-LABEL: addmul12:579; RV64XANDESPERF: # %bb.0:580; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a0581; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a0582; RV64XANDESPERF-NEXT: ret583 %c = mul i64 %a, 12584 %d = add i64 %c, %b585 ret i64 %d586}587 588define i64 @addmul14(i64 %a, i64 %b) {589; RV64I-LABEL: addmul14:590; RV64I: # %bb.0:591; RV64I-NEXT: slli a2, a0, 1592; RV64I-NEXT: slli a0, a0, 4593; RV64I-NEXT: sub a0, a0, a2594; RV64I-NEXT: add a0, a0, a1595; RV64I-NEXT: ret596;597; RV64ZBA-LABEL: addmul14:598; RV64ZBA: # %bb.0:599; RV64ZBA-NEXT: sh1add a2, a0, a0600; RV64ZBA-NEXT: sh1add a0, a2, a0601; RV64ZBA-NEXT: sh1add a0, a0, a1602; RV64ZBA-NEXT: ret603;604; RV64XANDESPERF-LABEL: addmul14:605; RV64XANDESPERF: # %bb.0:606; RV64XANDESPERF-NEXT: nds.lea.h a2, a0, a0607; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a2608; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0609; RV64XANDESPERF-NEXT: ret610 %c = mul i64 %a, 14611 %d = add i64 %c, %b612 ret i64 %d613}614 615define i64 @addmul18(i64 %a, i64 %b) {616; RV64I-LABEL: addmul18:617; RV64I: # %bb.0:618; RV64I-NEXT: slli a2, a0, 1619; RV64I-NEXT: slli a0, a0, 4620; RV64I-NEXT: add a0, a0, a2621; RV64I-NEXT: add a0, a0, a1622; RV64I-NEXT: ret623;624; RV64ZBA-LABEL: addmul18:625; RV64ZBA: # %bb.0:626; RV64ZBA-NEXT: sh3add a0, a0, a0627; RV64ZBA-NEXT: sh1add a0, a0, a1628; RV64ZBA-NEXT: ret629;630; RV64XANDESPERF-LABEL: addmul18:631; RV64XANDESPERF: # %bb.0:632; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a0633; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0634; RV64XANDESPERF-NEXT: ret635 %c = mul i64 %a, 18636 %d = add i64 %c, %b637 ret i64 %d638}639 640define i64 @addmul20(i64 %a, i64 %b) {641; RV64I-LABEL: addmul20:642; RV64I: # %bb.0:643; RV64I-NEXT: slli a2, a0, 2644; RV64I-NEXT: slli a0, a0, 4645; RV64I-NEXT: add a0, a0, a2646; RV64I-NEXT: add a0, a0, a1647; RV64I-NEXT: ret648;649; RV64ZBA-LABEL: addmul20:650; RV64ZBA: # %bb.0:651; RV64ZBA-NEXT: sh2add a0, a0, a0652; RV64ZBA-NEXT: sh2add a0, a0, a1653; RV64ZBA-NEXT: ret654;655; RV64XANDESPERF-LABEL: addmul20:656; RV64XANDESPERF: # %bb.0:657; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a0658; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a0659; RV64XANDESPERF-NEXT: ret660 %c = mul i64 %a, 20661 %d = add i64 %c, %b662 ret i64 %d663}664 665define i64 @addmul22(i64 %a, i64 %b) {666; RV64I-LABEL: addmul22:667; RV64I: # %bb.0:668; RV64I-NEXT: li a2, 22669; RV64I-NEXT: mul a0, a0, a2670; RV64I-NEXT: add a0, a0, a1671; RV64I-NEXT: ret672;673; RV64ZBA-LABEL: addmul22:674; RV64ZBA: # %bb.0:675; RV64ZBA-NEXT: sh2add a2, a0, a0676; RV64ZBA-NEXT: sh1add a0, a2, a0677; RV64ZBA-NEXT: sh1add a0, a0, a1678; RV64ZBA-NEXT: ret679;680; RV64XANDESPERF-LABEL: addmul22:681; RV64XANDESPERF: # %bb.0:682; RV64XANDESPERF-NEXT: nds.lea.w a2, a0, a0683; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a2684; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0685; RV64XANDESPERF-NEXT: ret686 %c = mul i64 %a, 22687 %d = add i64 %c, %b688 ret i64 %d689}690 691define i64 @addmul24(i64 %a, i64 %b) {692; RV64I-LABEL: addmul24:693; RV64I: # %bb.0:694; RV64I-NEXT: slli a2, a0, 3695; RV64I-NEXT: slli a0, a0, 4696; RV64I-NEXT: add a0, a0, a2697; RV64I-NEXT: add a0, a0, a1698; RV64I-NEXT: ret699;700; RV64ZBA-LABEL: addmul24:701; RV64ZBA: # %bb.0:702; RV64ZBA-NEXT: sh1add a0, a0, a0703; RV64ZBA-NEXT: sh3add a0, a0, a1704; RV64ZBA-NEXT: ret705;706; RV64XANDESPERF-LABEL: addmul24:707; RV64XANDESPERF: # %bb.0:708; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a0709; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a0710; RV64XANDESPERF-NEXT: ret711 %c = mul i64 %a, 24712 %d = add i64 %c, %b713 ret i64 %d714}715 716define i64 @addmul26(i64 %a, i64 %b) {717; RV64I-LABEL: addmul26:718; RV64I: # %bb.0:719; RV64I-NEXT: li a2, 26720; RV64I-NEXT: mul a0, a0, a2721; RV64I-NEXT: add a0, a0, a1722; RV64I-NEXT: ret723;724; RV64ZBA-LABEL: addmul26:725; RV64ZBA: # %bb.0:726; RV64ZBA-NEXT: sh1add a2, a0, a0727; RV64ZBA-NEXT: sh2add a0, a2, a0728; RV64ZBA-NEXT: sh1add a0, a0, a1729; RV64ZBA-NEXT: ret730;731; RV64XANDESPERF-LABEL: addmul26:732; RV64XANDESPERF: # %bb.0:733; RV64XANDESPERF-NEXT: nds.lea.h a2, a0, a0734; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a2735; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0736; RV64XANDESPERF-NEXT: ret737 %c = mul i64 %a, 26738 %d = add i64 %c, %b739 ret i64 %d740}741 742define i64 @addmul36(i64 %a, i64 %b) {743; RV64I-LABEL: addmul36:744; RV64I: # %bb.0:745; RV64I-NEXT: slli a2, a0, 2746; RV64I-NEXT: slli a0, a0, 5747; RV64I-NEXT: add a0, a0, a2748; RV64I-NEXT: add a0, a0, a1749; RV64I-NEXT: ret750;751; RV64ZBA-LABEL: addmul36:752; RV64ZBA: # %bb.0:753; RV64ZBA-NEXT: sh3add a0, a0, a0754; RV64ZBA-NEXT: sh2add a0, a0, a1755; RV64ZBA-NEXT: ret756;757; RV64XANDESPERF-LABEL: addmul36:758; RV64XANDESPERF: # %bb.0:759; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a0760; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a0761; RV64XANDESPERF-NEXT: ret762 %c = mul i64 %a, 36763 %d = add i64 %c, %b764 ret i64 %d765}766 767define i64 @addmul40(i64 %a, i64 %b) {768; RV64I-LABEL: addmul40:769; RV64I: # %bb.0:770; RV64I-NEXT: slli a2, a0, 3771; RV64I-NEXT: slli a0, a0, 5772; RV64I-NEXT: add a0, a0, a2773; RV64I-NEXT: add a0, a0, a1774; RV64I-NEXT: ret775;776; RV64ZBA-LABEL: addmul40:777; RV64ZBA: # %bb.0:778; RV64ZBA-NEXT: sh2add a0, a0, a0779; RV64ZBA-NEXT: sh3add a0, a0, a1780; RV64ZBA-NEXT: ret781;782; RV64XANDESPERF-LABEL: addmul40:783; RV64XANDESPERF: # %bb.0:784; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a0785; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a0786; RV64XANDESPERF-NEXT: ret787 %c = mul i64 %a, 40788 %d = add i64 %c, %b789 ret i64 %d790}791 792define i64 @addmul38(i64 %a, i64 %b) {793; RV64I-LABEL: addmul38:794; RV64I: # %bb.0:795; RV64I-NEXT: li a2, 38796; RV64I-NEXT: mul a0, a0, a2797; RV64I-NEXT: add a0, a0, a1798; RV64I-NEXT: ret799;800; RV64ZBA-LABEL: addmul38:801; RV64ZBA: # %bb.0:802; RV64ZBA-NEXT: sh3add a2, a0, a0803; RV64ZBA-NEXT: sh1add a0, a2, a0804; RV64ZBA-NEXT: sh1add a0, a0, a1805; RV64ZBA-NEXT: ret806;807; RV64XANDESPERF-LABEL: addmul38:808; RV64XANDESPERF: # %bb.0:809; RV64XANDESPERF-NEXT: nds.lea.d a2, a0, a0810; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a2811; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0812; RV64XANDESPERF-NEXT: ret813 %c = mul i64 %a, 38814 %d = add i64 %c, %b815 ret i64 %d816}817 818define i64 @addmul42(i64 %a, i64 %b) {819; RV64I-LABEL: addmul42:820; RV64I: # %bb.0:821; RV64I-NEXT: li a2, 42822; RV64I-NEXT: mul a0, a0, a2823; RV64I-NEXT: add a0, a0, a1824; RV64I-NEXT: ret825;826; RV64ZBA-LABEL: addmul42:827; RV64ZBA: # %bb.0:828; RV64ZBA-NEXT: sh2add a2, a0, a0829; RV64ZBA-NEXT: sh2add a0, a2, a0830; RV64ZBA-NEXT: sh1add a0, a0, a1831; RV64ZBA-NEXT: ret832;833; RV64XANDESPERF-LABEL: addmul42:834; RV64XANDESPERF: # %bb.0:835; RV64XANDESPERF-NEXT: nds.lea.w a2, a0, a0836; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a2837; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0838; RV64XANDESPERF-NEXT: ret839 %c = mul i64 %a, 42840 %d = add i64 %c, %b841 ret i64 %d842}843 844define i64 @addmul72(i64 %a, i64 %b) {845; RV64I-LABEL: addmul72:846; RV64I: # %bb.0:847; RV64I-NEXT: slli a2, a0, 3848; RV64I-NEXT: slli a0, a0, 6849; RV64I-NEXT: add a0, a0, a2850; RV64I-NEXT: add a0, a0, a1851; RV64I-NEXT: ret852;853; RV64ZBA-LABEL: addmul72:854; RV64ZBA: # %bb.0:855; RV64ZBA-NEXT: sh3add a0, a0, a0856; RV64ZBA-NEXT: sh3add a0, a0, a1857; RV64ZBA-NEXT: ret858;859; RV64XANDESPERF-LABEL: addmul72:860; RV64XANDESPERF: # %bb.0:861; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a0862; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a0863; RV64XANDESPERF-NEXT: ret864 %c = mul i64 %a, 72865 %d = add i64 %c, %b866 ret i64 %d867}868 869define i64 @addmul74(i64 %a, i64 %b) {870; RV64I-LABEL: addmul74:871; RV64I: # %bb.0:872; RV64I-NEXT: li a2, 74873; RV64I-NEXT: mul a0, a0, a2874; RV64I-NEXT: add a0, a0, a1875; RV64I-NEXT: ret876;877; RV64ZBA-LABEL: addmul74:878; RV64ZBA: # %bb.0:879; RV64ZBA-NEXT: sh3add a2, a0, a0880; RV64ZBA-NEXT: sh2add a0, a2, a0881; RV64ZBA-NEXT: sh1add a0, a0, a1882; RV64ZBA-NEXT: ret883;884; RV64XANDESPERF-LABEL: addmul74:885; RV64XANDESPERF: # %bb.0:886; RV64XANDESPERF-NEXT: nds.lea.d a2, a0, a0887; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a2888; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0889; RV64XANDESPERF-NEXT: ret890 %c = mul i64 %a, 74891 %d = add i64 %c, %b892 ret i64 %d893}894 895define i64 @addmul82(i64 %a, i64 %b) {896; RV64I-LABEL: addmul82:897; RV64I: # %bb.0:898; RV64I-NEXT: li a2, 82899; RV64I-NEXT: mul a0, a0, a2900; RV64I-NEXT: add a0, a0, a1901; RV64I-NEXT: ret902;903; RV64ZBA-LABEL: addmul82:904; RV64ZBA: # %bb.0:905; RV64ZBA-NEXT: sh2add a2, a0, a0906; RV64ZBA-NEXT: sh3add a0, a2, a0907; RV64ZBA-NEXT: sh1add a0, a0, a1908; RV64ZBA-NEXT: ret909;910; RV64XANDESPERF-LABEL: addmul82:911; RV64XANDESPERF: # %bb.0:912; RV64XANDESPERF-NEXT: nds.lea.w a2, a0, a0913; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a2914; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0915; RV64XANDESPERF-NEXT: ret916 %c = mul i64 %a, 82917 %d = add i64 %c, %b918 ret i64 %d919}920 921define i64 @addmul146(i64 %a, i64 %b) {922; RV64I-LABEL: addmul146:923; RV64I: # %bb.0:924; RV64I-NEXT: li a2, 146925; RV64I-NEXT: mul a0, a0, a2926; RV64I-NEXT: add a0, a0, a1927; RV64I-NEXT: ret928;929; RV64ZBA-LABEL: addmul146:930; RV64ZBA: # %bb.0:931; RV64ZBA-NEXT: sh3add a2, a0, a0932; RV64ZBA-NEXT: sh3add a0, a2, a0933; RV64ZBA-NEXT: sh1add a0, a0, a1934; RV64ZBA-NEXT: ret935;936; RV64XANDESPERF-LABEL: addmul146:937; RV64XANDESPERF: # %bb.0:938; RV64XANDESPERF-NEXT: nds.lea.d a2, a0, a0939; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a2940; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a0941; RV64XANDESPERF-NEXT: ret942 %c = mul i64 %a, 146943 %d = add i64 %c, %b944 ret i64 %d945}946 947define i64 @mul49(i64 %a) {948; RV64I-LABEL: mul49:949; RV64I: # %bb.0:950; RV64I-NEXT: li a1, 49951; RV64I-NEXT: mul a0, a0, a1952; RV64I-NEXT: ret953;954; RV64ZBA-LABEL: mul49:955; RV64ZBA: # %bb.0:956; RV64ZBA-NEXT: slli a1, a0, 4957; RV64ZBA-NEXT: sh1add a1, a1, a1958; RV64ZBA-NEXT: add a0, a1, a0959; RV64ZBA-NEXT: ret960;961; RV64XANDESPERF-LABEL: mul49:962; RV64XANDESPERF: # %bb.0:963; RV64XANDESPERF-NEXT: slli a1, a0, 4964; RV64XANDESPERF-NEXT: nds.lea.h a1, a1, a1965; RV64XANDESPERF-NEXT: add a0, a1, a0966; RV64XANDESPERF-NEXT: ret967 %c = mul i64 %a, 49968 ret i64 %c969}970 971define i64 @zext_mul49(i32 signext %a) {972; RV64I-LABEL: zext_mul49:973; RV64I: # %bb.0:974; RV64I-NEXT: li a1, 49975; RV64I-NEXT: slli a1, a1, 32976; RV64I-NEXT: slli a0, a0, 32977; RV64I-NEXT: mulhu a0, a0, a1978; RV64I-NEXT: ret979;980; RV64ZBA-LABEL: zext_mul49:981; RV64ZBA: # %bb.0:982; RV64ZBA-NEXT: slli.uw a1, a0, 4983; RV64ZBA-NEXT: sh1add a1, a1, a1984; RV64ZBA-NEXT: add.uw a0, a0, a1985; RV64ZBA-NEXT: ret986;987; RV64XANDESPERF-LABEL: zext_mul49:988; RV64XANDESPERF: # %bb.0:989; RV64XANDESPERF-NEXT: slli a1, a0, 32990; RV64XANDESPERF-NEXT: srli a1, a1, 28991; RV64XANDESPERF-NEXT: nds.lea.h a1, a1, a1992; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a0993; RV64XANDESPERF-NEXT: ret994 %b = zext i32 %a to i64995 %c = mul i64 %b, 49996 ret i64 %c997}998 999define i64 @mul50(i64 %a) {1000; RV64I-LABEL: mul50:1001; RV64I: # %bb.0:1002; RV64I-NEXT: li a1, 501003; RV64I-NEXT: mul a0, a0, a11004; RV64I-NEXT: ret1005;1006; RV64ZBA-LABEL: mul50:1007; RV64ZBA: # %bb.0:1008; RV64ZBA-NEXT: sh2add a0, a0, a01009; RV64ZBA-NEXT: sh2add a0, a0, a01010; RV64ZBA-NEXT: slli a0, a0, 11011; RV64ZBA-NEXT: ret1012;1013; RV64XANDESPERF-LABEL: mul50:1014; RV64XANDESPERF: # %bb.0:1015; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01016; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01017; RV64XANDESPERF-NEXT: slli a0, a0, 11018; RV64XANDESPERF-NEXT: ret1019 %c = mul i64 %a, 501020 ret i64 %c1021}1022 1023define i64 @addmul50(i64 %a, i64 %b) {1024; RV64I-LABEL: addmul50:1025; RV64I: # %bb.0:1026; RV64I-NEXT: li a2, 501027; RV64I-NEXT: mul a0, a0, a21028; RV64I-NEXT: add a0, a0, a11029; RV64I-NEXT: ret1030;1031; RV64ZBA-LABEL: addmul50:1032; RV64ZBA: # %bb.0:1033; RV64ZBA-NEXT: sh2add a0, a0, a01034; RV64ZBA-NEXT: sh2add a0, a0, a01035; RV64ZBA-NEXT: sh1add a0, a0, a11036; RV64ZBA-NEXT: ret1037;1038; RV64XANDESPERF-LABEL: addmul50:1039; RV64XANDESPERF: # %bb.0:1040; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01041; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01042; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a01043; RV64XANDESPERF-NEXT: ret1044 %c = mul i64 %a, 501045 %d = add i64 %c, %b1046 ret i64 %d1047}1048 1049define i64 @mul100(i64 %a) {1050; RV64I-LABEL: mul100:1051; RV64I: # %bb.0:1052; RV64I-NEXT: li a1, 1001053; RV64I-NEXT: mul a0, a0, a11054; RV64I-NEXT: ret1055;1056; RV64ZBA-LABEL: mul100:1057; RV64ZBA: # %bb.0:1058; RV64ZBA-NEXT: sh2add a0, a0, a01059; RV64ZBA-NEXT: sh2add a0, a0, a01060; RV64ZBA-NEXT: slli a0, a0, 21061; RV64ZBA-NEXT: ret1062;1063; RV64XANDESPERF-LABEL: mul100:1064; RV64XANDESPERF: # %bb.0:1065; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01066; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01067; RV64XANDESPERF-NEXT: slli a0, a0, 21068; RV64XANDESPERF-NEXT: ret1069 %c = mul i64 %a, 1001070 ret i64 %c1071}1072 1073define i64 @addmul100(i64 %a, i64 %b) {1074; RV64I-LABEL: addmul100:1075; RV64I: # %bb.0:1076; RV64I-NEXT: li a2, 1001077; RV64I-NEXT: mul a0, a0, a21078; RV64I-NEXT: add a0, a0, a11079; RV64I-NEXT: ret1080;1081; RV64ZBA-LABEL: addmul100:1082; RV64ZBA: # %bb.0:1083; RV64ZBA-NEXT: sh2add a0, a0, a01084; RV64ZBA-NEXT: sh2add a0, a0, a01085; RV64ZBA-NEXT: sh2add a0, a0, a11086; RV64ZBA-NEXT: ret1087;1088; RV64XANDESPERF-LABEL: addmul100:1089; RV64XANDESPERF: # %bb.0:1090; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01091; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01092; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a01093; RV64XANDESPERF-NEXT: ret1094 %c = mul i64 %a, 1001095 %d = add i64 %c, %b1096 ret i64 %d1097}1098 1099define i64 @mul145(i64 %a) {1100; RV64I-LABEL: mul145:1101; RV64I: # %bb.0:1102; RV64I-NEXT: li a1, 1451103; RV64I-NEXT: mul a0, a0, a11104; RV64I-NEXT: ret1105;1106; RV64ZBA-LABEL: mul145:1107; RV64ZBA: # %bb.0:1108; RV64ZBA-NEXT: slli a1, a0, 41109; RV64ZBA-NEXT: sh3add a1, a1, a11110; RV64ZBA-NEXT: add a0, a1, a01111; RV64ZBA-NEXT: ret1112;1113; RV64XANDESPERF-LABEL: mul145:1114; RV64XANDESPERF: # %bb.0:1115; RV64XANDESPERF-NEXT: slli a1, a0, 41116; RV64XANDESPERF-NEXT: nds.lea.d a1, a1, a11117; RV64XANDESPERF-NEXT: add a0, a1, a01118; RV64XANDESPERF-NEXT: ret1119 %c = mul i64 %a, 1451120 ret i64 %c1121}1122 1123define i64 @mul161(i64 %a) {1124; RV64I-LABEL: mul161:1125; RV64I: # %bb.0:1126; RV64I-NEXT: li a1, 1611127; RV64I-NEXT: mul a0, a0, a11128; RV64I-NEXT: ret1129;1130; RV64ZBA-LABEL: mul161:1131; RV64ZBA: # %bb.0:1132; RV64ZBA-NEXT: slli a1, a0, 51133; RV64ZBA-NEXT: sh2add a1, a1, a11134; RV64ZBA-NEXT: add a0, a1, a01135; RV64ZBA-NEXT: ret1136;1137; RV64XANDESPERF-LABEL: mul161:1138; RV64XANDESPERF: # %bb.0:1139; RV64XANDESPERF-NEXT: slli a1, a0, 51140; RV64XANDESPERF-NEXT: nds.lea.w a1, a1, a11141; RV64XANDESPERF-NEXT: add a0, a1, a01142; RV64XANDESPERF-NEXT: ret1143 %c = mul i64 %a, 1611144 ret i64 %c1145}1146 1147define i64 @mul162(i64 %a) {1148; RV64I-LABEL: mul162:1149; RV64I: # %bb.0:1150; RV64I-NEXT: li a1, 1621151; RV64I-NEXT: mul a0, a0, a11152; RV64I-NEXT: ret1153;1154; RV64ZBA-LABEL: mul162:1155; RV64ZBA: # %bb.0:1156; RV64ZBA-NEXT: sh3add a0, a0, a01157; RV64ZBA-NEXT: sh3add a0, a0, a01158; RV64ZBA-NEXT: slli a0, a0, 11159; RV64ZBA-NEXT: ret1160;1161; RV64XANDESPERF-LABEL: mul162:1162; RV64XANDESPERF: # %bb.0:1163; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01164; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01165; RV64XANDESPERF-NEXT: slli a0, a0, 11166; RV64XANDESPERF-NEXT: ret1167 %c = mul i64 %a, 1621168 ret i64 %c1169}1170 1171define i64 @addmul162(i64 %a, i64 %b) {1172; RV64I-LABEL: addmul162:1173; RV64I: # %bb.0:1174; RV64I-NEXT: li a2, 1621175; RV64I-NEXT: mul a0, a0, a21176; RV64I-NEXT: add a0, a0, a11177; RV64I-NEXT: ret1178;1179; RV64ZBA-LABEL: addmul162:1180; RV64ZBA: # %bb.0:1181; RV64ZBA-NEXT: sh3add a0, a0, a01182; RV64ZBA-NEXT: sh3add a0, a0, a01183; RV64ZBA-NEXT: sh1add a0, a0, a11184; RV64ZBA-NEXT: ret1185;1186; RV64XANDESPERF-LABEL: addmul162:1187; RV64XANDESPERF: # %bb.0:1188; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01189; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01190; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a01191; RV64XANDESPERF-NEXT: ret1192 %c = mul i64 %a, 1621193 %d = add i64 %c, %b1194 ret i64 %d1195}1196 1197define i64 @mul180(i64 %a) {1198; RV64I-LABEL: mul180:1199; RV64I: # %bb.0:1200; RV64I-NEXT: li a1, 1801201; RV64I-NEXT: mul a0, a0, a11202; RV64I-NEXT: ret1203;1204; RV64ZBA-LABEL: mul180:1205; RV64ZBA: # %bb.0:1206; RV64ZBA-NEXT: sh2add a0, a0, a01207; RV64ZBA-NEXT: sh3add a0, a0, a01208; RV64ZBA-NEXT: slli a0, a0, 21209; RV64ZBA-NEXT: ret1210;1211; RV64XANDESPERF-LABEL: mul180:1212; RV64XANDESPERF: # %bb.0:1213; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01214; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01215; RV64XANDESPERF-NEXT: slli a0, a0, 21216; RV64XANDESPERF-NEXT: ret1217 %c = mul i64 %a, 1801218 ret i64 %c1219}1220 1221define i64 @addmul180(i64 %a, i64 %b) {1222; RV64I-LABEL: addmul180:1223; RV64I: # %bb.0:1224; RV64I-NEXT: li a2, 1801225; RV64I-NEXT: mul a0, a0, a21226; RV64I-NEXT: add a0, a0, a11227; RV64I-NEXT: ret1228;1229; RV64ZBA-LABEL: addmul180:1230; RV64ZBA: # %bb.0:1231; RV64ZBA-NEXT: sh2add a0, a0, a01232; RV64ZBA-NEXT: sh3add a0, a0, a01233; RV64ZBA-NEXT: sh2add a0, a0, a11234; RV64ZBA-NEXT: ret1235;1236; RV64XANDESPERF-LABEL: addmul180:1237; RV64XANDESPERF: # %bb.0:1238; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01239; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01240; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a01241; RV64XANDESPERF-NEXT: ret1242 %c = mul i64 %a, 1801243 %d = add i64 %c, %b1244 ret i64 %d1245}1246 1247define i64 @add255mul180(i64 %a) {1248; RV64I-LABEL: add255mul180:1249; RV64I: # %bb.0:1250; RV64I-NEXT: li a1, 1801251; RV64I-NEXT: mul a0, a0, a11252; RV64I-NEXT: addi a0, a0, 2551253; RV64I-NEXT: ret1254;1255; RV64ZBA-LABEL: add255mul180:1256; RV64ZBA: # %bb.0:1257; RV64ZBA-NEXT: sh2add a0, a0, a01258; RV64ZBA-NEXT: sh3add a0, a0, a01259; RV64ZBA-NEXT: slli a0, a0, 21260; RV64ZBA-NEXT: addi a0, a0, 2551261; RV64ZBA-NEXT: ret1262;1263; RV64XANDESPERF-LABEL: add255mul180:1264; RV64XANDESPERF: # %bb.0:1265; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01266; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01267; RV64XANDESPERF-NEXT: slli a0, a0, 21268; RV64XANDESPERF-NEXT: addi a0, a0, 2551269; RV64XANDESPERF-NEXT: ret1270 %c = mul i64 %a, 1801271 %d = add i64 %c, 2551272 ret i64 %d1273}1274 1275define i64 @mul200(i64 %a) {1276; RV64I-LABEL: mul200:1277; RV64I: # %bb.0:1278; RV64I-NEXT: li a1, 2001279; RV64I-NEXT: mul a0, a0, a11280; RV64I-NEXT: ret1281;1282; RV64ZBA-LABEL: mul200:1283; RV64ZBA: # %bb.0:1284; RV64ZBA-NEXT: sh2add a0, a0, a01285; RV64ZBA-NEXT: sh2add a0, a0, a01286; RV64ZBA-NEXT: slli a0, a0, 31287; RV64ZBA-NEXT: ret1288;1289; RV64XANDESPERF-LABEL: mul200:1290; RV64XANDESPERF: # %bb.0:1291; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01292; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01293; RV64XANDESPERF-NEXT: slli a0, a0, 31294; RV64XANDESPERF-NEXT: ret1295 %c = mul i64 %a, 2001296 ret i64 %c1297}1298 1299define i64 @addmul200(i64 %a, i64 %b) {1300; RV64I-LABEL: addmul200:1301; RV64I: # %bb.0:1302; RV64I-NEXT: li a2, 2001303; RV64I-NEXT: mul a0, a0, a21304; RV64I-NEXT: add a0, a0, a11305; RV64I-NEXT: ret1306;1307; RV64ZBA-LABEL: addmul200:1308; RV64ZBA: # %bb.0:1309; RV64ZBA-NEXT: sh2add a0, a0, a01310; RV64ZBA-NEXT: sh2add a0, a0, a01311; RV64ZBA-NEXT: sh3add a0, a0, a11312; RV64ZBA-NEXT: ret1313;1314; RV64XANDESPERF-LABEL: addmul200:1315; RV64XANDESPERF: # %bb.0:1316; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01317; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01318; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a01319; RV64XANDESPERF-NEXT: ret1320 %c = mul i64 %a, 2001321 %d = add i64 %c, %b1322 ret i64 %d1323}1324 1325define i64 @addmul4096(i64 %a, i64 %b) {1326; CHECK-LABEL: addmul4096:1327; CHECK: # %bb.0:1328; CHECK-NEXT: slli a0, a0, 121329; CHECK-NEXT: add a0, a0, a11330; CHECK-NEXT: ret1331 %c = mul i64 %a, 40961332 %d = add i64 %c, %b1333 ret i64 %d1334}1335 1336define i64 @addmul4230(i64 %a, i64 %b) {1337; CHECK-LABEL: addmul4230:1338; CHECK: # %bb.0:1339; CHECK-NEXT: lui a2, 11340; CHECK-NEXT: addi a2, a2, 1341341; CHECK-NEXT: mul a0, a0, a21342; CHECK-NEXT: add a0, a0, a11343; CHECK-NEXT: ret1344 %c = mul i64 %a, 42301345 %d = add i64 %c, %b1346 ret i64 %d1347}1348 1349define i64 @mul96(i64 %a) {1350; RV64I-LABEL: mul96:1351; RV64I: # %bb.0:1352; RV64I-NEXT: slli a1, a0, 51353; RV64I-NEXT: slli a0, a0, 61354; RV64I-NEXT: add a0, a0, a11355; RV64I-NEXT: ret1356;1357; RV64ZBA-LABEL: mul96:1358; RV64ZBA: # %bb.0:1359; RV64ZBA-NEXT: sh1add a0, a0, a01360; RV64ZBA-NEXT: slli a0, a0, 51361; RV64ZBA-NEXT: ret1362;1363; RV64XANDESPERF-LABEL: mul96:1364; RV64XANDESPERF: # %bb.0:1365; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a01366; RV64XANDESPERF-NEXT: slli a0, a0, 51367; RV64XANDESPERF-NEXT: ret1368 %c = mul i64 %a, 961369 ret i64 %c1370}1371 1372define i64 @mul119(i64 %a) {1373; RV64I-LABEL: mul119:1374; RV64I: # %bb.0:1375; RV64I-NEXT: li a1, 1191376; RV64I-NEXT: mul a0, a0, a11377; RV64I-NEXT: ret1378;1379; RV64ZBA-LABEL: mul119:1380; RV64ZBA: # %bb.0:1381; RV64ZBA-NEXT: sh3add a1, a0, a01382; RV64ZBA-NEXT: slli a0, a0, 71383; RV64ZBA-NEXT: sub a0, a0, a11384; RV64ZBA-NEXT: ret1385;1386; RV64XANDESPERF-LABEL: mul119:1387; RV64XANDESPERF: # %bb.0:1388; RV64XANDESPERF-NEXT: nds.lea.d a1, a0, a01389; RV64XANDESPERF-NEXT: slli a0, a0, 71390; RV64XANDESPERF-NEXT: sub a0, a0, a11391; RV64XANDESPERF-NEXT: ret1392 %c = mul i64 %a, 1191393 ret i64 %c1394}1395 1396define i64 @mul123(i64 %a) {1397; RV64I-LABEL: mul123:1398; RV64I: # %bb.0:1399; RV64I-NEXT: li a1, 1231400; RV64I-NEXT: mul a0, a0, a11401; RV64I-NEXT: ret1402;1403; RV64ZBA-LABEL: mul123:1404; RV64ZBA: # %bb.0:1405; RV64ZBA-NEXT: sh2add a1, a0, a01406; RV64ZBA-NEXT: slli a0, a0, 71407; RV64ZBA-NEXT: sub a0, a0, a11408; RV64ZBA-NEXT: ret1409;1410; RV64XANDESPERF-LABEL: mul123:1411; RV64XANDESPERF: # %bb.0:1412; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a01413; RV64XANDESPERF-NEXT: slli a0, a0, 71414; RV64XANDESPERF-NEXT: sub a0, a0, a11415; RV64XANDESPERF-NEXT: ret1416 %c = mul i64 %a, 1231417 ret i64 %c1418}1419 1420define i64 @mul125(i64 %a) {1421; RV64I-LABEL: mul125:1422; RV64I: # %bb.0:1423; RV64I-NEXT: li a1, 1251424; RV64I-NEXT: mul a0, a0, a11425; RV64I-NEXT: ret1426;1427; RV64ZBA-LABEL: mul125:1428; RV64ZBA: # %bb.0:1429; RV64ZBA-NEXT: sh1add a1, a0, a01430; RV64ZBA-NEXT: slli a0, a0, 71431; RV64ZBA-NEXT: sub a0, a0, a11432; RV64ZBA-NEXT: ret1433;1434; RV64XANDESPERF-LABEL: mul125:1435; RV64XANDESPERF: # %bb.0:1436; RV64XANDESPERF-NEXT: nds.lea.h a1, a0, a01437; RV64XANDESPERF-NEXT: slli a0, a0, 71438; RV64XANDESPERF-NEXT: sub a0, a0, a11439; RV64XANDESPERF-NEXT: ret1440 %c = mul i64 %a, 1251441 ret i64 %c1442}1443 1444define i64 @mul131(i64 %a) {1445; RV64I-LABEL: mul131:1446; RV64I: # %bb.0:1447; RV64I-NEXT: li a1, 1311448; RV64I-NEXT: mul a0, a0, a11449; RV64I-NEXT: ret1450;1451; RV64ZBA-LABEL: mul131:1452; RV64ZBA: # %bb.0:1453; RV64ZBA-NEXT: sh1add a1, a0, a01454; RV64ZBA-NEXT: slli a0, a0, 71455; RV64ZBA-NEXT: add a0, a0, a11456; RV64ZBA-NEXT: ret1457;1458; RV64XANDESPERF-LABEL: mul131:1459; RV64XANDESPERF: # %bb.0:1460; RV64XANDESPERF-NEXT: nds.lea.h a1, a0, a01461; RV64XANDESPERF-NEXT: slli a0, a0, 71462; RV64XANDESPERF-NEXT: add a0, a0, a11463; RV64XANDESPERF-NEXT: ret1464 %c = mul i64 %a, 1311465 ret i64 %c1466}1467 1468define i64 @mul133(i64 %a) {1469; RV64I-LABEL: mul133:1470; RV64I: # %bb.0:1471; RV64I-NEXT: li a1, 1331472; RV64I-NEXT: mul a0, a0, a11473; RV64I-NEXT: ret1474;1475; RV64ZBA-LABEL: mul133:1476; RV64ZBA: # %bb.0:1477; RV64ZBA-NEXT: sh2add a1, a0, a01478; RV64ZBA-NEXT: slli a0, a0, 71479; RV64ZBA-NEXT: add a0, a0, a11480; RV64ZBA-NEXT: ret1481;1482; RV64XANDESPERF-LABEL: mul133:1483; RV64XANDESPERF: # %bb.0:1484; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a01485; RV64XANDESPERF-NEXT: slli a0, a0, 71486; RV64XANDESPERF-NEXT: add a0, a0, a11487; RV64XANDESPERF-NEXT: ret1488 %c = mul i64 %a, 1331489 ret i64 %c1490}1491 1492define i64 @mul137(i64 %a) {1493; RV64I-LABEL: mul137:1494; RV64I: # %bb.0:1495; RV64I-NEXT: li a1, 1371496; RV64I-NEXT: mul a0, a0, a11497; RV64I-NEXT: ret1498;1499; RV64ZBA-LABEL: mul137:1500; RV64ZBA: # %bb.0:1501; RV64ZBA-NEXT: sh3add a1, a0, a01502; RV64ZBA-NEXT: slli a0, a0, 71503; RV64ZBA-NEXT: add a0, a0, a11504; RV64ZBA-NEXT: ret1505;1506; RV64XANDESPERF-LABEL: mul137:1507; RV64XANDESPERF: # %bb.0:1508; RV64XANDESPERF-NEXT: nds.lea.d a1, a0, a01509; RV64XANDESPERF-NEXT: slli a0, a0, 71510; RV64XANDESPERF-NEXT: add a0, a0, a11511; RV64XANDESPERF-NEXT: ret1512 %c = mul i64 %a, 1371513 ret i64 %c1514}1515 1516define i64 @mul160(i64 %a) {1517; RV64I-LABEL: mul160:1518; RV64I: # %bb.0:1519; RV64I-NEXT: slli a1, a0, 51520; RV64I-NEXT: slli a0, a0, 71521; RV64I-NEXT: add a0, a0, a11522; RV64I-NEXT: ret1523;1524; RV64ZBA-LABEL: mul160:1525; RV64ZBA: # %bb.0:1526; RV64ZBA-NEXT: sh2add a0, a0, a01527; RV64ZBA-NEXT: slli a0, a0, 51528; RV64ZBA-NEXT: ret1529;1530; RV64XANDESPERF-LABEL: mul160:1531; RV64XANDESPERF: # %bb.0:1532; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01533; RV64XANDESPERF-NEXT: slli a0, a0, 51534; RV64XANDESPERF-NEXT: ret1535 %c = mul i64 %a, 1601536 ret i64 %c1537}1538 1539define i64 @mul288(i64 %a) {1540; RV64I-LABEL: mul288:1541; RV64I: # %bb.0:1542; RV64I-NEXT: slli a1, a0, 51543; RV64I-NEXT: slli a0, a0, 81544; RV64I-NEXT: add a0, a0, a11545; RV64I-NEXT: ret1546;1547; RV64ZBA-LABEL: mul288:1548; RV64ZBA: # %bb.0:1549; RV64ZBA-NEXT: sh3add a0, a0, a01550; RV64ZBA-NEXT: slli a0, a0, 51551; RV64ZBA-NEXT: ret1552;1553; RV64XANDESPERF-LABEL: mul288:1554; RV64XANDESPERF: # %bb.0:1555; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01556; RV64XANDESPERF-NEXT: slli a0, a0, 51557; RV64XANDESPERF-NEXT: ret1558 %c = mul i64 %a, 2881559 ret i64 %c1560}1561 1562define i64 @zext_mul44(i32 signext %a) {1563; RV64I-LABEL: zext_mul44:1564; RV64I: # %bb.0:1565; RV64I-NEXT: li a1, 111566; RV64I-NEXT: slli a1, a1, 341567; RV64I-NEXT: slli a0, a0, 321568; RV64I-NEXT: mulhu a0, a0, a11569; RV64I-NEXT: ret1570;1571; RV64ZBA-LABEL: zext_mul44:1572; RV64ZBA: # %bb.0:1573; RV64ZBA-NEXT: slli.uw a0, a0, 21574; RV64ZBA-NEXT: sh2add a1, a0, a01575; RV64ZBA-NEXT: sh1add a0, a1, a01576; RV64ZBA-NEXT: ret1577;1578; RV64XANDESPERF-LABEL: zext_mul44:1579; RV64XANDESPERF: # %bb.0:1580; RV64XANDESPERF-NEXT: slli a0, a0, 321581; RV64XANDESPERF-NEXT: srli a0, a0, 301582; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a01583; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a11584; RV64XANDESPERF-NEXT: ret1585 %b = zext i32 %a to i641586 %c = mul i64 %b, 441587 ret i64 %c1588}1589 1590define i64 @zext_mul68(i32 signext %a) {1591; RV64I-LABEL: zext_mul68:1592; RV64I: # %bb.0:1593; RV64I-NEXT: slli a0, a0, 321594; RV64I-NEXT: srli a1, a0, 301595; RV64I-NEXT: srli a0, a0, 261596; RV64I-NEXT: add a0, a0, a11597; RV64I-NEXT: ret1598;1599; RV64ZBA-LABEL: zext_mul68:1600; RV64ZBA: # %bb.0:1601; RV64ZBA-NEXT: slli.uw a1, a0, 61602; RV64ZBA-NEXT: sh2add.uw a0, a0, a11603; RV64ZBA-NEXT: ret1604;1605; RV64XANDESPERF-LABEL: zext_mul68:1606; RV64XANDESPERF: # %bb.0:1607; RV64XANDESPERF-NEXT: slli a1, a0, 321608; RV64XANDESPERF-NEXT: srli a1, a1, 261609; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a1, a01610; RV64XANDESPERF-NEXT: ret1611 %b = zext i32 %a to i641612 %c = mul i64 %b, 681613 ret i64 %c1614}1615 1616define i64 @zext_mul96(i32 signext %a) {1617; RV64I-LABEL: zext_mul96:1618; RV64I: # %bb.0:1619; RV64I-NEXT: slli a0, a0, 321620; RV64I-NEXT: srli a1, a0, 271621; RV64I-NEXT: srli a0, a0, 261622; RV64I-NEXT: add a0, a0, a11623; RV64I-NEXT: ret1624;1625; RV64ZBA-LABEL: zext_mul96:1626; RV64ZBA: # %bb.0:1627; RV64ZBA-NEXT: slli.uw a0, a0, 51628; RV64ZBA-NEXT: sh1add a0, a0, a01629; RV64ZBA-NEXT: ret1630;1631; RV64XANDESPERF-LABEL: zext_mul96:1632; RV64XANDESPERF: # %bb.0:1633; RV64XANDESPERF-NEXT: slli a0, a0, 321634; RV64XANDESPERF-NEXT: srli a0, a0, 271635; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a01636; RV64XANDESPERF-NEXT: ret1637 %b = zext i32 %a to i641638 %c = mul i64 %b, 961639 ret i64 %c1640}1641 1642define i64 @zext_mul100(i32 signext %a) {1643; RV64I-LABEL: zext_mul100:1644; RV64I: # %bb.0:1645; RV64I-NEXT: li a1, 251646; RV64I-NEXT: slli a1, a1, 341647; RV64I-NEXT: slli a0, a0, 321648; RV64I-NEXT: mulhu a0, a0, a11649; RV64I-NEXT: ret1650;1651; RV64ZBA-LABEL: zext_mul100:1652; RV64ZBA: # %bb.0:1653; RV64ZBA-NEXT: slli.uw a0, a0, 21654; RV64ZBA-NEXT: sh2add a0, a0, a01655; RV64ZBA-NEXT: sh2add a0, a0, a01656; RV64ZBA-NEXT: ret1657;1658; RV64XANDESPERF-LABEL: zext_mul100:1659; RV64XANDESPERF: # %bb.0:1660; RV64XANDESPERF-NEXT: slli a0, a0, 321661; RV64XANDESPERF-NEXT: srli a0, a0, 301662; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01663; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01664; RV64XANDESPERF-NEXT: ret1665 %b = zext i32 %a to i641666 %c = mul i64 %b, 1001667 ret i64 %c1668}1669 1670define i64 @zext_mul160(i32 signext %a) {1671; RV64I-LABEL: zext_mul160:1672; RV64I: # %bb.0:1673; RV64I-NEXT: slli a0, a0, 321674; RV64I-NEXT: srli a1, a0, 271675; RV64I-NEXT: srli a0, a0, 251676; RV64I-NEXT: add a0, a0, a11677; RV64I-NEXT: ret1678;1679; RV64ZBA-LABEL: zext_mul160:1680; RV64ZBA: # %bb.0:1681; RV64ZBA-NEXT: slli.uw a0, a0, 51682; RV64ZBA-NEXT: sh2add a0, a0, a01683; RV64ZBA-NEXT: ret1684;1685; RV64XANDESPERF-LABEL: zext_mul160:1686; RV64XANDESPERF: # %bb.0:1687; RV64XANDESPERF-NEXT: slli a0, a0, 321688; RV64XANDESPERF-NEXT: srli a0, a0, 271689; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01690; RV64XANDESPERF-NEXT: ret1691 %b = zext i32 %a to i641692 %c = mul i64 %b, 1601693 ret i64 %c1694}1695 1696define i64 @zext_mul288(i32 signext %a) {1697; RV64I-LABEL: zext_mul288:1698; RV64I: # %bb.0:1699; RV64I-NEXT: slli a0, a0, 321700; RV64I-NEXT: srli a1, a0, 271701; RV64I-NEXT: srli a0, a0, 241702; RV64I-NEXT: add a0, a0, a11703; RV64I-NEXT: ret1704;1705; RV64ZBA-LABEL: zext_mul288:1706; RV64ZBA: # %bb.0:1707; RV64ZBA-NEXT: slli.uw a0, a0, 51708; RV64ZBA-NEXT: sh3add a0, a0, a01709; RV64ZBA-NEXT: ret1710;1711; RV64XANDESPERF-LABEL: zext_mul288:1712; RV64XANDESPERF: # %bb.0:1713; RV64XANDESPERF-NEXT: slli a0, a0, 321714; RV64XANDESPERF-NEXT: srli a0, a0, 271715; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01716; RV64XANDESPERF-NEXT: ret1717 %b = zext i32 %a to i641718 %c = mul i64 %b, 2881719 ret i64 %c1720}1721 1722; We can't use slli.uw becaues the shift amount is more than 31.1723define i64 @zext_mul12884901888(i32 signext %a) {1724; RV64I-LABEL: zext_mul12884901888:1725; RV64I: # %bb.0:1726; RV64I-NEXT: slli a1, a0, 321727; RV64I-NEXT: slli a0, a0, 331728; RV64I-NEXT: add a0, a0, a11729; RV64I-NEXT: ret1730;1731; RV64ZBA-LABEL: zext_mul12884901888:1732; RV64ZBA: # %bb.0:1733; RV64ZBA-NEXT: sh1add a0, a0, a01734; RV64ZBA-NEXT: slli a0, a0, 321735; RV64ZBA-NEXT: ret1736;1737; RV64XANDESPERF-LABEL: zext_mul12884901888:1738; RV64XANDESPERF: # %bb.0:1739; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a01740; RV64XANDESPERF-NEXT: slli a0, a0, 321741; RV64XANDESPERF-NEXT: ret1742 %b = zext i32 %a to i641743 %c = mul i64 %b, 128849018881744 ret i64 %c1745}1746 1747; We can't use slli.uw becaues the shift amount is more than 31.1748define i64 @zext_mul21474836480(i32 signext %a) {1749; RV64I-LABEL: zext_mul21474836480:1750; RV64I: # %bb.0:1751; RV64I-NEXT: slli a1, a0, 321752; RV64I-NEXT: slli a0, a0, 341753; RV64I-NEXT: add a0, a0, a11754; RV64I-NEXT: ret1755;1756; RV64ZBA-LABEL: zext_mul21474836480:1757; RV64ZBA: # %bb.0:1758; RV64ZBA-NEXT: sh2add a0, a0, a01759; RV64ZBA-NEXT: slli a0, a0, 321760; RV64ZBA-NEXT: ret1761;1762; RV64XANDESPERF-LABEL: zext_mul21474836480:1763; RV64XANDESPERF: # %bb.0:1764; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a01765; RV64XANDESPERF-NEXT: slli a0, a0, 321766; RV64XANDESPERF-NEXT: ret1767 %b = zext i32 %a to i641768 %c = mul i64 %b, 214748364801769 ret i64 %c1770}1771 1772; We can't use slli.uw becaues the shift amount is more than 31.1773define i64 @zext_mul38654705664(i32 signext %a) {1774; RV64I-LABEL: zext_mul38654705664:1775; RV64I: # %bb.0:1776; RV64I-NEXT: slli a1, a0, 321777; RV64I-NEXT: slli a0, a0, 351778; RV64I-NEXT: add a0, a0, a11779; RV64I-NEXT: ret1780;1781; RV64ZBA-LABEL: zext_mul38654705664:1782; RV64ZBA: # %bb.0:1783; RV64ZBA-NEXT: sh3add a0, a0, a01784; RV64ZBA-NEXT: slli a0, a0, 321785; RV64ZBA-NEXT: ret1786;1787; RV64XANDESPERF-LABEL: zext_mul38654705664:1788; RV64XANDESPERF: # %bb.0:1789; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a01790; RV64XANDESPERF-NEXT: slli a0, a0, 321791; RV64XANDESPERF-NEXT: ret1792 %b = zext i32 %a to i641793 %c = mul i64 %b, 386547056641794 ret i64 %c1795}1796 1797define i64 @sh1add_imm(i64 %0) {1798; CHECK-LABEL: sh1add_imm:1799; CHECK: # %bb.0:1800; CHECK-NEXT: slli a0, a0, 11801; CHECK-NEXT: addi a0, a0, 51802; CHECK-NEXT: ret1803 %a = shl i64 %0, 11804 %b = add i64 %a, 51805 ret i64 %b1806}1807 1808define i64 @sh2add_imm(i64 %0) {1809; CHECK-LABEL: sh2add_imm:1810; CHECK: # %bb.0:1811; CHECK-NEXT: slli a0, a0, 21812; CHECK-NEXT: addi a0, a0, -61813; CHECK-NEXT: ret1814 %a = shl i64 %0, 21815 %b = add i64 %a, -61816 ret i64 %b1817}1818 1819define i64 @sh3add_imm(i64 %0) {1820; CHECK-LABEL: sh3add_imm:1821; CHECK: # %bb.0:1822; CHECK-NEXT: slli a0, a0, 31823; CHECK-NEXT: addi a0, a0, 71824; CHECK-NEXT: ret1825 %a = shl i64 %0, 31826 %b = add i64 %a, 71827 ret i64 %b1828}1829 1830define i64 @sh1adduw_imm(i32 signext %0) {1831; RV64I-LABEL: sh1adduw_imm:1832; RV64I: # %bb.0:1833; RV64I-NEXT: slli a0, a0, 321834; RV64I-NEXT: srli a0, a0, 311835; RV64I-NEXT: addi a0, a0, 111836; RV64I-NEXT: ret1837;1838; RV64ZBA-LABEL: sh1adduw_imm:1839; RV64ZBA: # %bb.0:1840; RV64ZBA-NEXT: slli.uw a0, a0, 11841; RV64ZBA-NEXT: addi a0, a0, 111842; RV64ZBA-NEXT: ret1843;1844; RV64XANDESPERF-LABEL: sh1adduw_imm:1845; RV64XANDESPERF: # %bb.0:1846; RV64XANDESPERF-NEXT: slli a0, a0, 321847; RV64XANDESPERF-NEXT: srli a0, a0, 311848; RV64XANDESPERF-NEXT: addi a0, a0, 111849; RV64XANDESPERF-NEXT: ret1850 %a = zext i32 %0 to i641851 %b = shl i64 %a, 11852 %c = add i64 %b, 111853 ret i64 %c1854}1855 1856define i64 @sh2adduw_imm(i32 signext %0) {1857; RV64I-LABEL: sh2adduw_imm:1858; RV64I: # %bb.0:1859; RV64I-NEXT: slli a0, a0, 321860; RV64I-NEXT: srli a0, a0, 301861; RV64I-NEXT: addi a0, a0, -121862; RV64I-NEXT: ret1863;1864; RV64ZBA-LABEL: sh2adduw_imm:1865; RV64ZBA: # %bb.0:1866; RV64ZBA-NEXT: slli.uw a0, a0, 21867; RV64ZBA-NEXT: addi a0, a0, -121868; RV64ZBA-NEXT: ret1869;1870; RV64XANDESPERF-LABEL: sh2adduw_imm:1871; RV64XANDESPERF: # %bb.0:1872; RV64XANDESPERF-NEXT: slli a0, a0, 321873; RV64XANDESPERF-NEXT: srli a0, a0, 301874; RV64XANDESPERF-NEXT: addi a0, a0, -121875; RV64XANDESPERF-NEXT: ret1876 %a = zext i32 %0 to i641877 %b = shl i64 %a, 21878 %c = add i64 %b, -121879 ret i64 %c1880}1881 1882define i64 @sh3adduw_imm(i32 signext %0) {1883; RV64I-LABEL: sh3adduw_imm:1884; RV64I: # %bb.0:1885; RV64I-NEXT: slli a0, a0, 321886; RV64I-NEXT: srli a0, a0, 291887; RV64I-NEXT: addi a0, a0, 131888; RV64I-NEXT: ret1889;1890; RV64ZBA-LABEL: sh3adduw_imm:1891; RV64ZBA: # %bb.0:1892; RV64ZBA-NEXT: slli.uw a0, a0, 31893; RV64ZBA-NEXT: addi a0, a0, 131894; RV64ZBA-NEXT: ret1895;1896; RV64XANDESPERF-LABEL: sh3adduw_imm:1897; RV64XANDESPERF: # %bb.0:1898; RV64XANDESPERF-NEXT: slli a0, a0, 321899; RV64XANDESPERF-NEXT: srli a0, a0, 291900; RV64XANDESPERF-NEXT: addi a0, a0, 131901; RV64XANDESPERF-NEXT: ret1902 %a = zext i32 %0 to i641903 %b = shl i64 %a, 31904 %c = add i64 %b, 131905 ret i64 %c1906}1907 1908define i64 @adduw_imm(i32 signext %0) nounwind {1909; RV64I-LABEL: adduw_imm:1910; RV64I: # %bb.0:1911; RV64I-NEXT: slli a0, a0, 321912; RV64I-NEXT: srli a0, a0, 321913; RV64I-NEXT: addi a0, a0, 51914; RV64I-NEXT: ret1915;1916; RV64ZBA-LABEL: adduw_imm:1917; RV64ZBA: # %bb.0:1918; RV64ZBA-NEXT: zext.w a0, a01919; RV64ZBA-NEXT: addi a0, a0, 51920; RV64ZBA-NEXT: ret1921;1922; RV64XANDESPERF-LABEL: adduw_imm:1923; RV64XANDESPERF: # %bb.0:1924; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 31, 01925; RV64XANDESPERF-NEXT: addi a0, a0, 51926; RV64XANDESPERF-NEXT: ret1927 %a = zext i32 %0 to i641928 %b = add i64 %a, 51929 ret i64 %b1930}1931 1932define i64 @mul258(i64 %a) {1933; RV64I-LABEL: mul258:1934; RV64I: # %bb.0:1935; RV64I-NEXT: slli a1, a0, 11936; RV64I-NEXT: slli a0, a0, 81937; RV64I-NEXT: add a0, a0, a11938; RV64I-NEXT: ret1939;1940; RV64ZBA-LABEL: mul258:1941; RV64ZBA: # %bb.0:1942; RV64ZBA-NEXT: slli a1, a0, 81943; RV64ZBA-NEXT: sh1add a0, a0, a11944; RV64ZBA-NEXT: ret1945;1946; RV64XANDESPERF-LABEL: mul258:1947; RV64XANDESPERF: # %bb.0:1948; RV64XANDESPERF-NEXT: slli a1, a0, 81949; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a01950; RV64XANDESPERF-NEXT: ret1951 %c = mul i64 %a, 2581952 ret i64 %c1953}1954 1955define i64 @mul260(i64 %a) {1956; RV64I-LABEL: mul260:1957; RV64I: # %bb.0:1958; RV64I-NEXT: slli a1, a0, 21959; RV64I-NEXT: slli a0, a0, 81960; RV64I-NEXT: add a0, a0, a11961; RV64I-NEXT: ret1962;1963; RV64ZBA-LABEL: mul260:1964; RV64ZBA: # %bb.0:1965; RV64ZBA-NEXT: slli a1, a0, 81966; RV64ZBA-NEXT: sh2add a0, a0, a11967; RV64ZBA-NEXT: ret1968;1969; RV64XANDESPERF-LABEL: mul260:1970; RV64XANDESPERF: # %bb.0:1971; RV64XANDESPERF-NEXT: slli a1, a0, 81972; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a01973; RV64XANDESPERF-NEXT: ret1974 %c = mul i64 %a, 2601975 ret i64 %c1976}1977 1978define i64 @mul264(i64 %a) {1979; RV64I-LABEL: mul264:1980; RV64I: # %bb.0:1981; RV64I-NEXT: slli a1, a0, 31982; RV64I-NEXT: slli a0, a0, 81983; RV64I-NEXT: add a0, a0, a11984; RV64I-NEXT: ret1985;1986; RV64ZBA-LABEL: mul264:1987; RV64ZBA: # %bb.0:1988; RV64ZBA-NEXT: slli a1, a0, 81989; RV64ZBA-NEXT: sh3add a0, a0, a11990; RV64ZBA-NEXT: ret1991;1992; RV64XANDESPERF-LABEL: mul264:1993; RV64XANDESPERF: # %bb.0:1994; RV64XANDESPERF-NEXT: slli a1, a0, 81995; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a01996; RV64XANDESPERF-NEXT: ret1997 %c = mul i64 %a, 2641998 ret i64 %c1999}2000 2001define i64 @imm_zextw() nounwind {2002; RV64I-LABEL: imm_zextw:2003; RV64I: # %bb.0:2004; RV64I-NEXT: li a0, 12005; RV64I-NEXT: slli a0, a0, 322006; RV64I-NEXT: addi a0, a0, -22007; RV64I-NEXT: ret2008;2009; RV64ZBA-LABEL: imm_zextw:2010; RV64ZBA: # %bb.0:2011; RV64ZBA-NEXT: li a0, -22012; RV64ZBA-NEXT: zext.w a0, a02013; RV64ZBA-NEXT: ret2014;2015; RV64XANDESPERF-LABEL: imm_zextw:2016; RV64XANDESPERF: # %bb.0:2017; RV64XANDESPERF-NEXT: li a0, 12018; RV64XANDESPERF-NEXT: slli a0, a0, 322019; RV64XANDESPERF-NEXT: addi a0, a0, -22020; RV64XANDESPERF-NEXT: ret2021 ret i64 4294967294 ; -2 in 32 bits.2022}2023 2024define i64 @mul11(i64 %a) {2025; RV64I-LABEL: mul11:2026; RV64I: # %bb.0:2027; RV64I-NEXT: li a1, 112028; RV64I-NEXT: mul a0, a0, a12029; RV64I-NEXT: ret2030;2031; RV64ZBA-LABEL: mul11:2032; RV64ZBA: # %bb.0:2033; RV64ZBA-NEXT: sh2add a1, a0, a02034; RV64ZBA-NEXT: sh1add a0, a1, a02035; RV64ZBA-NEXT: ret2036;2037; RV64XANDESPERF-LABEL: mul11:2038; RV64XANDESPERF: # %bb.0:2039; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a02040; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a12041; RV64XANDESPERF-NEXT: ret2042 %c = mul i64 %a, 112043 ret i64 %c2044}2045 2046define i64 @mul19(i64 %a) {2047; RV64I-LABEL: mul19:2048; RV64I: # %bb.0:2049; RV64I-NEXT: li a1, 192050; RV64I-NEXT: mul a0, a0, a12051; RV64I-NEXT: ret2052;2053; RV64ZBA-LABEL: mul19:2054; RV64ZBA: # %bb.0:2055; RV64ZBA-NEXT: sh3add a1, a0, a02056; RV64ZBA-NEXT: sh1add a0, a1, a02057; RV64ZBA-NEXT: ret2058;2059; RV64XANDESPERF-LABEL: mul19:2060; RV64XANDESPERF: # %bb.0:2061; RV64XANDESPERF-NEXT: nds.lea.d a1, a0, a02062; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a12063; RV64XANDESPERF-NEXT: ret2064 %c = mul i64 %a, 192065 ret i64 %c2066}2067 2068define i64 @mul13(i64 %a) {2069; RV64I-LABEL: mul13:2070; RV64I: # %bb.0:2071; RV64I-NEXT: li a1, 132072; RV64I-NEXT: mul a0, a0, a12073; RV64I-NEXT: ret2074;2075; RV64ZBA-LABEL: mul13:2076; RV64ZBA: # %bb.0:2077; RV64ZBA-NEXT: sh1add a1, a0, a02078; RV64ZBA-NEXT: sh2add a0, a1, a02079; RV64ZBA-NEXT: ret2080;2081; RV64XANDESPERF-LABEL: mul13:2082; RV64XANDESPERF: # %bb.0:2083; RV64XANDESPERF-NEXT: nds.lea.h a1, a0, a02084; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12085; RV64XANDESPERF-NEXT: ret2086 %c = mul i64 %a, 132087 ret i64 %c2088}2089 2090define i64 @mul21(i64 %a) {2091; RV64I-LABEL: mul21:2092; RV64I: # %bb.0:2093; RV64I-NEXT: li a1, 212094; RV64I-NEXT: mul a0, a0, a12095; RV64I-NEXT: ret2096;2097; RV64ZBA-LABEL: mul21:2098; RV64ZBA: # %bb.0:2099; RV64ZBA-NEXT: sh2add a1, a0, a02100; RV64ZBA-NEXT: sh2add a0, a1, a02101; RV64ZBA-NEXT: ret2102;2103; RV64XANDESPERF-LABEL: mul21:2104; RV64XANDESPERF: # %bb.0:2105; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a02106; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12107; RV64XANDESPERF-NEXT: ret2108 %c = mul i64 %a, 212109 ret i64 %c2110}2111 2112define i64 @mul37(i64 %a) {2113; RV64I-LABEL: mul37:2114; RV64I: # %bb.0:2115; RV64I-NEXT: li a1, 372116; RV64I-NEXT: mul a0, a0, a12117; RV64I-NEXT: ret2118;2119; RV64ZBA-LABEL: mul37:2120; RV64ZBA: # %bb.0:2121; RV64ZBA-NEXT: sh3add a1, a0, a02122; RV64ZBA-NEXT: sh2add a0, a1, a02123; RV64ZBA-NEXT: ret2124;2125; RV64XANDESPERF-LABEL: mul37:2126; RV64XANDESPERF: # %bb.0:2127; RV64XANDESPERF-NEXT: nds.lea.d a1, a0, a02128; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12129; RV64XANDESPERF-NEXT: ret2130 %c = mul i64 %a, 372131 ret i64 %c2132}2133 2134define i64 @mul25(i64 %a) {2135; RV64I-LABEL: mul25:2136; RV64I: # %bb.0:2137; RV64I-NEXT: li a1, 252138; RV64I-NEXT: mul a0, a0, a12139; RV64I-NEXT: ret2140;2141; RV64ZBA-LABEL: mul25:2142; RV64ZBA: # %bb.0:2143; RV64ZBA-NEXT: sh2add a0, a0, a02144; RV64ZBA-NEXT: sh2add a0, a0, a02145; RV64ZBA-NEXT: ret2146;2147; RV64XANDESPERF-LABEL: mul25:2148; RV64XANDESPERF: # %bb.0:2149; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a02150; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a02151; RV64XANDESPERF-NEXT: ret2152 %c = mul i64 %a, 252153 ret i64 %c2154}2155 2156define i64 @mul41(i64 %a) {2157; RV64I-LABEL: mul41:2158; RV64I: # %bb.0:2159; RV64I-NEXT: li a1, 412160; RV64I-NEXT: mul a0, a0, a12161; RV64I-NEXT: ret2162;2163; RV64ZBA-LABEL: mul41:2164; RV64ZBA: # %bb.0:2165; RV64ZBA-NEXT: sh2add a1, a0, a02166; RV64ZBA-NEXT: sh3add a0, a1, a02167; RV64ZBA-NEXT: ret2168;2169; RV64XANDESPERF-LABEL: mul41:2170; RV64XANDESPERF: # %bb.0:2171; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a02172; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12173; RV64XANDESPERF-NEXT: ret2174 %c = mul i64 %a, 412175 ret i64 %c2176}2177 2178define i64 @mul73(i64 %a) {2179; RV64I-LABEL: mul73:2180; RV64I: # %bb.0:2181; RV64I-NEXT: li a1, 732182; RV64I-NEXT: mul a0, a0, a12183; RV64I-NEXT: ret2184;2185; RV64ZBA-LABEL: mul73:2186; RV64ZBA: # %bb.0:2187; RV64ZBA-NEXT: sh3add a1, a0, a02188; RV64ZBA-NEXT: sh3add a0, a1, a02189; RV64ZBA-NEXT: ret2190;2191; RV64XANDESPERF-LABEL: mul73:2192; RV64XANDESPERF: # %bb.0:2193; RV64XANDESPERF-NEXT: nds.lea.d a1, a0, a02194; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12195; RV64XANDESPERF-NEXT: ret2196 %c = mul i64 %a, 732197 ret i64 %c2198}2199 2200define i64 @mul27(i64 %a) {2201; RV64I-LABEL: mul27:2202; RV64I: # %bb.0:2203; RV64I-NEXT: li a1, 272204; RV64I-NEXT: mul a0, a0, a12205; RV64I-NEXT: ret2206;2207; RV64ZBA-LABEL: mul27:2208; RV64ZBA: # %bb.0:2209; RV64ZBA-NEXT: sh1add a0, a0, a02210; RV64ZBA-NEXT: sh3add a0, a0, a02211; RV64ZBA-NEXT: ret2212;2213; RV64XANDESPERF-LABEL: mul27:2214; RV64XANDESPERF: # %bb.0:2215; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a02216; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a02217; RV64XANDESPERF-NEXT: ret2218 %c = mul i64 %a, 272219 ret i64 %c2220}2221 2222define i64 @mul45(i64 %a) {2223; RV64I-LABEL: mul45:2224; RV64I: # %bb.0:2225; RV64I-NEXT: li a1, 452226; RV64I-NEXT: mul a0, a0, a12227; RV64I-NEXT: ret2228;2229; RV64ZBA-LABEL: mul45:2230; RV64ZBA: # %bb.0:2231; RV64ZBA-NEXT: sh2add a0, a0, a02232; RV64ZBA-NEXT: sh3add a0, a0, a02233; RV64ZBA-NEXT: ret2234;2235; RV64XANDESPERF-LABEL: mul45:2236; RV64XANDESPERF: # %bb.0:2237; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a02238; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a02239; RV64XANDESPERF-NEXT: ret2240 %c = mul i64 %a, 452241 ret i64 %c2242}2243 2244define i64 @mul81(i64 %a) {2245; RV64I-LABEL: mul81:2246; RV64I: # %bb.0:2247; RV64I-NEXT: li a1, 812248; RV64I-NEXT: mul a0, a0, a12249; RV64I-NEXT: ret2250;2251; RV64ZBA-LABEL: mul81:2252; RV64ZBA: # %bb.0:2253; RV64ZBA-NEXT: sh3add a0, a0, a02254; RV64ZBA-NEXT: sh3add a0, a0, a02255; RV64ZBA-NEXT: ret2256;2257; RV64XANDESPERF-LABEL: mul81:2258; RV64XANDESPERF: # %bb.0:2259; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a02260; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a02261; RV64XANDESPERF-NEXT: ret2262 %c = mul i64 %a, 812263 ret i64 %c2264}2265 2266define i64 @mul4098(i64 %a) {2267; RV64I-LABEL: mul4098:2268; RV64I: # %bb.0:2269; RV64I-NEXT: slli a1, a0, 12270; RV64I-NEXT: slli a0, a0, 122271; RV64I-NEXT: add a0, a0, a12272; RV64I-NEXT: ret2273;2274; RV64ZBA-LABEL: mul4098:2275; RV64ZBA: # %bb.0:2276; RV64ZBA-NEXT: slli a1, a0, 122277; RV64ZBA-NEXT: sh1add a0, a0, a12278; RV64ZBA-NEXT: ret2279;2280; RV64XANDESPERF-LABEL: mul4098:2281; RV64XANDESPERF: # %bb.0:2282; RV64XANDESPERF-NEXT: slli a1, a0, 122283; RV64XANDESPERF-NEXT: nds.lea.h a0, a1, a02284; RV64XANDESPERF-NEXT: ret2285 %c = mul i64 %a, 40982286 ret i64 %c2287}2288 2289define i64 @mul4100(i64 %a) {2290; RV64I-LABEL: mul4100:2291; RV64I: # %bb.0:2292; RV64I-NEXT: slli a1, a0, 22293; RV64I-NEXT: slli a0, a0, 122294; RV64I-NEXT: add a0, a0, a12295; RV64I-NEXT: ret2296;2297; RV64ZBA-LABEL: mul4100:2298; RV64ZBA: # %bb.0:2299; RV64ZBA-NEXT: slli a1, a0, 122300; RV64ZBA-NEXT: sh2add a0, a0, a12301; RV64ZBA-NEXT: ret2302;2303; RV64XANDESPERF-LABEL: mul4100:2304; RV64XANDESPERF: # %bb.0:2305; RV64XANDESPERF-NEXT: slli a1, a0, 122306; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a02307; RV64XANDESPERF-NEXT: ret2308 %c = mul i64 %a, 41002309 ret i64 %c2310}2311 2312define i64 @mul4104(i64 %a) {2313; RV64I-LABEL: mul4104:2314; RV64I: # %bb.0:2315; RV64I-NEXT: slli a1, a0, 32316; RV64I-NEXT: slli a0, a0, 122317; RV64I-NEXT: add a0, a0, a12318; RV64I-NEXT: ret2319;2320; RV64ZBA-LABEL: mul4104:2321; RV64ZBA: # %bb.0:2322; RV64ZBA-NEXT: slli a1, a0, 122323; RV64ZBA-NEXT: sh3add a0, a0, a12324; RV64ZBA-NEXT: ret2325;2326; RV64XANDESPERF-LABEL: mul4104:2327; RV64XANDESPERF: # %bb.0:2328; RV64XANDESPERF-NEXT: slli a1, a0, 122329; RV64XANDESPERF-NEXT: nds.lea.d a0, a1, a02330; RV64XANDESPERF-NEXT: ret2331 %c = mul i64 %a, 41042332 ret i64 %c2333}2334 2335define signext i32 @mulw192(i32 signext %a) {2336; RV64I-LABEL: mulw192:2337; RV64I: # %bb.0:2338; RV64I-NEXT: slli a1, a0, 62339; RV64I-NEXT: slli a0, a0, 72340; RV64I-NEXT: addw a0, a0, a12341; RV64I-NEXT: ret2342;2343; RV64ZBA-LABEL: mulw192:2344; RV64ZBA: # %bb.0:2345; RV64ZBA-NEXT: sh1add a0, a0, a02346; RV64ZBA-NEXT: slliw a0, a0, 62347; RV64ZBA-NEXT: ret2348;2349; RV64XANDESPERF-LABEL: mulw192:2350; RV64XANDESPERF: # %bb.0:2351; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a02352; RV64XANDESPERF-NEXT: slliw a0, a0, 62353; RV64XANDESPERF-NEXT: ret2354 %c = mul i32 %a, 1922355 ret i32 %c2356}2357 2358define signext i32 @mulw320(i32 signext %a) {2359; RV64I-LABEL: mulw320:2360; RV64I: # %bb.0:2361; RV64I-NEXT: slli a1, a0, 62362; RV64I-NEXT: slli a0, a0, 82363; RV64I-NEXT: addw a0, a0, a12364; RV64I-NEXT: ret2365;2366; RV64ZBA-LABEL: mulw320:2367; RV64ZBA: # %bb.0:2368; RV64ZBA-NEXT: sh2add a0, a0, a02369; RV64ZBA-NEXT: slliw a0, a0, 62370; RV64ZBA-NEXT: ret2371;2372; RV64XANDESPERF-LABEL: mulw320:2373; RV64XANDESPERF: # %bb.0:2374; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a02375; RV64XANDESPERF-NEXT: slliw a0, a0, 62376; RV64XANDESPERF-NEXT: ret2377 %c = mul i32 %a, 3202378 ret i32 %c2379}2380 2381define signext i32 @mulw576(i32 signext %a) {2382; RV64I-LABEL: mulw576:2383; RV64I: # %bb.0:2384; RV64I-NEXT: slli a1, a0, 62385; RV64I-NEXT: slli a0, a0, 92386; RV64I-NEXT: addw a0, a0, a12387; RV64I-NEXT: ret2388;2389; RV64ZBA-LABEL: mulw576:2390; RV64ZBA: # %bb.0:2391; RV64ZBA-NEXT: sh3add a0, a0, a02392; RV64ZBA-NEXT: slliw a0, a0, 62393; RV64ZBA-NEXT: ret2394;2395; RV64XANDESPERF-LABEL: mulw576:2396; RV64XANDESPERF: # %bb.0:2397; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a02398; RV64XANDESPERF-NEXT: slliw a0, a0, 62399; RV64XANDESPERF-NEXT: ret2400 %c = mul i32 %a, 5762401 ret i32 %c2402}2403 2404define i64 @add4104(i64 %a) {2405; RV64I-LABEL: add4104:2406; RV64I: # %bb.0:2407; RV64I-NEXT: lui a1, 12408; RV64I-NEXT: addi a1, a1, 82409; RV64I-NEXT: add a0, a0, a12410; RV64I-NEXT: ret2411;2412; RV64ZBA-LABEL: add4104:2413; RV64ZBA: # %bb.0:2414; RV64ZBA-NEXT: li a1, 10262415; RV64ZBA-NEXT: sh2add a0, a1, a02416; RV64ZBA-NEXT: ret2417;2418; RV64XANDESPERF-LABEL: add4104:2419; RV64XANDESPERF: # %bb.0:2420; RV64XANDESPERF-NEXT: li a1, 10262421; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12422; RV64XANDESPERF-NEXT: ret2423 %c = add i64 %a, 41042424 ret i64 %c2425}2426 2427define i64 @add4104_2(i64 %a) {2428; RV64I-LABEL: add4104_2:2429; RV64I: # %bb.0:2430; RV64I-NEXT: lui a1, 12431; RV64I-NEXT: addi a1, a1, 82432; RV64I-NEXT: or a0, a0, a12433; RV64I-NEXT: ret2434;2435; RV64ZBA-LABEL: add4104_2:2436; RV64ZBA: # %bb.0:2437; RV64ZBA-NEXT: li a1, 10262438; RV64ZBA-NEXT: sh2add a0, a1, a02439; RV64ZBA-NEXT: ret2440;2441; RV64XANDESPERF-LABEL: add4104_2:2442; RV64XANDESPERF: # %bb.0:2443; RV64XANDESPERF-NEXT: li a1, 10262444; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12445; RV64XANDESPERF-NEXT: ret2446 %c = or disjoint i64 %a, 41042447 ret i64 %c2448}2449 2450define i64 @add8208(i64 %a) {2451; RV64I-LABEL: add8208:2452; RV64I: # %bb.0:2453; RV64I-NEXT: lui a1, 22454; RV64I-NEXT: addi a1, a1, 162455; RV64I-NEXT: add a0, a0, a12456; RV64I-NEXT: ret2457;2458; RV64ZBA-LABEL: add8208:2459; RV64ZBA: # %bb.0:2460; RV64ZBA-NEXT: li a1, 10262461; RV64ZBA-NEXT: sh3add a0, a1, a02462; RV64ZBA-NEXT: ret2463;2464; RV64XANDESPERF-LABEL: add8208:2465; RV64XANDESPERF: # %bb.0:2466; RV64XANDESPERF-NEXT: li a1, 10262467; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12468; RV64XANDESPERF-NEXT: ret2469 %c = add i64 %a, 82082470 ret i64 %c2471}2472 2473; Make sure we prefer LUI for the 8192 instead of using sh3add.2474define signext i32 @add8192_i32(i32 signext %a) {2475; CHECK-LABEL: add8192_i32:2476; CHECK: # %bb.0:2477; CHECK-NEXT: lui a1, 22478; CHECK-NEXT: addw a0, a0, a12479; CHECK-NEXT: ret2480 %c = add i32 %a, 81922481 ret i32 %c2482}2483 2484; Make sure we prefer LUI for the 8192 instead of using sh3add.2485define i64 @add8192(i64 %a) {2486; CHECK-LABEL: add8192:2487; CHECK: # %bb.0:2488; CHECK-NEXT: lui a1, 22489; CHECK-NEXT: add a0, a0, a12490; CHECK-NEXT: ret2491 %c = add i64 %a, 81922492 ret i64 %c2493}2494 2495define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {2496; RV64I-LABEL: addshl32_5_6:2497; RV64I: # %bb.0:2498; RV64I-NEXT: slli a0, a0, 52499; RV64I-NEXT: slli a1, a1, 62500; RV64I-NEXT: addw a0, a0, a12501; RV64I-NEXT: ret2502;2503; RV64ZBA-LABEL: addshl32_5_6:2504; RV64ZBA: # %bb.0:2505; RV64ZBA-NEXT: sh1add a0, a1, a02506; RV64ZBA-NEXT: slliw a0, a0, 52507; RV64ZBA-NEXT: ret2508;2509; RV64XANDESPERF-LABEL: addshl32_5_6:2510; RV64XANDESPERF: # %bb.0:2511; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a12512; RV64XANDESPERF-NEXT: slliw a0, a0, 52513; RV64XANDESPERF-NEXT: ret2514 %c = shl i32 %a, 52515 %d = shl i32 %b, 62516 %e = add i32 %c, %d2517 ret i32 %e2518}2519 2520define i64 @addshl64_5_6(i64 %a, i64 %b) {2521; RV64I-LABEL: addshl64_5_6:2522; RV64I: # %bb.0:2523; RV64I-NEXT: slli a0, a0, 52524; RV64I-NEXT: slli a1, a1, 62525; RV64I-NEXT: add a0, a0, a12526; RV64I-NEXT: ret2527;2528; RV64ZBA-LABEL: addshl64_5_6:2529; RV64ZBA: # %bb.0:2530; RV64ZBA-NEXT: sh1add a0, a1, a02531; RV64ZBA-NEXT: slli a0, a0, 52532; RV64ZBA-NEXT: ret2533;2534; RV64XANDESPERF-LABEL: addshl64_5_6:2535; RV64XANDESPERF: # %bb.0:2536; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a12537; RV64XANDESPERF-NEXT: slli a0, a0, 52538; RV64XANDESPERF-NEXT: ret2539 %c = shl i64 %a, 52540 %d = shl i64 %b, 62541 %e = add i64 %c, %d2542 ret i64 %e2543}2544 2545define signext i32 @addshl32_5_7(i32 signext %a, i32 signext %b) {2546; RV64I-LABEL: addshl32_5_7:2547; RV64I: # %bb.0:2548; RV64I-NEXT: slli a0, a0, 52549; RV64I-NEXT: slli a1, a1, 72550; RV64I-NEXT: addw a0, a0, a12551; RV64I-NEXT: ret2552;2553; RV64ZBA-LABEL: addshl32_5_7:2554; RV64ZBA: # %bb.0:2555; RV64ZBA-NEXT: sh2add a0, a1, a02556; RV64ZBA-NEXT: slliw a0, a0, 52557; RV64ZBA-NEXT: ret2558;2559; RV64XANDESPERF-LABEL: addshl32_5_7:2560; RV64XANDESPERF: # %bb.0:2561; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12562; RV64XANDESPERF-NEXT: slliw a0, a0, 52563; RV64XANDESPERF-NEXT: ret2564 %c = shl i32 %a, 52565 %d = shl i32 %b, 72566 %e = add i32 %c, %d2567 ret i32 %e2568}2569 2570define i64 @addshl64_5_7(i64 %a, i64 %b) {2571; RV64I-LABEL: addshl64_5_7:2572; RV64I: # %bb.0:2573; RV64I-NEXT: slli a0, a0, 52574; RV64I-NEXT: slli a1, a1, 72575; RV64I-NEXT: add a0, a0, a12576; RV64I-NEXT: ret2577;2578; RV64ZBA-LABEL: addshl64_5_7:2579; RV64ZBA: # %bb.0:2580; RV64ZBA-NEXT: sh2add a0, a1, a02581; RV64ZBA-NEXT: slli a0, a0, 52582; RV64ZBA-NEXT: ret2583;2584; RV64XANDESPERF-LABEL: addshl64_5_7:2585; RV64XANDESPERF: # %bb.0:2586; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a12587; RV64XANDESPERF-NEXT: slli a0, a0, 52588; RV64XANDESPERF-NEXT: ret2589 %c = shl i64 %a, 52590 %d = shl i64 %b, 72591 %e = add i64 %c, %d2592 ret i64 %e2593}2594 2595define signext i32 @addshl32_5_8(i32 signext %a, i32 signext %b) {2596; RV64I-LABEL: addshl32_5_8:2597; RV64I: # %bb.0:2598; RV64I-NEXT: slli a0, a0, 52599; RV64I-NEXT: slli a1, a1, 82600; RV64I-NEXT: addw a0, a0, a12601; RV64I-NEXT: ret2602;2603; RV64ZBA-LABEL: addshl32_5_8:2604; RV64ZBA: # %bb.0:2605; RV64ZBA-NEXT: sh3add a0, a1, a02606; RV64ZBA-NEXT: slliw a0, a0, 52607; RV64ZBA-NEXT: ret2608;2609; RV64XANDESPERF-LABEL: addshl32_5_8:2610; RV64XANDESPERF: # %bb.0:2611; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12612; RV64XANDESPERF-NEXT: slliw a0, a0, 52613; RV64XANDESPERF-NEXT: ret2614 %c = shl i32 %a, 52615 %d = shl i32 %b, 82616 %e = add i32 %c, %d2617 ret i32 %e2618}2619 2620define i64 @addshl64_5_8(i64 %a, i64 %b) {2621; RV64I-LABEL: addshl64_5_8:2622; RV64I: # %bb.0:2623; RV64I-NEXT: slli a0, a0, 52624; RV64I-NEXT: slli a1, a1, 82625; RV64I-NEXT: add a0, a0, a12626; RV64I-NEXT: ret2627;2628; RV64ZBA-LABEL: addshl64_5_8:2629; RV64ZBA: # %bb.0:2630; RV64ZBA-NEXT: sh3add a0, a1, a02631; RV64ZBA-NEXT: slli a0, a0, 52632; RV64ZBA-NEXT: ret2633;2634; RV64XANDESPERF-LABEL: addshl64_5_8:2635; RV64XANDESPERF: # %bb.0:2636; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12637; RV64XANDESPERF-NEXT: slli a0, a0, 52638; RV64XANDESPERF-NEXT: ret2639 %c = shl i64 %a, 52640 %d = shl i64 %b, 82641 %e = add i64 %c, %d2642 ret i64 %e2643}2644 2645; Make sure we use sext.b+slli+srli for Zba+Zbb.2646define zeroext i32 @sext_ashr_zext_i8(i8 %a) nounwind {2647; RV64I-LABEL: sext_ashr_zext_i8:2648; RV64I: # %bb.0:2649; RV64I-NEXT: slli a0, a0, 562650; RV64I-NEXT: srai a0, a0, 312651; RV64I-NEXT: srli a0, a0, 322652; RV64I-NEXT: ret2653;2654; RV64ZBANOZBB-LABEL: sext_ashr_zext_i8:2655; RV64ZBANOZBB: # %bb.0:2656; RV64ZBANOZBB-NEXT: slli a0, a0, 562657; RV64ZBANOZBB-NEXT: srai a0, a0, 312658; RV64ZBANOZBB-NEXT: srli a0, a0, 322659; RV64ZBANOZBB-NEXT: ret2660;2661; RV64ZBAZBB-LABEL: sext_ashr_zext_i8:2662; RV64ZBAZBB: # %bb.0:2663; RV64ZBAZBB-NEXT: sext.b a0, a02664; RV64ZBAZBB-NEXT: slli a0, a0, 232665; RV64ZBAZBB-NEXT: srli a0, a0, 322666; RV64ZBAZBB-NEXT: ret2667;2668; RV64XANDESPERF-LABEL: sext_ashr_zext_i8:2669; RV64XANDESPERF: # %bb.0:2670; RV64XANDESPERF-NEXT: nds.bfos a0, a0, 7, 02671; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 40, 92672; RV64XANDESPERF-NEXT: ret2673 %ext = sext i8 %a to i322674 %1 = ashr i32 %ext, 92675 ret i32 %12676}2677 2678define i64 @sh6_sh3_add1(i64 noundef %x, i64 noundef %y, i64 noundef %z) {2679; RV64I-LABEL: sh6_sh3_add1:2680; RV64I: # %bb.0: # %entry2681; RV64I-NEXT: slli a2, a2, 32682; RV64I-NEXT: slli a1, a1, 62683; RV64I-NEXT: add a1, a1, a22684; RV64I-NEXT: add a0, a1, a02685; RV64I-NEXT: ret2686;2687; RV64ZBA-LABEL: sh6_sh3_add1:2688; RV64ZBA: # %bb.0: # %entry2689; RV64ZBA-NEXT: sh3add a1, a1, a22690; RV64ZBA-NEXT: sh3add a0, a1, a02691; RV64ZBA-NEXT: ret2692;2693; RV64XANDESPERF-LABEL: sh6_sh3_add1:2694; RV64XANDESPERF: # %bb.0: # %entry2695; RV64XANDESPERF-NEXT: nds.lea.d a1, a2, a12696; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12697; RV64XANDESPERF-NEXT: ret2698entry:2699 %shl = shl i64 %z, 32700 %shl1 = shl i64 %y, 62701 %add = add nsw i64 %shl1, %shl2702 %add2 = add nsw i64 %add, %x2703 ret i64 %add22704}2705 2706define i64 @sh6_sh3_add2(i64 noundef %x, i64 noundef %y, i64 noundef %z) {2707; RV64I-LABEL: sh6_sh3_add2:2708; RV64I: # %bb.0: # %entry2709; RV64I-NEXT: slli a2, a2, 32710; RV64I-NEXT: slli a1, a1, 62711; RV64I-NEXT: add a0, a1, a02712; RV64I-NEXT: add a0, a0, a22713; RV64I-NEXT: ret2714;2715; RV64ZBA-LABEL: sh6_sh3_add2:2716; RV64ZBA: # %bb.0: # %entry2717; RV64ZBA-NEXT: sh3add a1, a1, a22718; RV64ZBA-NEXT: sh3add a0, a1, a02719; RV64ZBA-NEXT: ret2720;2721; RV64XANDESPERF-LABEL: sh6_sh3_add2:2722; RV64XANDESPERF: # %bb.0: # %entry2723; RV64XANDESPERF-NEXT: slli a1, a1, 62724; RV64XANDESPERF-NEXT: add a0, a1, a02725; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a22726; RV64XANDESPERF-NEXT: ret2727entry:2728 %shl = shl i64 %z, 32729 %shl1 = shl i64 %y, 62730 %add = add nsw i64 %shl1, %x2731 %add2 = add nsw i64 %add, %shl2732 ret i64 %add22733}2734 2735define i64 @sh6_sh3_add3(i64 noundef %x, i64 noundef %y, i64 noundef %z) {2736; RV64I-LABEL: sh6_sh3_add3:2737; RV64I: # %bb.0: # %entry2738; RV64I-NEXT: slli a2, a2, 32739; RV64I-NEXT: slli a1, a1, 62740; RV64I-NEXT: add a1, a1, a22741; RV64I-NEXT: add a0, a0, a12742; RV64I-NEXT: ret2743;2744; RV64ZBA-LABEL: sh6_sh3_add3:2745; RV64ZBA: # %bb.0: # %entry2746; RV64ZBA-NEXT: sh3add a1, a1, a22747; RV64ZBA-NEXT: sh3add a0, a1, a02748; RV64ZBA-NEXT: ret2749;2750; RV64XANDESPERF-LABEL: sh6_sh3_add3:2751; RV64XANDESPERF: # %bb.0: # %entry2752; RV64XANDESPERF-NEXT: nds.lea.d a1, a2, a12753; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a12754; RV64XANDESPERF-NEXT: ret2755entry:2756 %shl = shl i64 %z, 32757 %shl1 = shl i64 %y, 62758 %add = add nsw i64 %shl1, %shl2759 %add2 = add nsw i64 %x, %add2760 ret i64 %add22761}2762 2763define i64 @sh6_sh3_add4(i64 noundef %x, i64 noundef %y, i64 noundef %z) {2764; RV64I-LABEL: sh6_sh3_add4:2765; RV64I: # %bb.0: # %entry2766; RV64I-NEXT: slli a2, a2, 32767; RV64I-NEXT: slli a1, a1, 62768; RV64I-NEXT: add a0, a0, a22769; RV64I-NEXT: add a0, a0, a12770; RV64I-NEXT: ret2771;2772; RV64ZBA-LABEL: sh6_sh3_add4:2773; RV64ZBA: # %bb.0: # %entry2774; RV64ZBA-NEXT: slli a1, a1, 62775; RV64ZBA-NEXT: sh3add a0, a2, a02776; RV64ZBA-NEXT: add a0, a0, a12777; RV64ZBA-NEXT: ret2778;2779; RV64XANDESPERF-LABEL: sh6_sh3_add4:2780; RV64XANDESPERF: # %bb.0: # %entry2781; RV64XANDESPERF-NEXT: slli a1, a1, 62782; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a22783; RV64XANDESPERF-NEXT: add a0, a0, a12784; RV64XANDESPERF-NEXT: ret2785entry:2786 %shl = shl i64 %z, 32787 %shl1 = shl i64 %y, 62788 %add = add nsw i64 %x, %shl2789 %add2 = add nsw i64 %add, %shl12790 ret i64 %add22791}2792 2793; Make sure we use sext.h+slli+srli for Zba+Zbb.2794define zeroext i32 @sext_ashr_zext_i16(i16 %a) nounwind {2795; RV64I-LABEL: sext_ashr_zext_i16:2796; RV64I: # %bb.0:2797; RV64I-NEXT: slli a0, a0, 482798; RV64I-NEXT: srai a0, a0, 252799; RV64I-NEXT: srli a0, a0, 322800; RV64I-NEXT: ret2801;2802; RV64ZBANOZBB-LABEL: sext_ashr_zext_i16:2803; RV64ZBANOZBB: # %bb.0:2804; RV64ZBANOZBB-NEXT: slli a0, a0, 482805; RV64ZBANOZBB-NEXT: srai a0, a0, 252806; RV64ZBANOZBB-NEXT: srli a0, a0, 322807; RV64ZBANOZBB-NEXT: ret2808;2809; RV64ZBAZBB-LABEL: sext_ashr_zext_i16:2810; RV64ZBAZBB: # %bb.0:2811; RV64ZBAZBB-NEXT: sext.h a0, a02812; RV64ZBAZBB-NEXT: slli a0, a0, 232813; RV64ZBAZBB-NEXT: srli a0, a0, 322814; RV64ZBAZBB-NEXT: ret2815;2816; RV64XANDESPERF-LABEL: sext_ashr_zext_i16:2817; RV64XANDESPERF: # %bb.0:2818; RV64XANDESPERF-NEXT: nds.bfos a0, a0, 15, 02819; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 40, 92820; RV64XANDESPERF-NEXT: ret2821 %ext = sext i16 %a to i322822 %1 = ashr i32 %ext, 92823 ret i32 %12824}2825 2826; This the IR you get from InstCombine if take the difference of 2 pointers and2827; cast is to unsigned before using as an index.2828define signext i16 @sh1adduw_ptrdiff(i64 %diff, ptr %baseptr) {2829; RV64I-LABEL: sh1adduw_ptrdiff:2830; RV64I: # %bb.0:2831; RV64I-NEXT: li a2, 12832; RV64I-NEXT: slli a2, a2, 332833; RV64I-NEXT: addi a2, a2, -22834; RV64I-NEXT: and a0, a0, a22835; RV64I-NEXT: add a0, a1, a02836; RV64I-NEXT: lh a0, 0(a0)2837; RV64I-NEXT: ret2838;2839; RV64ZBA-LABEL: sh1adduw_ptrdiff:2840; RV64ZBA: # %bb.0:2841; RV64ZBA-NEXT: srli a0, a0, 12842; RV64ZBA-NEXT: sh1add.uw a0, a0, a12843; RV64ZBA-NEXT: lh a0, 0(a0)2844; RV64ZBA-NEXT: ret2845;2846; RV64XANDESPERF-LABEL: sh1adduw_ptrdiff:2847; RV64XANDESPERF: # %bb.0:2848; RV64XANDESPERF-NEXT: srli a0, a0, 12849; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a1, a02850; RV64XANDESPERF-NEXT: lh a0, 0(a0)2851; RV64XANDESPERF-NEXT: ret2852 %ptrdiff = lshr exact i64 %diff, 12853 %cast = and i64 %ptrdiff, 42949672952854 %ptr = getelementptr inbounds i16, ptr %baseptr, i64 %cast2855 %res = load i16, ptr %ptr2856 ret i16 %res2857}2858 2859define signext i32 @sh2adduw_ptrdiff(i64 %diff, ptr %baseptr) {2860; RV64I-LABEL: sh2adduw_ptrdiff:2861; RV64I: # %bb.0:2862; RV64I-NEXT: li a2, 12863; RV64I-NEXT: slli a2, a2, 342864; RV64I-NEXT: addi a2, a2, -42865; RV64I-NEXT: and a0, a0, a22866; RV64I-NEXT: add a0, a1, a02867; RV64I-NEXT: lw a0, 0(a0)2868; RV64I-NEXT: ret2869;2870; RV64ZBA-LABEL: sh2adduw_ptrdiff:2871; RV64ZBA: # %bb.0:2872; RV64ZBA-NEXT: srli a0, a0, 22873; RV64ZBA-NEXT: sh2add.uw a0, a0, a12874; RV64ZBA-NEXT: lw a0, 0(a0)2875; RV64ZBA-NEXT: ret2876;2877; RV64XANDESPERF-LABEL: sh2adduw_ptrdiff:2878; RV64XANDESPERF: # %bb.0:2879; RV64XANDESPERF-NEXT: srli a0, a0, 22880; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a1, a02881; RV64XANDESPERF-NEXT: lw a0, 0(a0)2882; RV64XANDESPERF-NEXT: ret2883 %ptrdiff = lshr exact i64 %diff, 22884 %cast = and i64 %ptrdiff, 42949672952885 %ptr = getelementptr inbounds i32, ptr %baseptr, i64 %cast2886 %res = load i32, ptr %ptr2887 ret i32 %res2888}2889 2890define i64 @sh3adduw_ptrdiff(i64 %diff, ptr %baseptr) {2891; RV64I-LABEL: sh3adduw_ptrdiff:2892; RV64I: # %bb.0:2893; RV64I-NEXT: li a2, 12894; RV64I-NEXT: slli a2, a2, 352895; RV64I-NEXT: addi a2, a2, -82896; RV64I-NEXT: and a0, a0, a22897; RV64I-NEXT: add a0, a1, a02898; RV64I-NEXT: ld a0, 0(a0)2899; RV64I-NEXT: ret2900;2901; RV64ZBA-LABEL: sh3adduw_ptrdiff:2902; RV64ZBA: # %bb.0:2903; RV64ZBA-NEXT: srli a0, a0, 32904; RV64ZBA-NEXT: sh3add.uw a0, a0, a12905; RV64ZBA-NEXT: ld a0, 0(a0)2906; RV64ZBA-NEXT: ret2907;2908; RV64XANDESPERF-LABEL: sh3adduw_ptrdiff:2909; RV64XANDESPERF: # %bb.0:2910; RV64XANDESPERF-NEXT: srli a0, a0, 32911; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a1, a02912; RV64XANDESPERF-NEXT: ld a0, 0(a0)2913; RV64XANDESPERF-NEXT: ret2914 %ptrdiff = lshr exact i64 %diff, 32915 %cast = and i64 %ptrdiff, 42949672952916 %ptr = getelementptr inbounds i64, ptr %baseptr, i64 %cast2917 %res = load i64, ptr %ptr2918 ret i64 %res2919}2920 2921define signext i16 @srliw_1_sh1add(ptr %0, i32 signext %1) {2922; RV64I-LABEL: srliw_1_sh1add:2923; RV64I: # %bb.0:2924; RV64I-NEXT: srliw a1, a1, 12925; RV64I-NEXT: slli a1, a1, 12926; RV64I-NEXT: add a0, a0, a12927; RV64I-NEXT: lh a0, 0(a0)2928; RV64I-NEXT: ret2929;2930; RV64ZBA-LABEL: srliw_1_sh1add:2931; RV64ZBA: # %bb.0:2932; RV64ZBA-NEXT: srliw a1, a1, 12933; RV64ZBA-NEXT: sh1add a0, a1, a02934; RV64ZBA-NEXT: lh a0, 0(a0)2935; RV64ZBA-NEXT: ret2936;2937; RV64XANDESPERF-LABEL: srliw_1_sh1add:2938; RV64XANDESPERF: # %bb.0:2939; RV64XANDESPERF-NEXT: srliw a1, a1, 12940; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a0, a12941; RV64XANDESPERF-NEXT: lh a0, 0(a0)2942; RV64XANDESPERF-NEXT: ret2943 %3 = lshr i32 %1, 12944 %4 = zext i32 %3 to i642945 %5 = getelementptr inbounds i16, ptr %0, i64 %42946 %6 = load i16, ptr %5, align 22947 ret i16 %62948}2949 2950define i128 @slliuw_ptrdiff(i64 %diff, ptr %baseptr) {2951; RV64I-LABEL: slliuw_ptrdiff:2952; RV64I: # %bb.0:2953; RV64I-NEXT: li a2, 12954; RV64I-NEXT: slli a2, a2, 362955; RV64I-NEXT: addi a2, a2, -162956; RV64I-NEXT: and a0, a0, a22957; RV64I-NEXT: add a1, a1, a02958; RV64I-NEXT: ld a0, 0(a1)2959; RV64I-NEXT: ld a1, 8(a1)2960; RV64I-NEXT: ret2961;2962; RV64ZBA-LABEL: slliuw_ptrdiff:2963; RV64ZBA: # %bb.0:2964; RV64ZBA-NEXT: srli a0, a0, 42965; RV64ZBA-NEXT: slli.uw a0, a0, 42966; RV64ZBA-NEXT: add a1, a1, a02967; RV64ZBA-NEXT: ld a0, 0(a1)2968; RV64ZBA-NEXT: ld a1, 8(a1)2969; RV64ZBA-NEXT: ret2970;2971; RV64XANDESPERF-LABEL: slliuw_ptrdiff:2972; RV64XANDESPERF: # %bb.0:2973; RV64XANDESPERF-NEXT: li a2, 12974; RV64XANDESPERF-NEXT: slli a2, a2, 362975; RV64XANDESPERF-NEXT: addi a2, a2, -162976; RV64XANDESPERF-NEXT: and a0, a0, a22977; RV64XANDESPERF-NEXT: add a1, a1, a02978; RV64XANDESPERF-NEXT: ld a0, 0(a1)2979; RV64XANDESPERF-NEXT: ld a1, 8(a1)2980; RV64XANDESPERF-NEXT: ret2981 %ptrdiff = lshr exact i64 %diff, 42982 %cast = and i64 %ptrdiff, 42949672952983 %ptr = getelementptr inbounds i128, ptr %baseptr, i64 %cast2984 %res = load i128, ptr %ptr2985 ret i128 %res2986}2987 2988define signext i32 @srliw_2_sh2add(ptr %0, i32 signext %1) {2989; RV64I-LABEL: srliw_2_sh2add:2990; RV64I: # %bb.0:2991; RV64I-NEXT: srliw a1, a1, 22992; RV64I-NEXT: slli a1, a1, 22993; RV64I-NEXT: add a0, a0, a12994; RV64I-NEXT: lw a0, 0(a0)2995; RV64I-NEXT: ret2996;2997; RV64ZBA-LABEL: srliw_2_sh2add:2998; RV64ZBA: # %bb.0:2999; RV64ZBA-NEXT: srliw a1, a1, 23000; RV64ZBA-NEXT: sh2add a0, a1, a03001; RV64ZBA-NEXT: lw a0, 0(a0)3002; RV64ZBA-NEXT: ret3003;3004; RV64XANDESPERF-LABEL: srliw_2_sh2add:3005; RV64XANDESPERF: # %bb.0:3006; RV64XANDESPERF-NEXT: srliw a1, a1, 23007; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a0, a13008; RV64XANDESPERF-NEXT: lw a0, 0(a0)3009; RV64XANDESPERF-NEXT: ret3010 %3 = lshr i32 %1, 23011 %4 = zext i32 %3 to i643012 %5 = getelementptr inbounds i32, ptr %0, i64 %43013 %6 = load i32, ptr %5, align 43014 ret i32 %63015}3016 3017define i64 @srliw_3_sh3add(ptr %0, i32 signext %1) {3018; RV64I-LABEL: srliw_3_sh3add:3019; RV64I: # %bb.0:3020; RV64I-NEXT: srliw a1, a1, 33021; RV64I-NEXT: slli a1, a1, 33022; RV64I-NEXT: add a0, a0, a13023; RV64I-NEXT: ld a0, 0(a0)3024; RV64I-NEXT: ret3025;3026; RV64ZBA-LABEL: srliw_3_sh3add:3027; RV64ZBA: # %bb.0:3028; RV64ZBA-NEXT: srliw a1, a1, 33029; RV64ZBA-NEXT: sh3add a0, a1, a03030; RV64ZBA-NEXT: ld a0, 0(a0)3031; RV64ZBA-NEXT: ret3032;3033; RV64XANDESPERF-LABEL: srliw_3_sh3add:3034; RV64XANDESPERF: # %bb.0:3035; RV64XANDESPERF-NEXT: srliw a1, a1, 33036; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a0, a13037; RV64XANDESPERF-NEXT: ld a0, 0(a0)3038; RV64XANDESPERF-NEXT: ret3039 %3 = lshr i32 %1, 33040 %4 = zext i32 %3 to i643041 %5 = getelementptr inbounds i64, ptr %0, i64 %43042 %6 = load i64, ptr %5, align 83043 ret i64 %63044}3045 3046define signext i32 @srliw_1_sh2add(ptr %0, i32 signext %1) {3047; RV64I-LABEL: srliw_1_sh2add:3048; RV64I: # %bb.0:3049; RV64I-NEXT: srliw a1, a1, 13050; RV64I-NEXT: slli a1, a1, 23051; RV64I-NEXT: add a0, a0, a13052; RV64I-NEXT: lw a0, 0(a0)3053; RV64I-NEXT: ret3054;3055; RV64ZBA-LABEL: srliw_1_sh2add:3056; RV64ZBA: # %bb.0:3057; RV64ZBA-NEXT: srliw a1, a1, 13058; RV64ZBA-NEXT: sh2add a0, a1, a03059; RV64ZBA-NEXT: lw a0, 0(a0)3060; RV64ZBA-NEXT: ret3061;3062; RV64XANDESPERF-LABEL: srliw_1_sh2add:3063; RV64XANDESPERF: # %bb.0:3064; RV64XANDESPERF-NEXT: srliw a1, a1, 13065; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13066; RV64XANDESPERF-NEXT: lw a0, 0(a0)3067; RV64XANDESPERF-NEXT: ret3068 %3 = lshr i32 %1, 13069 %4 = zext i32 %3 to i643070 %5 = getelementptr inbounds i32, ptr %0, i64 %43071 %6 = load i32, ptr %5, align 43072 ret i32 %63073}3074 3075define i64 @srliw_1_sh3add(ptr %0, i32 signext %1) {3076; RV64I-LABEL: srliw_1_sh3add:3077; RV64I: # %bb.0:3078; RV64I-NEXT: srliw a1, a1, 13079; RV64I-NEXT: slli a1, a1, 33080; RV64I-NEXT: add a0, a0, a13081; RV64I-NEXT: ld a0, 0(a0)3082; RV64I-NEXT: ret3083;3084; RV64ZBA-LABEL: srliw_1_sh3add:3085; RV64ZBA: # %bb.0:3086; RV64ZBA-NEXT: srliw a1, a1, 13087; RV64ZBA-NEXT: sh3add a0, a1, a03088; RV64ZBA-NEXT: ld a0, 0(a0)3089; RV64ZBA-NEXT: ret3090;3091; RV64XANDESPERF-LABEL: srliw_1_sh3add:3092; RV64XANDESPERF: # %bb.0:3093; RV64XANDESPERF-NEXT: srliw a1, a1, 13094; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13095; RV64XANDESPERF-NEXT: ld a0, 0(a0)3096; RV64XANDESPERF-NEXT: ret3097 %3 = lshr i32 %1, 13098 %4 = zext i32 %3 to i643099 %5 = getelementptr inbounds i64, ptr %0, i64 %43100 %6 = load i64, ptr %5, align 83101 ret i64 %63102}3103 3104define i64 @srliw_2_sh3add(ptr %0, i32 signext %1) {3105; RV64I-LABEL: srliw_2_sh3add:3106; RV64I: # %bb.0:3107; RV64I-NEXT: srliw a1, a1, 23108; RV64I-NEXT: slli a1, a1, 33109; RV64I-NEXT: add a0, a0, a13110; RV64I-NEXT: ld a0, 0(a0)3111; RV64I-NEXT: ret3112;3113; RV64ZBA-LABEL: srliw_2_sh3add:3114; RV64ZBA: # %bb.0:3115; RV64ZBA-NEXT: srliw a1, a1, 23116; RV64ZBA-NEXT: sh3add a0, a1, a03117; RV64ZBA-NEXT: ld a0, 0(a0)3118; RV64ZBA-NEXT: ret3119;3120; RV64XANDESPERF-LABEL: srliw_2_sh3add:3121; RV64XANDESPERF: # %bb.0:3122; RV64XANDESPERF-NEXT: srliw a1, a1, 23123; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13124; RV64XANDESPERF-NEXT: ld a0, 0(a0)3125; RV64XANDESPERF-NEXT: ret3126 %3 = lshr i32 %1, 23127 %4 = zext i32 %3 to i643128 %5 = getelementptr inbounds i64, ptr %0, i64 %43129 %6 = load i64, ptr %5, align 83130 ret i64 %63131}3132 3133define signext i16 @srliw_2_sh1add(ptr %0, i32 signext %1) {3134; RV64I-LABEL: srliw_2_sh1add:3135; RV64I: # %bb.0:3136; RV64I-NEXT: srliw a1, a1, 23137; RV64I-NEXT: slli a1, a1, 13138; RV64I-NEXT: add a0, a0, a13139; RV64I-NEXT: lh a0, 0(a0)3140; RV64I-NEXT: ret3141;3142; RV64ZBA-LABEL: srliw_2_sh1add:3143; RV64ZBA: # %bb.0:3144; RV64ZBA-NEXT: srliw a1, a1, 23145; RV64ZBA-NEXT: sh1add a0, a1, a03146; RV64ZBA-NEXT: lh a0, 0(a0)3147; RV64ZBA-NEXT: ret3148;3149; RV64XANDESPERF-LABEL: srliw_2_sh1add:3150; RV64XANDESPERF: # %bb.0:3151; RV64XANDESPERF-NEXT: srliw a1, a1, 23152; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a13153; RV64XANDESPERF-NEXT: lh a0, 0(a0)3154; RV64XANDESPERF-NEXT: ret3155 %3 = lshr i32 %1, 23156 %4 = zext i32 %3 to i643157 %5 = getelementptr inbounds i16, ptr %0, i64 %43158 %6 = load i16, ptr %5, align 23159 ret i16 %63160}3161 3162 3163define signext i32 @srliw_3_sh2add(ptr %0, i32 signext %1) {3164; RV64I-LABEL: srliw_3_sh2add:3165; RV64I: # %bb.0:3166; RV64I-NEXT: srliw a1, a1, 33167; RV64I-NEXT: slli a1, a1, 23168; RV64I-NEXT: add a0, a0, a13169; RV64I-NEXT: lw a0, 0(a0)3170; RV64I-NEXT: ret3171;3172; RV64ZBA-LABEL: srliw_3_sh2add:3173; RV64ZBA: # %bb.0:3174; RV64ZBA-NEXT: srliw a1, a1, 33175; RV64ZBA-NEXT: sh2add a0, a1, a03176; RV64ZBA-NEXT: lw a0, 0(a0)3177; RV64ZBA-NEXT: ret3178;3179; RV64XANDESPERF-LABEL: srliw_3_sh2add:3180; RV64XANDESPERF: # %bb.0:3181; RV64XANDESPERF-NEXT: srliw a1, a1, 33182; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13183; RV64XANDESPERF-NEXT: lw a0, 0(a0)3184; RV64XANDESPERF-NEXT: ret3185 %3 = lshr i32 %1, 33186 %4 = zext i32 %3 to i643187 %5 = getelementptr inbounds i32, ptr %0, i64 %43188 %6 = load i32, ptr %5, align 43189 ret i32 %63190}3191 3192define i64 @srliw_4_sh3add(ptr %0, i32 signext %1) {3193; RV64I-LABEL: srliw_4_sh3add:3194; RV64I: # %bb.0:3195; RV64I-NEXT: srliw a1, a1, 43196; RV64I-NEXT: slli a1, a1, 33197; RV64I-NEXT: add a0, a0, a13198; RV64I-NEXT: ld a0, 0(a0)3199; RV64I-NEXT: ret3200;3201; RV64ZBA-LABEL: srliw_4_sh3add:3202; RV64ZBA: # %bb.0:3203; RV64ZBA-NEXT: srliw a1, a1, 43204; RV64ZBA-NEXT: sh3add a0, a1, a03205; RV64ZBA-NEXT: ld a0, 0(a0)3206; RV64ZBA-NEXT: ret3207;3208; RV64XANDESPERF-LABEL: srliw_4_sh3add:3209; RV64XANDESPERF: # %bb.0:3210; RV64XANDESPERF-NEXT: srliw a1, a1, 43211; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13212; RV64XANDESPERF-NEXT: ld a0, 0(a0)3213; RV64XANDESPERF-NEXT: ret3214 %3 = lshr i32 %1, 43215 %4 = zext i32 %3 to i643216 %5 = getelementptr inbounds i64, ptr %0, i64 %43217 %6 = load i64, ptr %5, align 83218 ret i64 %63219}3220 3221define signext i32 @srli_1_sh2add(ptr %0, i64 %1) {3222; RV64I-LABEL: srli_1_sh2add:3223; RV64I: # %bb.0:3224; RV64I-NEXT: slli a1, a1, 13225; RV64I-NEXT: andi a1, a1, -43226; RV64I-NEXT: add a0, a0, a13227; RV64I-NEXT: lw a0, 0(a0)3228; RV64I-NEXT: ret3229;3230; RV64ZBA-LABEL: srli_1_sh2add:3231; RV64ZBA: # %bb.0:3232; RV64ZBA-NEXT: srli a1, a1, 13233; RV64ZBA-NEXT: sh2add a0, a1, a03234; RV64ZBA-NEXT: lw a0, 0(a0)3235; RV64ZBA-NEXT: ret3236;3237; RV64XANDESPERF-LABEL: srli_1_sh2add:3238; RV64XANDESPERF: # %bb.0:3239; RV64XANDESPERF-NEXT: srli a1, a1, 13240; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13241; RV64XANDESPERF-NEXT: lw a0, 0(a0)3242; RV64XANDESPERF-NEXT: ret3243 %3 = lshr i64 %1, 13244 %4 = getelementptr inbounds i32, ptr %0, i64 %33245 %5 = load i32, ptr %4, align 43246 ret i32 %53247}3248 3249define i64 @srli_2_sh3add(ptr %0, i64 %1) {3250; RV64I-LABEL: srli_2_sh3add:3251; RV64I: # %bb.0:3252; RV64I-NEXT: slli a1, a1, 13253; RV64I-NEXT: andi a1, a1, -83254; RV64I-NEXT: add a0, a0, a13255; RV64I-NEXT: ld a0, 0(a0)3256; RV64I-NEXT: ret3257;3258; RV64ZBA-LABEL: srli_2_sh3add:3259; RV64ZBA: # %bb.0:3260; RV64ZBA-NEXT: srli a1, a1, 23261; RV64ZBA-NEXT: sh3add a0, a1, a03262; RV64ZBA-NEXT: ld a0, 0(a0)3263; RV64ZBA-NEXT: ret3264;3265; RV64XANDESPERF-LABEL: srli_2_sh3add:3266; RV64XANDESPERF: # %bb.0:3267; RV64XANDESPERF-NEXT: srli a1, a1, 23268; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13269; RV64XANDESPERF-NEXT: ld a0, 0(a0)3270; RV64XANDESPERF-NEXT: ret3271 %3 = lshr i64 %1, 23272 %4 = getelementptr inbounds i64, ptr %0, i64 %33273 %5 = load i64, ptr %4, align 83274 ret i64 %53275}3276 3277define signext i16 @srli_2_sh1add(ptr %0, i64 %1) {3278; RV64I-LABEL: srli_2_sh1add:3279; RV64I: # %bb.0:3280; RV64I-NEXT: srli a1, a1, 13281; RV64I-NEXT: andi a1, a1, -23282; RV64I-NEXT: add a0, a0, a13283; RV64I-NEXT: lh a0, 0(a0)3284; RV64I-NEXT: ret3285;3286; RV64ZBA-LABEL: srli_2_sh1add:3287; RV64ZBA: # %bb.0:3288; RV64ZBA-NEXT: srli a1, a1, 23289; RV64ZBA-NEXT: sh1add a0, a1, a03290; RV64ZBA-NEXT: lh a0, 0(a0)3291; RV64ZBA-NEXT: ret3292;3293; RV64XANDESPERF-LABEL: srli_2_sh1add:3294; RV64XANDESPERF: # %bb.0:3295; RV64XANDESPERF-NEXT: srli a1, a1, 23296; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a13297; RV64XANDESPERF-NEXT: lh a0, 0(a0)3298; RV64XANDESPERF-NEXT: ret3299 %3 = lshr i64 %1, 23300 %4 = getelementptr inbounds i16, ptr %0, i64 %33301 %5 = load i16, ptr %4, align 23302 ret i16 %53303}3304 3305define signext i32 @srli_3_sh2add(ptr %0, i64 %1) {3306; RV64I-LABEL: srli_3_sh2add:3307; RV64I: # %bb.0:3308; RV64I-NEXT: srli a1, a1, 13309; RV64I-NEXT: andi a1, a1, -43310; RV64I-NEXT: add a0, a0, a13311; RV64I-NEXT: lw a0, 0(a0)3312; RV64I-NEXT: ret3313;3314; RV64ZBA-LABEL: srli_3_sh2add:3315; RV64ZBA: # %bb.0:3316; RV64ZBA-NEXT: srli a1, a1, 33317; RV64ZBA-NEXT: sh2add a0, a1, a03318; RV64ZBA-NEXT: lw a0, 0(a0)3319; RV64ZBA-NEXT: ret3320;3321; RV64XANDESPERF-LABEL: srli_3_sh2add:3322; RV64XANDESPERF: # %bb.0:3323; RV64XANDESPERF-NEXT: srli a1, a1, 33324; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13325; RV64XANDESPERF-NEXT: lw a0, 0(a0)3326; RV64XANDESPERF-NEXT: ret3327 %3 = lshr i64 %1, 33328 %4 = getelementptr inbounds i32, ptr %0, i64 %33329 %5 = load i32, ptr %4, align 43330 ret i32 %53331}3332 3333define i64 @srli_4_sh3add(ptr %0, i64 %1) {3334; RV64I-LABEL: srli_4_sh3add:3335; RV64I: # %bb.0:3336; RV64I-NEXT: srli a1, a1, 13337; RV64I-NEXT: andi a1, a1, -83338; RV64I-NEXT: add a0, a0, a13339; RV64I-NEXT: ld a0, 0(a0)3340; RV64I-NEXT: ret3341;3342; RV64ZBA-LABEL: srli_4_sh3add:3343; RV64ZBA: # %bb.0:3344; RV64ZBA-NEXT: srli a1, a1, 43345; RV64ZBA-NEXT: sh3add a0, a1, a03346; RV64ZBA-NEXT: ld a0, 0(a0)3347; RV64ZBA-NEXT: ret3348;3349; RV64XANDESPERF-LABEL: srli_4_sh3add:3350; RV64XANDESPERF: # %bb.0:3351; RV64XANDESPERF-NEXT: srli a1, a1, 43352; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13353; RV64XANDESPERF-NEXT: ld a0, 0(a0)3354; RV64XANDESPERF-NEXT: ret3355 %3 = lshr i64 %1, 43356 %4 = getelementptr inbounds i64, ptr %0, i64 %33357 %5 = load i64, ptr %4, align 83358 ret i64 %53359}3360 3361define signext i16 @shl_2_sh1adduw(ptr %0, i32 signext %1) {3362; RV64I-LABEL: shl_2_sh1adduw:3363; RV64I: # %bb.0:3364; RV64I-NEXT: slli a1, a1, 343365; RV64I-NEXT: srli a1, a1, 313366; RV64I-NEXT: add a0, a0, a13367; RV64I-NEXT: lh a0, 0(a0)3368; RV64I-NEXT: ret3369;3370; RV64ZBA-LABEL: shl_2_sh1adduw:3371; RV64ZBA: # %bb.0:3372; RV64ZBA-NEXT: slli a1, a1, 23373; RV64ZBA-NEXT: sh1add.uw a0, a1, a03374; RV64ZBA-NEXT: lh a0, 0(a0)3375; RV64ZBA-NEXT: ret3376;3377; RV64XANDESPERF-LABEL: shl_2_sh1adduw:3378; RV64XANDESPERF: # %bb.0:3379; RV64XANDESPERF-NEXT: slli a1, a1, 23380; RV64XANDESPERF-NEXT: nds.lea.h.ze a0, a0, a13381; RV64XANDESPERF-NEXT: lh a0, 0(a0)3382; RV64XANDESPERF-NEXT: ret3383 %3 = shl i32 %1, 23384 %4 = zext i32 %3 to i643385 %5 = getelementptr inbounds i16, ptr %0, i64 %43386 %6 = load i16, ptr %5, align 23387 ret i16 %63388}3389 3390define signext i32 @shl_16_sh2adduw(ptr %0, i32 signext %1) {3391; RV64I-LABEL: shl_16_sh2adduw:3392; RV64I: # %bb.0:3393; RV64I-NEXT: slli a1, a1, 483394; RV64I-NEXT: srli a1, a1, 303395; RV64I-NEXT: add a0, a0, a13396; RV64I-NEXT: lw a0, 0(a0)3397; RV64I-NEXT: ret3398;3399; RV64ZBA-LABEL: shl_16_sh2adduw:3400; RV64ZBA: # %bb.0:3401; RV64ZBA-NEXT: slli a1, a1, 163402; RV64ZBA-NEXT: sh2add.uw a0, a1, a03403; RV64ZBA-NEXT: lw a0, 0(a0)3404; RV64ZBA-NEXT: ret3405;3406; RV64XANDESPERF-LABEL: shl_16_sh2adduw:3407; RV64XANDESPERF: # %bb.0:3408; RV64XANDESPERF-NEXT: slli a1, a1, 163409; RV64XANDESPERF-NEXT: nds.lea.w.ze a0, a0, a13410; RV64XANDESPERF-NEXT: lw a0, 0(a0)3411; RV64XANDESPERF-NEXT: ret3412 %3 = shl i32 %1, 163413 %4 = zext i32 %3 to i643414 %5 = getelementptr inbounds i32, ptr %0, i64 %43415 %6 = load i32, ptr %5, align 43416 ret i32 %63417}3418 3419define i64 @shl_31_sh3adduw(ptr %0, i32 signext %1) {3420; RV64I-LABEL: shl_31_sh3adduw:3421; RV64I: # %bb.0:3422; RV64I-NEXT: slli a1, a1, 633423; RV64I-NEXT: srli a1, a1, 293424; RV64I-NEXT: add a0, a0, a13425; RV64I-NEXT: ld a0, 0(a0)3426; RV64I-NEXT: ret3427;3428; RV64ZBA-LABEL: shl_31_sh3adduw:3429; RV64ZBA: # %bb.0:3430; RV64ZBA-NEXT: slli a1, a1, 313431; RV64ZBA-NEXT: sh3add.uw a0, a1, a03432; RV64ZBA-NEXT: ld a0, 0(a0)3433; RV64ZBA-NEXT: ret3434;3435; RV64XANDESPERF-LABEL: shl_31_sh3adduw:3436; RV64XANDESPERF: # %bb.0:3437; RV64XANDESPERF-NEXT: slli a1, a1, 313438; RV64XANDESPERF-NEXT: nds.lea.d.ze a0, a0, a13439; RV64XANDESPERF-NEXT: ld a0, 0(a0)3440; RV64XANDESPERF-NEXT: ret3441 %3 = shl i32 %1, 313442 %4 = zext i32 %3 to i643443 %5 = getelementptr inbounds i64, ptr %0, i64 %43444 %6 = load i64, ptr %5, align 83445 ret i64 %63446}3447 3448define i64 @pack_i64(i64 %a, i64 %b) nounwind {3449; RV64I-LABEL: pack_i64:3450; RV64I: # %bb.0:3451; RV64I-NEXT: slli a0, a0, 323452; RV64I-NEXT: srli a0, a0, 323453; RV64I-NEXT: slli a1, a1, 323454; RV64I-NEXT: or a0, a1, a03455; RV64I-NEXT: ret3456;3457; RV64ZBA-LABEL: pack_i64:3458; RV64ZBA: # %bb.0:3459; RV64ZBA-NEXT: slli a1, a1, 323460; RV64ZBA-NEXT: add.uw a0, a0, a13461; RV64ZBA-NEXT: ret3462;3463; RV64XANDESPERF-LABEL: pack_i64:3464; RV64XANDESPERF: # %bb.0:3465; RV64XANDESPERF-NEXT: slli a1, a1, 323466; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a03467; RV64XANDESPERF-NEXT: ret3468 %shl = and i64 %a, 42949672953469 %shl1 = shl i64 %b, 323470 %or = or i64 %shl1, %shl3471 ret i64 %or3472}3473 3474define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {3475; RV64I-LABEL: pack_i64_2:3476; RV64I: # %bb.0:3477; RV64I-NEXT: slli a0, a0, 323478; RV64I-NEXT: srli a0, a0, 323479; RV64I-NEXT: slli a1, a1, 323480; RV64I-NEXT: or a0, a1, a03481; RV64I-NEXT: ret3482;3483; RV64ZBA-LABEL: pack_i64_2:3484; RV64ZBA: # %bb.0:3485; RV64ZBA-NEXT: slli a1, a1, 323486; RV64ZBA-NEXT: add.uw a0, a0, a13487; RV64ZBA-NEXT: ret3488;3489; RV64XANDESPERF-LABEL: pack_i64_2:3490; RV64XANDESPERF: # %bb.0:3491; RV64XANDESPERF-NEXT: slli a1, a1, 323492; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a03493; RV64XANDESPERF-NEXT: ret3494 %zexta = zext i32 %a to i643495 %zextb = zext i32 %b to i643496 %shl1 = shl i64 %zextb, 323497 %or = or i64 %shl1, %zexta3498 ret i64 %or3499}3500 3501define i64 @pack_i64_disjoint(i64 %a, i64 %b) nounwind {3502; RV64I-LABEL: pack_i64_disjoint:3503; RV64I: # %bb.0:3504; RV64I-NEXT: slli a0, a0, 323505; RV64I-NEXT: srli a0, a0, 323506; RV64I-NEXT: or a0, a1, a03507; RV64I-NEXT: ret3508;3509; RV64ZBA-LABEL: pack_i64_disjoint:3510; RV64ZBA: # %bb.0:3511; RV64ZBA-NEXT: add.uw a0, a0, a13512; RV64ZBA-NEXT: ret3513;3514; RV64XANDESPERF-LABEL: pack_i64_disjoint:3515; RV64XANDESPERF: # %bb.0:3516; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a03517; RV64XANDESPERF-NEXT: ret3518 %shl = and i64 %a, 42949672953519 %or = or disjoint i64 %b, %shl3520 ret i64 %or3521}3522 3523define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind {3524; RV64I-LABEL: pack_i64_disjoint_2:3525; RV64I: # %bb.0:3526; RV64I-NEXT: slli a0, a0, 323527; RV64I-NEXT: srli a0, a0, 323528; RV64I-NEXT: or a0, a1, a03529; RV64I-NEXT: ret3530;3531; RV64ZBA-LABEL: pack_i64_disjoint_2:3532; RV64ZBA: # %bb.0:3533; RV64ZBA-NEXT: add.uw a0, a0, a13534; RV64ZBA-NEXT: ret3535;3536; RV64XANDESPERF-LABEL: pack_i64_disjoint_2:3537; RV64XANDESPERF: # %bb.0:3538; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a1, a03539; RV64XANDESPERF-NEXT: ret3540 %zexta = zext i32 %a to i643541 %or = or disjoint i64 %b, %zexta3542 ret i64 %or3543}3544 3545define i8 @array_index_sh1_sh0(ptr %p, i64 %idx1, i64 %idx2) {3546; RV64I-LABEL: array_index_sh1_sh0:3547; RV64I: # %bb.0:3548; RV64I-NEXT: slli a1, a1, 13549; RV64I-NEXT: add a0, a0, a23550; RV64I-NEXT: add a0, a0, a13551; RV64I-NEXT: lbu a0, 0(a0)3552; RV64I-NEXT: ret3553;3554; RV64ZBA-LABEL: array_index_sh1_sh0:3555; RV64ZBA: # %bb.0:3556; RV64ZBA-NEXT: sh1add a0, a1, a03557; RV64ZBA-NEXT: add a0, a0, a23558; RV64ZBA-NEXT: lbu a0, 0(a0)3559; RV64ZBA-NEXT: ret3560;3561; RV64XANDESPERF-LABEL: array_index_sh1_sh0:3562; RV64XANDESPERF: # %bb.0:3563; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a13564; RV64XANDESPERF-NEXT: add a0, a0, a23565; RV64XANDESPERF-NEXT: lbu a0, 0(a0)3566; RV64XANDESPERF-NEXT: ret3567 %a = getelementptr inbounds [2 x i8], ptr %p, i64 %idx1, i64 %idx23568 %b = load i8, ptr %a, align 13569 ret i8 %b3570}3571 3572define i16 @array_index_sh1_sh1(ptr %p, i64 %idx1, i64 %idx2) {3573; RV64I-LABEL: array_index_sh1_sh1:3574; RV64I: # %bb.0:3575; RV64I-NEXT: slli a1, a1, 23576; RV64I-NEXT: add a0, a0, a13577; RV64I-NEXT: slli a2, a2, 13578; RV64I-NEXT: add a0, a0, a23579; RV64I-NEXT: lh a0, 0(a0)3580; RV64I-NEXT: ret3581;3582; RV64ZBA-LABEL: array_index_sh1_sh1:3583; RV64ZBA: # %bb.0:3584; RV64ZBA-NEXT: sh2add a0, a1, a03585; RV64ZBA-NEXT: sh1add a0, a2, a03586; RV64ZBA-NEXT: lh a0, 0(a0)3587; RV64ZBA-NEXT: ret3588;3589; RV64XANDESPERF-LABEL: array_index_sh1_sh1:3590; RV64XANDESPERF: # %bb.0:3591; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13592; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a23593; RV64XANDESPERF-NEXT: lh a0, 0(a0)3594; RV64XANDESPERF-NEXT: ret3595 %a = getelementptr inbounds [2 x i16], ptr %p, i64 %idx1, i64 %idx23596 %b = load i16, ptr %a, align 23597 ret i16 %b3598}3599 3600define i32 @array_index_sh1_sh2(ptr %p, i64 %idx1, i64 %idx2) {3601; RV64I-LABEL: array_index_sh1_sh2:3602; RV64I: # %bb.0:3603; RV64I-NEXT: slli a1, a1, 33604; RV64I-NEXT: add a0, a0, a13605; RV64I-NEXT: slli a2, a2, 23606; RV64I-NEXT: add a0, a0, a23607; RV64I-NEXT: lw a0, 0(a0)3608; RV64I-NEXT: ret3609;3610; RV64ZBA-LABEL: array_index_sh1_sh2:3611; RV64ZBA: # %bb.0:3612; RV64ZBA-NEXT: sh3add a0, a1, a03613; RV64ZBA-NEXT: sh2add a0, a2, a03614; RV64ZBA-NEXT: lw a0, 0(a0)3615; RV64ZBA-NEXT: ret3616;3617; RV64XANDESPERF-LABEL: array_index_sh1_sh2:3618; RV64XANDESPERF: # %bb.0:3619; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13620; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a23621; RV64XANDESPERF-NEXT: lw a0, 0(a0)3622; RV64XANDESPERF-NEXT: ret3623 %a = getelementptr inbounds [2 x i32], ptr %p, i64 %idx1, i64 %idx23624 %b = load i32, ptr %a, align 43625 ret i32 %b3626}3627 3628define i64 @array_index_sh1_sh3(ptr %p, i64 %idx1, i64 %idx2) {3629; RV64I-LABEL: array_index_sh1_sh3:3630; RV64I: # %bb.0:3631; RV64I-NEXT: slli a1, a1, 43632; RV64I-NEXT: add a0, a0, a13633; RV64I-NEXT: slli a2, a2, 33634; RV64I-NEXT: add a0, a0, a23635; RV64I-NEXT: ld a0, 0(a0)3636; RV64I-NEXT: ret3637;3638; RV64ZBA-LABEL: array_index_sh1_sh3:3639; RV64ZBA: # %bb.0:3640; RV64ZBA-NEXT: sh1add a1, a1, a23641; RV64ZBA-NEXT: sh3add a0, a1, a03642; RV64ZBA-NEXT: ld a0, 0(a0)3643; RV64ZBA-NEXT: ret3644;3645; RV64XANDESPERF-LABEL: array_index_sh1_sh3:3646; RV64XANDESPERF: # %bb.0:3647; RV64XANDESPERF-NEXT: slli a1, a1, 43648; RV64XANDESPERF-NEXT: add a0, a0, a13649; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a23650; RV64XANDESPERF-NEXT: ld a0, 0(a0)3651; RV64XANDESPERF-NEXT: ret3652 %a = getelementptr inbounds [2 x i64], ptr %p, i64 %idx1, i64 %idx23653 %b = load i64, ptr %a, align 83654 ret i64 %b3655}3656 3657define i8 @array_index_sh2_sh0(ptr %p, i64 %idx1, i64 %idx2) {3658; RV64I-LABEL: array_index_sh2_sh0:3659; RV64I: # %bb.0:3660; RV64I-NEXT: slli a1, a1, 23661; RV64I-NEXT: add a0, a0, a23662; RV64I-NEXT: add a0, a0, a13663; RV64I-NEXT: lbu a0, 0(a0)3664; RV64I-NEXT: ret3665;3666; RV64ZBA-LABEL: array_index_sh2_sh0:3667; RV64ZBA: # %bb.0:3668; RV64ZBA-NEXT: sh2add a0, a1, a03669; RV64ZBA-NEXT: add a0, a0, a23670; RV64ZBA-NEXT: lbu a0, 0(a0)3671; RV64ZBA-NEXT: ret3672;3673; RV64XANDESPERF-LABEL: array_index_sh2_sh0:3674; RV64XANDESPERF: # %bb.0:3675; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a13676; RV64XANDESPERF-NEXT: add a0, a0, a23677; RV64XANDESPERF-NEXT: lbu a0, 0(a0)3678; RV64XANDESPERF-NEXT: ret3679 %a = getelementptr inbounds [4 x i8], ptr %p, i64 %idx1, i64 %idx23680 %b = load i8, ptr %a, align 13681 ret i8 %b3682}3683 3684define i16 @array_index_sh2_sh1(ptr %p, i64 %idx1, i64 %idx2) {3685; RV64I-LABEL: array_index_sh2_sh1:3686; RV64I: # %bb.0:3687; RV64I-NEXT: slli a1, a1, 33688; RV64I-NEXT: add a0, a0, a13689; RV64I-NEXT: slli a2, a2, 13690; RV64I-NEXT: add a0, a0, a23691; RV64I-NEXT: lh a0, 0(a0)3692; RV64I-NEXT: ret3693;3694; RV64ZBA-LABEL: array_index_sh2_sh1:3695; RV64ZBA: # %bb.0:3696; RV64ZBA-NEXT: sh3add a0, a1, a03697; RV64ZBA-NEXT: sh1add a0, a2, a03698; RV64ZBA-NEXT: lh a0, 0(a0)3699; RV64ZBA-NEXT: ret3700;3701; RV64XANDESPERF-LABEL: array_index_sh2_sh1:3702; RV64XANDESPERF: # %bb.0:3703; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13704; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a23705; RV64XANDESPERF-NEXT: lh a0, 0(a0)3706; RV64XANDESPERF-NEXT: ret3707 %a = getelementptr inbounds [4 x i16], ptr %p, i64 %idx1, i64 %idx23708 %b = load i16, ptr %a, align 23709 ret i16 %b3710}3711 3712define i32 @array_index_sh2_sh2(ptr %p, i64 %idx1, i64 %idx2) {3713; RV64I-LABEL: array_index_sh2_sh2:3714; RV64I: # %bb.0:3715; RV64I-NEXT: slli a1, a1, 43716; RV64I-NEXT: add a0, a0, a13717; RV64I-NEXT: slli a2, a2, 23718; RV64I-NEXT: add a0, a0, a23719; RV64I-NEXT: lw a0, 0(a0)3720; RV64I-NEXT: ret3721;3722; RV64ZBA-LABEL: array_index_sh2_sh2:3723; RV64ZBA: # %bb.0:3724; RV64ZBA-NEXT: sh2add a1, a1, a23725; RV64ZBA-NEXT: sh2add a0, a1, a03726; RV64ZBA-NEXT: lw a0, 0(a0)3727; RV64ZBA-NEXT: ret3728;3729; RV64XANDESPERF-LABEL: array_index_sh2_sh2:3730; RV64XANDESPERF: # %bb.0:3731; RV64XANDESPERF-NEXT: slli a1, a1, 43732; RV64XANDESPERF-NEXT: add a0, a0, a13733; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a23734; RV64XANDESPERF-NEXT: lw a0, 0(a0)3735; RV64XANDESPERF-NEXT: ret3736 %a = getelementptr inbounds [4 x i32], ptr %p, i64 %idx1, i64 %idx23737 %b = load i32, ptr %a, align 43738 ret i32 %b3739}3740 3741define i64 @array_index_sh2_sh3(ptr %p, i64 %idx1, i64 %idx2) {3742; RV64I-LABEL: array_index_sh2_sh3:3743; RV64I: # %bb.0:3744; RV64I-NEXT: slli a1, a1, 53745; RV64I-NEXT: add a0, a0, a13746; RV64I-NEXT: slli a2, a2, 33747; RV64I-NEXT: add a0, a0, a23748; RV64I-NEXT: ld a0, 0(a0)3749; RV64I-NEXT: ret3750;3751; RV64ZBA-LABEL: array_index_sh2_sh3:3752; RV64ZBA: # %bb.0:3753; RV64ZBA-NEXT: sh2add a1, a1, a23754; RV64ZBA-NEXT: sh3add a0, a1, a03755; RV64ZBA-NEXT: ld a0, 0(a0)3756; RV64ZBA-NEXT: ret3757;3758; RV64XANDESPERF-LABEL: array_index_sh2_sh3:3759; RV64XANDESPERF: # %bb.0:3760; RV64XANDESPERF-NEXT: slli a1, a1, 53761; RV64XANDESPERF-NEXT: add a0, a0, a13762; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a23763; RV64XANDESPERF-NEXT: ld a0, 0(a0)3764; RV64XANDESPERF-NEXT: ret3765 %a = getelementptr inbounds [4 x i64], ptr %p, i64 %idx1, i64 %idx23766 %b = load i64, ptr %a, align 83767 ret i64 %b3768}3769 3770define i8 @array_index_sh3_sh0(ptr %p, i64 %idx1, i64 %idx2) {3771; RV64I-LABEL: array_index_sh3_sh0:3772; RV64I: # %bb.0:3773; RV64I-NEXT: slli a1, a1, 33774; RV64I-NEXT: add a0, a0, a23775; RV64I-NEXT: add a0, a0, a13776; RV64I-NEXT: lbu a0, 0(a0)3777; RV64I-NEXT: ret3778;3779; RV64ZBA-LABEL: array_index_sh3_sh0:3780; RV64ZBA: # %bb.0:3781; RV64ZBA-NEXT: sh3add a0, a1, a03782; RV64ZBA-NEXT: add a0, a0, a23783; RV64ZBA-NEXT: lbu a0, 0(a0)3784; RV64ZBA-NEXT: ret3785;3786; RV64XANDESPERF-LABEL: array_index_sh3_sh0:3787; RV64XANDESPERF: # %bb.0:3788; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a13789; RV64XANDESPERF-NEXT: add a0, a0, a23790; RV64XANDESPERF-NEXT: lbu a0, 0(a0)3791; RV64XANDESPERF-NEXT: ret3792 %a = getelementptr inbounds [8 x i8], ptr %p, i64 %idx1, i64 %idx23793 %b = load i8, ptr %a, align 13794 ret i8 %b3795}3796 3797define i16 @array_index_sh3_sh1(ptr %p, i64 %idx1, i64 %idx2) {3798; RV64I-LABEL: array_index_sh3_sh1:3799; RV64I: # %bb.0:3800; RV64I-NEXT: slli a1, a1, 43801; RV64I-NEXT: add a0, a0, a13802; RV64I-NEXT: slli a2, a2, 13803; RV64I-NEXT: add a0, a0, a23804; RV64I-NEXT: lh a0, 0(a0)3805; RV64I-NEXT: ret3806;3807; RV64ZBA-LABEL: array_index_sh3_sh1:3808; RV64ZBA: # %bb.0:3809; RV64ZBA-NEXT: sh3add a1, a1, a23810; RV64ZBA-NEXT: sh1add a0, a1, a03811; RV64ZBA-NEXT: lh a0, 0(a0)3812; RV64ZBA-NEXT: ret3813;3814; RV64XANDESPERF-LABEL: array_index_sh3_sh1:3815; RV64XANDESPERF: # %bb.0:3816; RV64XANDESPERF-NEXT: slli a1, a1, 43817; RV64XANDESPERF-NEXT: add a0, a0, a13818; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a23819; RV64XANDESPERF-NEXT: lh a0, 0(a0)3820; RV64XANDESPERF-NEXT: ret3821 %a = getelementptr inbounds [8 x i16], ptr %p, i64 %idx1, i64 %idx23822 %b = load i16, ptr %a, align 23823 ret i16 %b3824}3825 3826define i32 @array_index_sh3_sh2(ptr %p, i64 %idx1, i64 %idx2) {3827; RV64I-LABEL: array_index_sh3_sh2:3828; RV64I: # %bb.0:3829; RV64I-NEXT: slli a1, a1, 53830; RV64I-NEXT: add a0, a0, a13831; RV64I-NEXT: slli a2, a2, 23832; RV64I-NEXT: add a0, a0, a23833; RV64I-NEXT: lw a0, 0(a0)3834; RV64I-NEXT: ret3835;3836; RV64ZBA-LABEL: array_index_sh3_sh2:3837; RV64ZBA: # %bb.0:3838; RV64ZBA-NEXT: sh3add a1, a1, a23839; RV64ZBA-NEXT: sh2add a0, a1, a03840; RV64ZBA-NEXT: lw a0, 0(a0)3841; RV64ZBA-NEXT: ret3842;3843; RV64XANDESPERF-LABEL: array_index_sh3_sh2:3844; RV64XANDESPERF: # %bb.0:3845; RV64XANDESPERF-NEXT: slli a1, a1, 53846; RV64XANDESPERF-NEXT: add a0, a0, a13847; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a23848; RV64XANDESPERF-NEXT: lw a0, 0(a0)3849; RV64XANDESPERF-NEXT: ret3850 %a = getelementptr inbounds [8 x i32], ptr %p, i64 %idx1, i64 %idx23851 %b = load i32, ptr %a, align 43852 ret i32 %b3853}3854 3855define i64 @array_index_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {3856; RV64I-LABEL: array_index_sh3_sh3:3857; RV64I: # %bb.0:3858; RV64I-NEXT: slli a1, a1, 63859; RV64I-NEXT: add a0, a0, a13860; RV64I-NEXT: slli a2, a2, 33861; RV64I-NEXT: add a0, a0, a23862; RV64I-NEXT: ld a0, 0(a0)3863; RV64I-NEXT: ret3864;3865; RV64ZBA-LABEL: array_index_sh3_sh3:3866; RV64ZBA: # %bb.0:3867; RV64ZBA-NEXT: sh3add a1, a1, a23868; RV64ZBA-NEXT: sh3add a0, a1, a03869; RV64ZBA-NEXT: ld a0, 0(a0)3870; RV64ZBA-NEXT: ret3871;3872; RV64XANDESPERF-LABEL: array_index_sh3_sh3:3873; RV64XANDESPERF: # %bb.0:3874; RV64XANDESPERF-NEXT: slli a1, a1, 63875; RV64XANDESPERF-NEXT: add a0, a0, a13876; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a23877; RV64XANDESPERF-NEXT: ld a0, 0(a0)3878; RV64XANDESPERF-NEXT: ret3879 %a = getelementptr inbounds [8 x i64], ptr %p, i64 %idx1, i64 %idx23880 %b = load i64, ptr %a, align 83881 ret i64 %b3882}3883 3884; Similar to above, but with a lshr on one of the indices. This requires3885; special handling during isel to form a shift pair.3886define i64 @array_index_lshr_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {3887; RV64I-LABEL: array_index_lshr_sh3_sh3:3888; RV64I: # %bb.0:3889; RV64I-NEXT: srli a1, a1, 583890; RV64I-NEXT: slli a2, a2, 33891; RV64I-NEXT: slli a1, a1, 63892; RV64I-NEXT: add a0, a0, a23893; RV64I-NEXT: add a0, a0, a13894; RV64I-NEXT: ld a0, 0(a0)3895; RV64I-NEXT: ret3896;3897; RV64ZBA-LABEL: array_index_lshr_sh3_sh3:3898; RV64ZBA: # %bb.0:3899; RV64ZBA-NEXT: srli a1, a1, 583900; RV64ZBA-NEXT: sh3add a1, a1, a23901; RV64ZBA-NEXT: sh3add a0, a1, a03902; RV64ZBA-NEXT: ld a0, 0(a0)3903; RV64ZBA-NEXT: ret3904;3905; RV64XANDESPERF-LABEL: array_index_lshr_sh3_sh3:3906; RV64XANDESPERF: # %bb.0:3907; RV64XANDESPERF-NEXT: srli a1, a1, 583908; RV64XANDESPERF-NEXT: slli a1, a1, 63909; RV64XANDESPERF-NEXT: add a0, a0, a13910; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a23911; RV64XANDESPERF-NEXT: ld a0, 0(a0)3912; RV64XANDESPERF-NEXT: ret3913 %shr = lshr i64 %idx1, 583914 %a = getelementptr inbounds [8 x i64], ptr %p, i64 %shr, i64 %idx23915 %b = load i64, ptr %a, align 83916 ret i64 %b3917}3918 3919define i8 @array_index_sh4_sh0(ptr %p, i64 %idx1, i64 %idx2) {3920; CHECK-LABEL: array_index_sh4_sh0:3921; CHECK: # %bb.0:3922; CHECK-NEXT: slli a1, a1, 43923; CHECK-NEXT: add a0, a0, a23924; CHECK-NEXT: add a0, a0, a13925; CHECK-NEXT: lbu a0, 0(a0)3926; CHECK-NEXT: ret3927 %a = getelementptr inbounds [16 x i8], ptr %p, i64 %idx1, i64 %idx23928 %b = load i8, ptr %a, align 13929 ret i8 %b3930}3931 3932define i16 @array_index_sh4_sh1(ptr %p, i64 %idx1, i64 %idx2) {3933; RV64I-LABEL: array_index_sh4_sh1:3934; RV64I: # %bb.0:3935; RV64I-NEXT: slli a1, a1, 53936; RV64I-NEXT: add a0, a0, a13937; RV64I-NEXT: slli a2, a2, 13938; RV64I-NEXT: add a0, a0, a23939; RV64I-NEXT: lh a0, 0(a0)3940; RV64I-NEXT: ret3941;3942; RV64ZBA-LABEL: array_index_sh4_sh1:3943; RV64ZBA: # %bb.0:3944; RV64ZBA-NEXT: slli a1, a1, 53945; RV64ZBA-NEXT: add a0, a0, a13946; RV64ZBA-NEXT: sh1add a0, a2, a03947; RV64ZBA-NEXT: lh a0, 0(a0)3948; RV64ZBA-NEXT: ret3949;3950; RV64XANDESPERF-LABEL: array_index_sh4_sh1:3951; RV64XANDESPERF: # %bb.0:3952; RV64XANDESPERF-NEXT: slli a1, a1, 53953; RV64XANDESPERF-NEXT: add a0, a0, a13954; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a23955; RV64XANDESPERF-NEXT: lh a0, 0(a0)3956; RV64XANDESPERF-NEXT: ret3957 %a = getelementptr inbounds [16 x i16], ptr %p, i64 %idx1, i64 %idx23958 %b = load i16, ptr %a, align 23959 ret i16 %b3960}3961 3962define i32 @array_index_sh4_sh2(ptr %p, i64 %idx1, i64 %idx2) {3963; RV64I-LABEL: array_index_sh4_sh2:3964; RV64I: # %bb.0:3965; RV64I-NEXT: slli a1, a1, 63966; RV64I-NEXT: add a0, a0, a13967; RV64I-NEXT: slli a2, a2, 23968; RV64I-NEXT: add a0, a0, a23969; RV64I-NEXT: lw a0, 0(a0)3970; RV64I-NEXT: ret3971;3972; RV64ZBA-LABEL: array_index_sh4_sh2:3973; RV64ZBA: # %bb.0:3974; RV64ZBA-NEXT: slli a1, a1, 63975; RV64ZBA-NEXT: add a0, a0, a13976; RV64ZBA-NEXT: sh2add a0, a2, a03977; RV64ZBA-NEXT: lw a0, 0(a0)3978; RV64ZBA-NEXT: ret3979;3980; RV64XANDESPERF-LABEL: array_index_sh4_sh2:3981; RV64XANDESPERF: # %bb.0:3982; RV64XANDESPERF-NEXT: slli a1, a1, 63983; RV64XANDESPERF-NEXT: add a0, a0, a13984; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a23985; RV64XANDESPERF-NEXT: lw a0, 0(a0)3986; RV64XANDESPERF-NEXT: ret3987 %a = getelementptr inbounds [16 x i32], ptr %p, i64 %idx1, i64 %idx23988 %b = load i32, ptr %a, align 43989 ret i32 %b3990}3991 3992define i64 @array_index_sh4_sh3(ptr %p, i64 %idx1, i64 %idx2) {3993; RV64I-LABEL: array_index_sh4_sh3:3994; RV64I: # %bb.0:3995; RV64I-NEXT: slli a1, a1, 73996; RV64I-NEXT: add a0, a0, a13997; RV64I-NEXT: slli a2, a2, 33998; RV64I-NEXT: add a0, a0, a23999; RV64I-NEXT: ld a0, 0(a0)4000; RV64I-NEXT: ret4001;4002; RV64ZBA-LABEL: array_index_sh4_sh3:4003; RV64ZBA: # %bb.0:4004; RV64ZBA-NEXT: slli a1, a1, 74005; RV64ZBA-NEXT: add a0, a0, a14006; RV64ZBA-NEXT: sh3add a0, a2, a04007; RV64ZBA-NEXT: ld a0, 0(a0)4008; RV64ZBA-NEXT: ret4009;4010; RV64XANDESPERF-LABEL: array_index_sh4_sh3:4011; RV64XANDESPERF: # %bb.0:4012; RV64XANDESPERF-NEXT: slli a1, a1, 74013; RV64XANDESPERF-NEXT: add a0, a0, a14014; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a24015; RV64XANDESPERF-NEXT: ld a0, 0(a0)4016; RV64XANDESPERF-NEXT: ret4017 %a = getelementptr inbounds [16 x i64], ptr %p, i64 %idx1, i64 %idx24018 %b = load i64, ptr %a, align 84019 ret i64 %b4020}4021 4022define ptr @test_gep_gep_dont_crash(ptr %p, i64 %a1, i64 %a2) {4023; RV64I-LABEL: test_gep_gep_dont_crash:4024; RV64I: # %bb.0:4025; RV64I-NEXT: srliw a2, a2, 64026; RV64I-NEXT: slli a1, a1, 34027; RV64I-NEXT: slli a2, a2, 34028; RV64I-NEXT: add a0, a0, a14029; RV64I-NEXT: add a0, a0, a24030; RV64I-NEXT: ret4031;4032; RV64ZBA-LABEL: test_gep_gep_dont_crash:4033; RV64ZBA: # %bb.0:4034; RV64ZBA-NEXT: srliw a2, a2, 64035; RV64ZBA-NEXT: sh3add a0, a2, a04036; RV64ZBA-NEXT: sh3add a0, a1, a04037; RV64ZBA-NEXT: ret4038;4039; RV64XANDESPERF-LABEL: test_gep_gep_dont_crash:4040; RV64XANDESPERF: # %bb.0:4041; RV64XANDESPERF-NEXT: srliw a2, a2, 64042; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a24043; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a14044; RV64XANDESPERF-NEXT: ret4045 %lshr = lshr i64 %a2, 64046 %and = and i64 %lshr, 671088634047 %gep1 = getelementptr i64, ptr %p, i64 %and4048 %gep2 = getelementptr i64, ptr %gep1, i64 %a14049 ret ptr %gep24050}4051 4052define i64 @regression(i32 signext %x, i32 signext %y) {4053; RV64I-LABEL: regression:4054; RV64I: # %bb.0:4055; RV64I-NEXT: sub a0, a0, a14056; RV64I-NEXT: slli a0, a0, 324057; RV64I-NEXT: srli a1, a0, 294058; RV64I-NEXT: srli a0, a0, 284059; RV64I-NEXT: add a0, a0, a14060; RV64I-NEXT: ret4061;4062; RV64ZBA-LABEL: regression:4063; RV64ZBA: # %bb.0:4064; RV64ZBA-NEXT: sub a0, a0, a14065; RV64ZBA-NEXT: slli.uw a0, a0, 34066; RV64ZBA-NEXT: sh1add a0, a0, a04067; RV64ZBA-NEXT: ret4068;4069; RV64XANDESPERF-LABEL: regression:4070; RV64XANDESPERF: # %bb.0:4071; RV64XANDESPERF-NEXT: sub a0, a0, a14072; RV64XANDESPERF-NEXT: slli a0, a0, 324073; RV64XANDESPERF-NEXT: srli a0, a0, 294074; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a04075; RV64XANDESPERF-NEXT: ret4076 %sub = sub i32 %x, %y4077 %ext = zext i32 %sub to i644078 %res = mul nuw nsw i64 %ext, 244079 ret i64 %res4080}4081 4082define i64 @mul_neg1(i64 %a) {4083; CHECK-LABEL: mul_neg1:4084; CHECK: # %bb.0:4085; CHECK-NEXT: neg a0, a04086; CHECK-NEXT: ret4087 %c = mul i64 %a, -14088 ret i64 %c4089}4090 4091define i64 @mul_neg2(i64 %a) {4092; CHECK-LABEL: mul_neg2:4093; CHECK: # %bb.0:4094; CHECK-NEXT: slli a0, a0, 14095; CHECK-NEXT: neg a0, a04096; CHECK-NEXT: ret4097 %c = mul i64 %a, -24098 ret i64 %c4099}4100 4101define i64 @mul_neg3(i64 %a) {4102; RV64I-LABEL: mul_neg3:4103; RV64I: # %bb.0:4104; RV64I-NEXT: slli a1, a0, 14105; RV64I-NEXT: neg a0, a04106; RV64I-NEXT: sub a0, a0, a14107; RV64I-NEXT: ret4108;4109; RV64ZBA-LABEL: mul_neg3:4110; RV64ZBA: # %bb.0:4111; RV64ZBA-NEXT: sh1add a0, a0, a04112; RV64ZBA-NEXT: neg a0, a04113; RV64ZBA-NEXT: ret4114;4115; RV64XANDESPERF-LABEL: mul_neg3:4116; RV64XANDESPERF: # %bb.0:4117; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a04118; RV64XANDESPERF-NEXT: neg a0, a04119; RV64XANDESPERF-NEXT: ret4120 %c = mul i64 %a, -34121 ret i64 %c4122}4123 4124define i64 @mul_neg4(i64 %a) {4125; CHECK-LABEL: mul_neg4:4126; CHECK: # %bb.0:4127; CHECK-NEXT: slli a0, a0, 24128; CHECK-NEXT: neg a0, a04129; CHECK-NEXT: ret4130 %c = mul i64 %a, -44131 ret i64 %c4132}4133 4134define i64 @mul_neg5(i64 %a) {4135; RV64I-LABEL: mul_neg5:4136; RV64I: # %bb.0:4137; RV64I-NEXT: slli a1, a0, 24138; RV64I-NEXT: neg a0, a04139; RV64I-NEXT: sub a0, a0, a14140; RV64I-NEXT: ret4141;4142; RV64ZBA-LABEL: mul_neg5:4143; RV64ZBA: # %bb.0:4144; RV64ZBA-NEXT: sh2add a0, a0, a04145; RV64ZBA-NEXT: neg a0, a04146; RV64ZBA-NEXT: ret4147;4148; RV64XANDESPERF-LABEL: mul_neg5:4149; RV64XANDESPERF: # %bb.0:4150; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a04151; RV64XANDESPERF-NEXT: neg a0, a04152; RV64XANDESPERF-NEXT: ret4153 %c = mul i64 %a, -54154 ret i64 %c4155}4156 4157define i64 @mul_neg6(i64 %a) {4158; CHECK-LABEL: mul_neg6:4159; CHECK: # %bb.0:4160; CHECK-NEXT: li a1, -64161; CHECK-NEXT: mul a0, a0, a14162; CHECK-NEXT: ret4163 %c = mul i64 %a, -64164 ret i64 %c4165}4166 4167define i64 @mul_neg7(i64 %a) {4168; CHECK-LABEL: mul_neg7:4169; CHECK: # %bb.0:4170; CHECK-NEXT: slli a1, a0, 34171; CHECK-NEXT: sub a0, a0, a14172; CHECK-NEXT: ret4173 %c = mul i64 %a, -74174 ret i64 %c4175}4176 4177define i64 @mul_neg8(i64 %a) {4178; CHECK-LABEL: mul_neg8:4179; CHECK: # %bb.0:4180; CHECK-NEXT: slli a0, a0, 34181; CHECK-NEXT: neg a0, a04182; CHECK-NEXT: ret4183 %c = mul i64 %a, -84184 ret i64 %c4185}4186 4187define i64 @bext_mul12(i32 %1, i32 %2) {4188; RV64I-LABEL: bext_mul12:4189; RV64I: # %bb.0: # %entry4190; RV64I-NEXT: srlw a0, a0, a14191; RV64I-NEXT: andi a0, a0, 14192; RV64I-NEXT: slli a1, a0, 24193; RV64I-NEXT: slli a0, a0, 34194; RV64I-NEXT: or a0, a0, a14195; RV64I-NEXT: ret4196;4197; RV64ZBANOZBB-LABEL: bext_mul12:4198; RV64ZBANOZBB: # %bb.0: # %entry4199; RV64ZBANOZBB-NEXT: srlw a0, a0, a14200; RV64ZBANOZBB-NEXT: andi a0, a0, 14201; RV64ZBANOZBB-NEXT: sh1add a0, a0, a04202; RV64ZBANOZBB-NEXT: slli a0, a0, 24203; RV64ZBANOZBB-NEXT: ret4204;4205; RV64ZBAZBBNOZBS-LABEL: bext_mul12:4206; RV64ZBAZBBNOZBS: # %bb.0: # %entry4207; RV64ZBAZBBNOZBS-NEXT: srlw a0, a0, a14208; RV64ZBAZBBNOZBS-NEXT: andi a0, a0, 14209; RV64ZBAZBBNOZBS-NEXT: sh1add a0, a0, a04210; RV64ZBAZBBNOZBS-NEXT: slli a0, a0, 24211; RV64ZBAZBBNOZBS-NEXT: ret4212;4213; RV64ZBAZBBZBS-LABEL: bext_mul12:4214; RV64ZBAZBBZBS: # %bb.0: # %entry4215; RV64ZBAZBBZBS-NEXT: bext a0, a0, a14216; RV64ZBAZBBZBS-NEXT: sh1add a0, a0, a04217; RV64ZBAZBBZBS-NEXT: slli a0, a0, 24218; RV64ZBAZBBZBS-NEXT: ret4219;4220; RV64XANDESPERF-LABEL: bext_mul12:4221; RV64XANDESPERF: # %bb.0: # %entry4222; RV64XANDESPERF-NEXT: srlw a0, a0, a14223; RV64XANDESPERF-NEXT: andi a0, a0, 14224; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a04225; RV64XANDESPERF-NEXT: slli a0, a0, 24226; RV64XANDESPERF-NEXT: ret4227entry:4228 %3 = lshr i32 %1, %24229 %4 = and i32 %3, 14230 %5 = zext nneg i32 %4 to i644231 %6 = mul i64 %5, 124232 ret i64 %64233}4234 4235define i64 @bext_mul45(i32 %1, i32 %2) {4236; RV64I-LABEL: bext_mul45:4237; RV64I: # %bb.0: # %entry4238; RV64I-NEXT: srlw a0, a0, a14239; RV64I-NEXT: andi a0, a0, 14240; RV64I-NEXT: li a1, 454241; RV64I-NEXT: mul a0, a0, a14242; RV64I-NEXT: ret4243;4244; RV64ZBANOZBB-LABEL: bext_mul45:4245; RV64ZBANOZBB: # %bb.0: # %entry4246; RV64ZBANOZBB-NEXT: srlw a0, a0, a14247; RV64ZBANOZBB-NEXT: andi a0, a0, 14248; RV64ZBANOZBB-NEXT: sh2add a0, a0, a04249; RV64ZBANOZBB-NEXT: sh3add a0, a0, a04250; RV64ZBANOZBB-NEXT: ret4251;4252; RV64ZBAZBBNOZBS-LABEL: bext_mul45:4253; RV64ZBAZBBNOZBS: # %bb.0: # %entry4254; RV64ZBAZBBNOZBS-NEXT: srlw a0, a0, a14255; RV64ZBAZBBNOZBS-NEXT: andi a0, a0, 14256; RV64ZBAZBBNOZBS-NEXT: sh2add a0, a0, a04257; RV64ZBAZBBNOZBS-NEXT: sh3add a0, a0, a04258; RV64ZBAZBBNOZBS-NEXT: ret4259;4260; RV64ZBAZBBZBS-LABEL: bext_mul45:4261; RV64ZBAZBBZBS: # %bb.0: # %entry4262; RV64ZBAZBBZBS-NEXT: bext a0, a0, a14263; RV64ZBAZBBZBS-NEXT: sh2add a0, a0, a04264; RV64ZBAZBBZBS-NEXT: sh3add a0, a0, a04265; RV64ZBAZBBZBS-NEXT: ret4266;4267; RV64XANDESPERF-LABEL: bext_mul45:4268; RV64XANDESPERF: # %bb.0: # %entry4269; RV64XANDESPERF-NEXT: srlw a0, a0, a14270; RV64XANDESPERF-NEXT: andi a0, a0, 14271; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a04272; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a04273; RV64XANDESPERF-NEXT: ret4274entry:4275 %3 = lshr i32 %1, %24276 %4 = and i32 %3, 14277 %5 = zext nneg i32 %4 to i644278 %6 = mul i64 %5, 454279 ret i64 %64280}4281 4282define i64 @bext_mul132(i32 %1, i32 %2) {4283; RV64I-LABEL: bext_mul132:4284; RV64I: # %bb.0: # %entry4285; RV64I-NEXT: srlw a0, a0, a14286; RV64I-NEXT: andi a0, a0, 14287; RV64I-NEXT: slli a1, a0, 24288; RV64I-NEXT: slli a0, a0, 74289; RV64I-NEXT: or a0, a0, a14290; RV64I-NEXT: ret4291;4292; RV64ZBANOZBB-LABEL: bext_mul132:4293; RV64ZBANOZBB: # %bb.0: # %entry4294; RV64ZBANOZBB-NEXT: srlw a0, a0, a14295; RV64ZBANOZBB-NEXT: andi a0, a0, 14296; RV64ZBANOZBB-NEXT: slli a1, a0, 74297; RV64ZBANOZBB-NEXT: sh2add a0, a0, a14298; RV64ZBANOZBB-NEXT: ret4299;4300; RV64ZBAZBBNOZBS-LABEL: bext_mul132:4301; RV64ZBAZBBNOZBS: # %bb.0: # %entry4302; RV64ZBAZBBNOZBS-NEXT: srlw a0, a0, a14303; RV64ZBAZBBNOZBS-NEXT: andi a0, a0, 14304; RV64ZBAZBBNOZBS-NEXT: slli a1, a0, 74305; RV64ZBAZBBNOZBS-NEXT: sh2add a0, a0, a14306; RV64ZBAZBBNOZBS-NEXT: ret4307;4308; RV64ZBAZBBZBS-LABEL: bext_mul132:4309; RV64ZBAZBBZBS: # %bb.0: # %entry4310; RV64ZBAZBBZBS-NEXT: bext a0, a0, a14311; RV64ZBAZBBZBS-NEXT: slli a1, a0, 74312; RV64ZBAZBBZBS-NEXT: sh2add a0, a0, a14313; RV64ZBAZBBZBS-NEXT: ret4314;4315; RV64XANDESPERF-LABEL: bext_mul132:4316; RV64XANDESPERF: # %bb.0: # %entry4317; RV64XANDESPERF-NEXT: srlw a0, a0, a14318; RV64XANDESPERF-NEXT: andi a0, a0, 14319; RV64XANDESPERF-NEXT: slli a1, a0, 74320; RV64XANDESPERF-NEXT: nds.lea.w a0, a1, a04321; RV64XANDESPERF-NEXT: ret4322entry:4323 %3 = lshr i32 %1, %24324 %4 = and i32 %3, 14325 %5 = zext nneg i32 %4 to i644326 %6 = mul i64 %5, 1324327 ret i64 %64328}4329 4330define ptr @gep_lshr_i32(ptr %0, i64 %1) {4331; RV64I-LABEL: gep_lshr_i32:4332; RV64I: # %bb.0: # %entry4333; RV64I-NEXT: srli a1, a1, 24334; RV64I-NEXT: slli a1, a1, 324335; RV64I-NEXT: srli a2, a1, 284336; RV64I-NEXT: srli a1, a1, 264337; RV64I-NEXT: add a1, a1, a24338; RV64I-NEXT: add a0, a0, a14339; RV64I-NEXT: ret4340;4341; RV64ZBA-LABEL: gep_lshr_i32:4342; RV64ZBA: # %bb.0: # %entry4343; RV64ZBA-NEXT: srli a1, a1, 24344; RV64ZBA-NEXT: slli.uw a1, a1, 44345; RV64ZBA-NEXT: sh2add a1, a1, a14346; RV64ZBA-NEXT: add a0, a0, a14347; RV64ZBA-NEXT: ret4348;4349; RV64XANDESPERF-LABEL: gep_lshr_i32:4350; RV64XANDESPERF: # %bb.0: # %entry4351; RV64XANDESPERF-NEXT: slli a1, a1, 24352; RV64XANDESPERF-NEXT: li a2, 14353; RV64XANDESPERF-NEXT: slli a2, a2, 364354; RV64XANDESPERF-NEXT: addi a2, a2, -164355; RV64XANDESPERF-NEXT: and a1, a1, a24356; RV64XANDESPERF-NEXT: nds.lea.w a1, a1, a14357; RV64XANDESPERF-NEXT: add a0, a0, a14358; RV64XANDESPERF-NEXT: ret4359entry:4360 %2 = lshr exact i64 %1, 24361 %3 = and i64 %2, 42949672954362 %5 = getelementptr [80 x i8], ptr %0, i64 %34363 ret ptr %54364}4365 4366define i64 @srli_slliuw(i64 %1) {4367; RV64I-LABEL: srli_slliuw:4368; RV64I: # %bb.0: # %entry4369; RV64I-NEXT: slli a0, a0, 24370; RV64I-NEXT: li a1, 14371; RV64I-NEXT: slli a1, a1, 364372; RV64I-NEXT: addi a1, a1, -164373; RV64I-NEXT: and a0, a0, a14374; RV64I-NEXT: ret4375;4376; RV64ZBA-LABEL: srli_slliuw:4377; RV64ZBA: # %bb.0: # %entry4378; RV64ZBA-NEXT: srli a0, a0, 24379; RV64ZBA-NEXT: slli.uw a0, a0, 44380; RV64ZBA-NEXT: ret4381;4382; RV64XANDESPERF-LABEL: srli_slliuw:4383; RV64XANDESPERF: # %bb.0: # %entry4384; RV64XANDESPERF-NEXT: slli a0, a0, 24385; RV64XANDESPERF-NEXT: li a1, 14386; RV64XANDESPERF-NEXT: slli a1, a1, 364387; RV64XANDESPERF-NEXT: addi a1, a1, -164388; RV64XANDESPERF-NEXT: and a0, a0, a14389; RV64XANDESPERF-NEXT: ret4390entry:4391 %2 = lshr exact i64 %1, 24392 %3 = and i64 %2, 42949672954393 %4 = shl i64 %3, 44394 ret i64 %44395}4396 4397define i64 @srli_slliuw_canonical(i64 %0) {4398; RV64I-LABEL: srli_slliuw_canonical:4399; RV64I: # %bb.0: # %entry4400; RV64I-NEXT: slli a0, a0, 24401; RV64I-NEXT: li a1, 14402; RV64I-NEXT: slli a1, a1, 364403; RV64I-NEXT: addi a1, a1, -164404; RV64I-NEXT: and a0, a0, a14405; RV64I-NEXT: ret4406;4407; RV64ZBA-LABEL: srli_slliuw_canonical:4408; RV64ZBA: # %bb.0: # %entry4409; RV64ZBA-NEXT: srli a0, a0, 24410; RV64ZBA-NEXT: slli.uw a0, a0, 44411; RV64ZBA-NEXT: ret4412;4413; RV64XANDESPERF-LABEL: srli_slliuw_canonical:4414; RV64XANDESPERF: # %bb.0: # %entry4415; RV64XANDESPERF-NEXT: slli a0, a0, 24416; RV64XANDESPERF-NEXT: li a1, 14417; RV64XANDESPERF-NEXT: slli a1, a1, 364418; RV64XANDESPERF-NEXT: addi a1, a1, -164419; RV64XANDESPERF-NEXT: and a0, a0, a14420; RV64XANDESPERF-NEXT: ret4421entry:4422 %1 = shl i64 %0, 24423 %2 = and i64 %1, 687194767204424 ret i64 %24425}4426 4427; Make sure we don't accidentally use slli.uw with a shift of 32.4428define i64 @srli_slliuw_negative_test(i64 %0) {4429; CHECK-LABEL: srli_slliuw_negative_test:4430; CHECK: # %bb.0: # %entry4431; CHECK-NEXT: srli a0, a0, 64432; CHECK-NEXT: slli a0, a0, 324433; CHECK-NEXT: ret4434entry:4435 %1 = lshr i64 %0, 64436 %2 = shl i64 %1, 324437 ret i64 %24438}4439 4440define i64 @srli_slli_i16(i64 %1) {4441; CHECK-LABEL: srli_slli_i16:4442; CHECK: # %bb.0: # %entry4443; CHECK-NEXT: slli a0, a0, 24444; CHECK-NEXT: lui a1, 2564445; CHECK-NEXT: addi a1, a1, -164446; CHECK-NEXT: and a0, a0, a14447; CHECK-NEXT: ret4448entry:4449 %2 = lshr exact i64 %1, 24450 %3 = and i64 %2, 655354451 %4 = shl i64 %3, 44452 ret i64 %44453}4454 4455define i64 @srli_slliuw_2(i64 %1) {4456; RV64I-LABEL: srli_slliuw_2:4457; RV64I: # %bb.0: # %entry4458; RV64I-NEXT: srli a0, a0, 154459; RV64I-NEXT: li a1, 14460; RV64I-NEXT: slli a1, a1, 354461; RV64I-NEXT: addi a1, a1, -84462; RV64I-NEXT: and a0, a0, a14463; RV64I-NEXT: ret4464;4465; RV64ZBA-LABEL: srli_slliuw_2:4466; RV64ZBA: # %bb.0: # %entry4467; RV64ZBA-NEXT: srli a0, a0, 184468; RV64ZBA-NEXT: slli.uw a0, a0, 34469; RV64ZBA-NEXT: ret4470;4471; RV64XANDESPERF-LABEL: srli_slliuw_2:4472; RV64XANDESPERF: # %bb.0: # %entry4473; RV64XANDESPERF-NEXT: srli a0, a0, 154474; RV64XANDESPERF-NEXT: li a1, 14475; RV64XANDESPERF-NEXT: slli a1, a1, 354476; RV64XANDESPERF-NEXT: addi a1, a1, -84477; RV64XANDESPERF-NEXT: and a0, a0, a14478; RV64XANDESPERF-NEXT: ret4479entry:4480 %2 = lshr i64 %1, 184481 %3 = and i64 %2, 42949672954482 %4 = shl i64 %3, 34483 ret i64 %44484}4485 4486define i64 @srli_slliuw_canonical_2(i64 %0) {4487; RV64I-LABEL: srli_slliuw_canonical_2:4488; RV64I: # %bb.0: # %entry4489; RV64I-NEXT: srli a0, a0, 154490; RV64I-NEXT: li a1, 14491; RV64I-NEXT: slli a1, a1, 354492; RV64I-NEXT: addi a1, a1, -84493; RV64I-NEXT: and a0, a0, a14494; RV64I-NEXT: ret4495;4496; RV64ZBA-LABEL: srli_slliuw_canonical_2:4497; RV64ZBA: # %bb.0: # %entry4498; RV64ZBA-NEXT: srli a0, a0, 184499; RV64ZBA-NEXT: slli.uw a0, a0, 34500; RV64ZBA-NEXT: ret4501;4502; RV64XANDESPERF-LABEL: srli_slliuw_canonical_2:4503; RV64XANDESPERF: # %bb.0: # %entry4504; RV64XANDESPERF-NEXT: srli a0, a0, 154505; RV64XANDESPERF-NEXT: li a1, 14506; RV64XANDESPERF-NEXT: slli a1, a1, 354507; RV64XANDESPERF-NEXT: addi a1, a1, -84508; RV64XANDESPERF-NEXT: and a0, a0, a14509; RV64XANDESPERF-NEXT: ret4510entry:4511 %1 = lshr i64 %0, 154512 %2 = and i64 %1, 343597383604513 ret i64 %24514}4515 4516define ptr @srai_srli_sh3add(ptr %0, i64 %1) nounwind {4517; RV64I-LABEL: srai_srli_sh3add:4518; RV64I: # %bb.0: # %entry4519; RV64I-NEXT: srai a1, a1, 324520; RV64I-NEXT: srli a1, a1, 64521; RV64I-NEXT: slli a1, a1, 34522; RV64I-NEXT: add a0, a0, a14523; RV64I-NEXT: ret4524;4525; RV64ZBA-LABEL: srai_srli_sh3add:4526; RV64ZBA: # %bb.0: # %entry4527; RV64ZBA-NEXT: srai a1, a1, 324528; RV64ZBA-NEXT: srli a1, a1, 64529; RV64ZBA-NEXT: sh3add a0, a1, a04530; RV64ZBA-NEXT: ret4531;4532; RV64XANDESPERF-LABEL: srai_srli_sh3add:4533; RV64XANDESPERF: # %bb.0: # %entry4534; RV64XANDESPERF-NEXT: srai a1, a1, 324535; RV64XANDESPERF-NEXT: srli a1, a1, 64536; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a14537; RV64XANDESPERF-NEXT: ret4538entry:4539 %2 = ashr i64 %1, 324540 %3 = lshr i64 %2, 64541 %4 = getelementptr i64, ptr %0, i64 %34542 ret ptr %44543}4544 4545define ptr @srai_srli_slli(ptr %0, i64 %1) nounwind {4546; CHECK-LABEL: srai_srli_slli:4547; CHECK: # %bb.0: # %entry4548; CHECK-NEXT: srai a1, a1, 324549; CHECK-NEXT: srli a1, a1, 64550; CHECK-NEXT: slli a1, a1, 44551; CHECK-NEXT: add a0, a0, a14552; CHECK-NEXT: ret4553entry:4554 %2 = ashr i64 %1, 324555 %3 = lshr i64 %2, 64556 %4 = getelementptr i128, ptr %0, i64 %34557 ret ptr %44558}4559 4560; Negative to make sure the peephole added for srai_srli_slli and4561; srai_srli_sh3add doesn't break this.4562define i64 @srai_andi(i64 %x) nounwind {4563; CHECK-LABEL: srai_andi:4564; CHECK: # %bb.0: # %entry4565; CHECK-NEXT: srai a0, a0, 84566; CHECK-NEXT: andi a0, a0, -84567; CHECK-NEXT: ret4568entry:4569 %y = ashr i64 %x, 84570 %z = and i64 %y, -84571 ret i64 %z4572}4573 4574; Negative to make sure the peephole added for srai_srli_slli and4575; srai_srli_sh3add doesn't break this.4576define i64 @srai_lui_and(i64 %x) nounwind {4577; CHECK-LABEL: srai_lui_and:4578; CHECK: # %bb.0: # %entry4579; CHECK-NEXT: srai a0, a0, 84580; CHECK-NEXT: lui a1, 10485744581; CHECK-NEXT: and a0, a0, a14582; CHECK-NEXT: ret4583entry:4584 %y = ashr i64 %x, 84585 %z = and i64 %y, -81924586 ret i64 %z4587}4588 4589define i64 @add_u32simm32_zextw(i64 %x) nounwind {4590; RV64I-LABEL: add_u32simm32_zextw:4591; RV64I: # %bb.0: # %entry4592; RV64I-NEXT: li a1, 14593; RV64I-NEXT: slli a1, a1, 324594; RV64I-NEXT: addi a1, a1, -24595; RV64I-NEXT: add a0, a0, a14596; RV64I-NEXT: addi a1, a1, 14597; RV64I-NEXT: and a0, a0, a14598; RV64I-NEXT: ret4599;4600; RV64ZBA-LABEL: add_u32simm32_zextw:4601; RV64ZBA: # %bb.0: # %entry4602; RV64ZBA-NEXT: addi a0, a0, -24603; RV64ZBA-NEXT: zext.w a0, a04604; RV64ZBA-NEXT: ret4605;4606; RV64XANDESPERF-LABEL: add_u32simm32_zextw:4607; RV64XANDESPERF: # %bb.0: # %entry4608; RV64XANDESPERF-NEXT: li a1, -24609; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a14610; RV64XANDESPERF-NEXT: li a1, 14611; RV64XANDESPERF-NEXT: slli a1, a1, 324612; RV64XANDESPERF-NEXT: addi a1, a1, -24613; RV64XANDESPERF-NEXT: addi a1, a1, 14614; RV64XANDESPERF-NEXT: and a0, a0, a14615; RV64XANDESPERF-NEXT: ret4616entry:4617 %add = add i64 %x, 42949672944618 %and = and i64 %add, 42949672954619 ret i64 %and4620}4621 4622define ptr @shl_and_gep(ptr %p, i64 %i) {4623; RV64I-LABEL: shl_and_gep:4624; RV64I: # %bb.0:4625; RV64I-NEXT: srliw a1, a1, 24626; RV64I-NEXT: slli a1, a1, 34627; RV64I-NEXT: add a0, a0, a14628; RV64I-NEXT: ret4629;4630; RV64ZBA-LABEL: shl_and_gep:4631; RV64ZBA: # %bb.0:4632; RV64ZBA-NEXT: srliw a1, a1, 24633; RV64ZBA-NEXT: sh3add a0, a1, a04634; RV64ZBA-NEXT: ret4635;4636; RV64XANDESPERF-LABEL: shl_and_gep:4637; RV64XANDESPERF: # %bb.0:4638; RV64XANDESPERF-NEXT: srliw a1, a1, 24639; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a14640; RV64XANDESPERF-NEXT: ret4641 %shl = shl i64 %i, 14642 %and = and i64 %shl, 85899345844643 %gep = getelementptr i8, ptr %p, i64 %and4644 ret ptr %gep4645}4646 4647define ptr @shr_and_gep(ptr %p, i64 %i) {4648; RV64I-LABEL: shr_and_gep:4649; RV64I: # %bb.0:4650; RV64I-NEXT: srliw a1, a1, 64651; RV64I-NEXT: slli a1, a1, 14652; RV64I-NEXT: add a0, a0, a14653; RV64I-NEXT: ret4654;4655; RV64ZBA-LABEL: shr_and_gep:4656; RV64ZBA: # %bb.0:4657; RV64ZBA-NEXT: srliw a1, a1, 64658; RV64ZBA-NEXT: sh1add a0, a1, a04659; RV64ZBA-NEXT: ret4660;4661; RV64XANDESPERF-LABEL: shr_and_gep:4662; RV64XANDESPERF: # %bb.0:4663; RV64XANDESPERF-NEXT: srliw a1, a1, 64664; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a14665; RV64XANDESPERF-NEXT: ret4666 %lshr = lshr i64 %i, 64667 %and = and i64 %lshr, 671088634668 %gep = getelementptr i16, ptr %p, i64 %and4669 ret ptr %gep4670}4671 4672define ptr @slt_select_gep(ptr %p, i32 %y) {4673; RV64I-LABEL: slt_select_gep:4674; RV64I: # %bb.0:4675; RV64I-NEXT: srli a1, a1, 284676; RV64I-NEXT: andi a1, a1, 84677; RV64I-NEXT: add a0, a0, a14678; RV64I-NEXT: addi a0, a0, 164679; RV64I-NEXT: ret4680;4681; RV64ZBA-LABEL: slt_select_gep:4682; RV64ZBA: # %bb.0:4683; RV64ZBA-NEXT: srliw a1, a1, 314684; RV64ZBA-NEXT: sh3add a0, a1, a04685; RV64ZBA-NEXT: addi a0, a0, 164686; RV64ZBA-NEXT: ret4687;4688; RV64XANDESPERF-LABEL: slt_select_gep:4689; RV64XANDESPERF: # %bb.0:4690; RV64XANDESPERF-NEXT: srliw a1, a1, 314691; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a14692; RV64XANDESPERF-NEXT: addi a0, a0, 164693; RV64XANDESPERF-NEXT: ret4694 %cmp = icmp slt i32 %y, 04695 %select = select i1 %cmp, i64 24, i64 164696 %gep = getelementptr i8, ptr %p, i64 %select4697 ret ptr %gep4698}4699 4700define i32 @shr_and_add(i32 %x, i32 %y) {4701; RV64I-LABEL: shr_and_add:4702; RV64I: # %bb.0:4703; RV64I-NEXT: srliw a1, a1, 94704; RV64I-NEXT: slli a1, a1, 24705; RV64I-NEXT: addw a0, a0, a14706; RV64I-NEXT: ret4707;4708; RV64ZBA-LABEL: shr_and_add:4709; RV64ZBA: # %bb.0:4710; RV64ZBA-NEXT: srliw a1, a1, 94711; RV64ZBA-NEXT: sh2add a0, a1, a04712; RV64ZBA-NEXT: sext.w a0, a04713; RV64ZBA-NEXT: ret4714;4715; RV64XANDESPERF-LABEL: shr_and_add:4716; RV64XANDESPERF: # %bb.0:4717; RV64XANDESPERF-NEXT: srliw a1, a1, 94718; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a14719; RV64XANDESPERF-NEXT: sext.w a0, a04720; RV64XANDESPERF-NEXT: ret4721 %lshr = lshr i32 %y, 74722 %and = and i32 %lshr, 335544284723 %add = add i32 %x, %and4724 ret i32 %add4725}4726 4727define ptr @udiv1280_gep(ptr %p, i16 zeroext %i) {4728; RV64I-LABEL: udiv1280_gep:4729; RV64I: # %bb.0:4730; RV64I-NEXT: lui a2, 134731; RV64I-NEXT: addi a2, a2, -8194732; RV64I-NEXT: mul a1, a1, a24733; RV64I-NEXT: srliw a1, a1, 264734; RV64I-NEXT: slli a1, a1, 34735; RV64I-NEXT: add a0, a0, a14736; RV64I-NEXT: ret4737;4738; RV64ZBA-LABEL: udiv1280_gep:4739; RV64ZBA: # %bb.0:4740; RV64ZBA-NEXT: lui a2, 134741; RV64ZBA-NEXT: addi a2, a2, -8194742; RV64ZBA-NEXT: mul a1, a1, a24743; RV64ZBA-NEXT: srliw a1, a1, 264744; RV64ZBA-NEXT: sh3add a0, a1, a04745; RV64ZBA-NEXT: ret4746;4747; RV64XANDESPERF-LABEL: udiv1280_gep:4748; RV64XANDESPERF: # %bb.0:4749; RV64XANDESPERF-NEXT: lui a2, 134750; RV64XANDESPERF-NEXT: addi a2, a2, -8194751; RV64XANDESPERF-NEXT: mul a1, a1, a24752; RV64XANDESPERF-NEXT: srliw a1, a1, 264753; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a14754; RV64XANDESPERF-NEXT: ret4755 %udiv = udiv i16 %i, 12804756 %idx.ext = zext nneg i16 %udiv to i644757 %add.ptr = getelementptr i64, ptr %p, i64 %idx.ext4758 ret ptr %add.ptr4759}4760 4761define i64 @adduw_m1(i64 %x) {4762; RV64I-LABEL: adduw_m1:4763; RV64I: # %bb.0:4764; RV64I-NEXT: li a1, -14765; RV64I-NEXT: srli a1, a1, 324766; RV64I-NEXT: add a0, a0, a14767; RV64I-NEXT: ret4768;4769; RV64ZBA-LABEL: adduw_m1:4770; RV64ZBA: # %bb.0:4771; RV64ZBA-NEXT: li a1, -14772; RV64ZBA-NEXT: add.uw a0, a1, a04773; RV64ZBA-NEXT: ret4774;4775; RV64XANDESPERF-LABEL: adduw_m1:4776; RV64XANDESPERF: # %bb.0:4777; RV64XANDESPERF-NEXT: li a1, -14778; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a14779; RV64XANDESPERF-NEXT: ret4780 %a = add i64 %x, 42949672954781 ret i64 %a4782}4783 4784define i64 @adduw_m3(i64 %x) {4785; RV64I-LABEL: adduw_m3:4786; RV64I: # %bb.0:4787; RV64I-NEXT: li a1, 14788; RV64I-NEXT: slli a1, a1, 324789; RV64I-NEXT: addi a1, a1, -34790; RV64I-NEXT: add a0, a0, a14791; RV64I-NEXT: ret4792;4793; RV64ZBA-LABEL: adduw_m3:4794; RV64ZBA: # %bb.0:4795; RV64ZBA-NEXT: li a1, -34796; RV64ZBA-NEXT: add.uw a0, a1, a04797; RV64ZBA-NEXT: ret4798;4799; RV64XANDESPERF-LABEL: adduw_m3:4800; RV64XANDESPERF: # %bb.0:4801; RV64XANDESPERF-NEXT: li a1, -34802; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a14803; RV64XANDESPERF-NEXT: ret4804 %a = add i64 %x, 42949672934805 ret i64 %a4806}4807 4808define i64 @adduw_3shl30(i64 %x) {4809; RV64I-LABEL: adduw_3shl30:4810; RV64I: # %bb.0:4811; RV64I-NEXT: li a1, 34812; RV64I-NEXT: slli a1, a1, 304813; RV64I-NEXT: add a0, a0, a14814; RV64I-NEXT: ret4815;4816; RV64ZBA-LABEL: adduw_3shl30:4817; RV64ZBA: # %bb.0:4818; RV64ZBA-NEXT: lui a1, 7864324819; RV64ZBA-NEXT: add.uw a0, a1, a04820; RV64ZBA-NEXT: ret4821;4822; RV64XANDESPERF-LABEL: adduw_3shl30:4823; RV64XANDESPERF: # %bb.0:4824; RV64XANDESPERF-NEXT: lui a1, 7864324825; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a14826; RV64XANDESPERF-NEXT: ret4827 %a = add i64 %x, 32212254724828 ret i64 %a4829}4830 4831define i64 @adduw_m3_multiuse(i64 %x, i64 %y) {4832; RV64I-LABEL: adduw_m3_multiuse:4833; RV64I: # %bb.0:4834; RV64I-NEXT: li a2, 14835; RV64I-NEXT: slli a2, a2, 324836; RV64I-NEXT: addi a2, a2, -34837; RV64I-NEXT: add a0, a0, a24838; RV64I-NEXT: add a1, a1, a24839; RV64I-NEXT: or a0, a0, a14840; RV64I-NEXT: ret4841;4842; RV64ZBA-LABEL: adduw_m3_multiuse:4843; RV64ZBA: # %bb.0:4844; RV64ZBA-NEXT: li a2, -34845; RV64ZBA-NEXT: add.uw a0, a2, a04846; RV64ZBA-NEXT: add.uw a1, a2, a14847; RV64ZBA-NEXT: or a0, a0, a14848; RV64ZBA-NEXT: ret4849;4850; RV64XANDESPERF-LABEL: adduw_m3_multiuse:4851; RV64XANDESPERF: # %bb.0:4852; RV64XANDESPERF-NEXT: li a2, -34853; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a24854; RV64XANDESPERF-NEXT: nds.lea.b.ze a1, a1, a24855; RV64XANDESPERF-NEXT: or a0, a0, a14856; RV64XANDESPERF-NEXT: ret4857 %a = add i64 %x, 42949672934858 %b = add i64 %y, 42949672934859 %c = or i64 %a, %b4860 ret i64 %c4861}4862 4863define i64 @add_or_m3(i64 %x) {4864; RV64I-LABEL: add_or_m3:4865; RV64I: # %bb.0:4866; RV64I-NEXT: li a1, 14867; RV64I-NEXT: slli a1, a1, 324868; RV64I-NEXT: addi a1, a1, -34869; RV64I-NEXT: or a2, a0, a14870; RV64I-NEXT: add a0, a0, a14871; RV64I-NEXT: add a0, a0, a24872; RV64I-NEXT: ret4873;4874; RV64ZBA-LABEL: add_or_m3:4875; RV64ZBA: # %bb.0:4876; RV64ZBA-NEXT: li a1, -34877; RV64ZBA-NEXT: zext.w a1, a14878; RV64ZBA-NEXT: or a2, a0, a14879; RV64ZBA-NEXT: add a0, a0, a14880; RV64ZBA-NEXT: add a0, a0, a24881; RV64ZBA-NEXT: ret4882;4883; RV64XANDESPERF-LABEL: add_or_m3:4884; RV64XANDESPERF: # %bb.0:4885; RV64XANDESPERF-NEXT: li a1, 14886; RV64XANDESPERF-NEXT: slli a1, a1, 324887; RV64XANDESPERF-NEXT: addi a1, a1, -34888; RV64XANDESPERF-NEXT: or a2, a0, a14889; RV64XANDESPERF-NEXT: add a0, a0, a14890; RV64XANDESPERF-NEXT: add a0, a0, a24891; RV64XANDESPERF-NEXT: ret4892 %a = add i64 %x, 42949672934893 %o = or i64 %x, 42949672934894 %c = add i64 %a, %o4895 ret i64 %c4896}4897 4898define i64 @append_32ones(i64 %x) {4899; RV64I-LABEL: append_32ones:4900; RV64I: # %bb.0:4901; RV64I-NEXT: slli a0, a0, 324902; RV64I-NEXT: li a1, -14903; RV64I-NEXT: srli a1, a1, 324904; RV64I-NEXT: or a0, a0, a14905; RV64I-NEXT: ret4906;4907; RV64ZBA-LABEL: append_32ones:4908; RV64ZBA: # %bb.0:4909; RV64ZBA-NEXT: slli a0, a0, 324910; RV64ZBA-NEXT: li a1, -14911; RV64ZBA-NEXT: add.uw a0, a1, a04912; RV64ZBA-NEXT: ret4913;4914; RV64XANDESPERF-LABEL: append_32ones:4915; RV64XANDESPERF: # %bb.0:4916; RV64XANDESPERF-NEXT: slli a0, a0, 324917; RV64XANDESPERF-NEXT: li a1, -14918; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a14919; RV64XANDESPERF-NEXT: ret4920 %s = shl i64 %x, 324921 %o = or i64 %s, 42949672954922 ret i64 %o4923}4924 4925define i32 @select3(i1 zeroext %x) {4926; RV64I-LABEL: select3:4927; RV64I: # %bb.0:4928; RV64I-NEXT: neg a0, a04929; RV64I-NEXT: andi a0, a0, 34930; RV64I-NEXT: ret4931;4932; RV64ZBA-LABEL: select3:4933; RV64ZBA: # %bb.0:4934; RV64ZBA-NEXT: sh1add a0, a0, a04935; RV64ZBA-NEXT: ret4936;4937; RV64XANDESPERF-LABEL: select3:4938; RV64XANDESPERF: # %bb.0:4939; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a04940; RV64XANDESPERF-NEXT: ret4941 %select = select i1 %x, i32 3, i32 04942 ret i32 %select4943}4944 4945define i32 @select5(i1 zeroext %x) {4946; RV64I-LABEL: select5:4947; RV64I: # %bb.0:4948; RV64I-NEXT: neg a0, a04949; RV64I-NEXT: andi a0, a0, 54950; RV64I-NEXT: ret4951;4952; RV64ZBA-LABEL: select5:4953; RV64ZBA: # %bb.0:4954; RV64ZBA-NEXT: sh2add a0, a0, a04955; RV64ZBA-NEXT: ret4956;4957; RV64XANDESPERF-LABEL: select5:4958; RV64XANDESPERF: # %bb.0:4959; RV64XANDESPERF-NEXT: nds.lea.w a0, a0, a04960; RV64XANDESPERF-NEXT: ret4961 %select = select i1 %x, i32 5, i32 04962 ret i32 %select4963}4964 4965define i32 @select9(i1 zeroext %x) {4966; RV64I-LABEL: select9:4967; RV64I: # %bb.0:4968; RV64I-NEXT: neg a0, a04969; RV64I-NEXT: andi a0, a0, 94970; RV64I-NEXT: ret4971;4972; RV64ZBA-LABEL: select9:4973; RV64ZBA: # %bb.0:4974; RV64ZBA-NEXT: sh3add a0, a0, a04975; RV64ZBA-NEXT: ret4976;4977; RV64XANDESPERF-LABEL: select9:4978; RV64XANDESPERF: # %bb.0:4979; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a04980; RV64XANDESPERF-NEXT: ret4981 %select = select i1 %x, i32 9, i32 04982 ret i32 %select4983}4984 4985define ptr @shl_add_knownbits(ptr %p, i64 %i) {4986; RV64I-LABEL: shl_add_knownbits:4987; RV64I: # %bb.0:4988; RV64I-NEXT: slli a1, a1, 504989; RV64I-NEXT: srli a1, a1, 504990; RV64I-NEXT: slli a2, a1, 14991; RV64I-NEXT: slli a1, a1, 24992; RV64I-NEXT: add a1, a1, a24993; RV64I-NEXT: srli a1, a1, 34994; RV64I-NEXT: add a0, a0, a14995; RV64I-NEXT: ret4996;4997; RV64ZBA-LABEL: shl_add_knownbits:4998; RV64ZBA: # %bb.0:4999; RV64ZBA-NEXT: slli a1, a1, 505000; RV64ZBA-NEXT: srli a1, a1, 505001; RV64ZBA-NEXT: sh1add a1, a1, a15002; RV64ZBA-NEXT: srli a1, a1, 25003; RV64ZBA-NEXT: add a0, a0, a15004; RV64ZBA-NEXT: ret5005;5006; RV64XANDESPERF-LABEL: shl_add_knownbits:5007; RV64XANDESPERF: # %bb.0:5008; RV64XANDESPERF-NEXT: nds.bfoz a1, a1, 13, 05009; RV64XANDESPERF-NEXT: nds.lea.h a1, a1, a15010; RV64XANDESPERF-NEXT: srli a1, a1, 25011; RV64XANDESPERF-NEXT: add a0, a0, a15012; RV64XANDESPERF-NEXT: ret5013 %and = and i64 %i, 163835014 %mul = mul i64 %and, 65015 %shr = lshr i64 %mul, 35016 %r = getelementptr i8, ptr %p, i64 %shr5017 ret ptr %r5018}5019 5020define i64 @exactashr1mul6(i64 %a) {5021; RV64I-LABEL: exactashr1mul6:5022; RV64I: # %bb.0:5023; RV64I-NEXT: slli a1, a0, 15024; RV64I-NEXT: add a0, a1, a05025; RV64I-NEXT: ret5026;5027; RV64ZBA-LABEL: exactashr1mul6:5028; RV64ZBA: # %bb.0:5029; RV64ZBA-NEXT: sh1add a0, a0, a05030; RV64ZBA-NEXT: ret5031;5032; RV64XANDESPERF-LABEL: exactashr1mul6:5033; RV64XANDESPERF: # %bb.0:5034; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a05035; RV64XANDESPERF-NEXT: ret5036 %c = ashr exact i64 %a, 15037 %d = mul i64 %c, 65038 ret i64 %d5039}5040 5041define i64 @exactlshr3mul22(i64 %a) {5042; RV64I-LABEL: exactlshr3mul22:5043; RV64I: # %bb.0:5044; RV64I-NEXT: srli a0, a0, 35045; RV64I-NEXT: li a1, 225046; RV64I-NEXT: mul a0, a0, a15047; RV64I-NEXT: ret5048;5049; RV64ZBA-LABEL: exactlshr3mul22:5050; RV64ZBA: # %bb.0:5051; RV64ZBA-NEXT: srli a0, a0, 25052; RV64ZBA-NEXT: sh2add a1, a0, a05053; RV64ZBA-NEXT: sh1add a0, a1, a05054; RV64ZBA-NEXT: ret5055;5056; RV64XANDESPERF-LABEL: exactlshr3mul22:5057; RV64XANDESPERF: # %bb.0:5058; RV64XANDESPERF-NEXT: srli a0, a0, 25059; RV64XANDESPERF-NEXT: nds.lea.w a1, a0, a05060; RV64XANDESPERF-NEXT: nds.lea.h a0, a0, a15061; RV64XANDESPERF-NEXT: ret5062 %c = lshr exact i64 %a, 35063 %d = mul i64 %c, 225064 ret i64 %d5065}5066 5067define i64 @exactashr1mul36(i64 %a) {5068; RV64I-LABEL: exactashr1mul36:5069; RV64I: # %bb.0:5070; RV64I-NEXT: slli a1, a0, 15071; RV64I-NEXT: slli a0, a0, 45072; RV64I-NEXT: add a0, a0, a15073; RV64I-NEXT: ret5074;5075; RV64ZBA-LABEL: exactashr1mul36:5076; RV64ZBA: # %bb.0:5077; RV64ZBA-NEXT: slli a0, a0, 15078; RV64ZBA-NEXT: sh3add a0, a0, a05079; RV64ZBA-NEXT: ret5080;5081; RV64XANDESPERF-LABEL: exactashr1mul36:5082; RV64XANDESPERF: # %bb.0:5083; RV64XANDESPERF-NEXT: slli a0, a0, 15084; RV64XANDESPERF-NEXT: nds.lea.d a0, a0, a05085; RV64XANDESPERF-NEXT: ret5086 %c = ashr exact i64 %a, 15087 %d = mul i64 %c, 365088 ret i64 %d5089}5090