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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64ZBB4 5define signext i32 @orcb32(i32 signext %a) nounwind {6; RV64ZBB-LABEL: orcb32:7; RV64ZBB: # %bb.0:8; RV64ZBB-NEXT: orc.b a0, a09; RV64ZBB-NEXT: sext.w a0, a010; RV64ZBB-NEXT: ret11 %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)12 ret i32 %tmp13}14 15define zeroext i32 @orcb32_zext(i32 zeroext %a) nounwind {16; RV64ZBB-LABEL: orcb32_zext:17; RV64ZBB: # %bb.0:18; RV64ZBB-NEXT: orc.b a0, a019; RV64ZBB-NEXT: ret20 %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)21 ret i32 %tmp22}23 24; Second and+or is redundant with the first, make sure we remove them.25define signext i32 @orcb32_knownbits(i32 signext %a) nounwind {26; RV64ZBB-LABEL: orcb32_knownbits:27; RV64ZBB: # %bb.0:28; RV64ZBB-NEXT: lui a1, 104448029; RV64ZBB-NEXT: and a0, a0, a130; RV64ZBB-NEXT: lui a1, 408031; RV64ZBB-NEXT: orc.b a0, a032; RV64ZBB-NEXT: addi a1, a1, 25533; RV64ZBB-NEXT: or a0, a0, a134; RV64ZBB-NEXT: sext.w a0, a035; RV64ZBB-NEXT: ret36 %tmp = and i32 %a, 4278190080 ; 0xFF00000037 %tmp2 = or i32 %tmp, 8388609 ; 0x80000138 %tmp3 = call i32 @llvm.riscv.orc.b.i32(i32 %tmp2)39 %tmp4 = and i32 %tmp3, 4278190080 ; 0xFF00000040 %tmp5 = or i32 %tmp4, 16711935 ; 0xFF00FF41 ret i32 %tmp542}43 44define i64 @orcb64(i64 %a) nounwind {45; RV64ZBB-LABEL: orcb64:46; RV64ZBB: # %bb.0:47; RV64ZBB-NEXT: orc.b a0, a048; RV64ZBB-NEXT: ret49 %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)50 ret i64 %tmp51}52 53; Second and+or is redundant with the first, make sure we remove one of the ands54; and one of the ors.55define i64 @orcb64_knownbits(i64 %a) nounwind {56; RV64ZBB-LABEL: orcb64_knownbits:57; RV64ZBB: # %bb.0:58; RV64ZBB-NEXT: lui a1, 6553559; RV64ZBB-NEXT: lui a2, 408060; RV64ZBB-NEXT: slli a1, a1, 1261; RV64ZBB-NEXT: addi a2, a2, 25562; RV64ZBB-NEXT: and a0, a0, a163; RV64ZBB-NEXT: slli a1, a2, 4064; RV64ZBB-NEXT: orc.b a0, a065; RV64ZBB-NEXT: add a1, a2, a166; RV64ZBB-NEXT: or a0, a0, a167; RV64ZBB-NEXT: ret68 %tmp = and i64 %a, 1099494850560 ; 0x000000ffff00000069 %tmp2 = or i64 %tmp, 4611721202800525320 ; 0x400020000010000870 %tmp3 = call i64 @llvm.riscv.orc.b.i64(i64 %tmp2)71 %tmp4 = and i64 %tmp3, 1099494850560 ; 0x000000ffff00000072 %tmp5 = or i64 %tmp4, 18374966855153418495 ; 0xff00ff0000ff00ff73 ret i64 %tmp574}75