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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I4; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB6 7define signext i32 @ctlz_i32(i32 signext %a) nounwind {8; RV64I-LABEL: ctlz_i32:9; RV64I: # %bb.0:10; RV64I-NEXT: beqz a0, .LBB0_211; RV64I-NEXT: # %bb.1: # %cond.false12; RV64I-NEXT: srliw a1, a0, 113; RV64I-NEXT: lui a2, 34952514; RV64I-NEXT: or a0, a0, a115; RV64I-NEXT: addi a1, a2, 136516; RV64I-NEXT: srliw a2, a0, 217; RV64I-NEXT: or a0, a0, a218; RV64I-NEXT: srliw a2, a0, 419; RV64I-NEXT: or a0, a0, a220; RV64I-NEXT: srliw a2, a0, 821; RV64I-NEXT: or a0, a0, a222; RV64I-NEXT: srliw a2, a0, 1623; RV64I-NEXT: or a0, a0, a224; RV64I-NEXT: not a0, a025; RV64I-NEXT: srli a2, a0, 126; RV64I-NEXT: and a1, a2, a127; RV64I-NEXT: lui a2, 20971528; RV64I-NEXT: addi a2, a2, 81929; RV64I-NEXT: sub a0, a0, a130; RV64I-NEXT: and a1, a0, a231; RV64I-NEXT: srli a0, a0, 232; RV64I-NEXT: and a0, a0, a233; RV64I-NEXT: lui a2, 6168134; RV64I-NEXT: add a0, a1, a035; RV64I-NEXT: srli a1, a0, 436; RV64I-NEXT: add a0, a0, a137; RV64I-NEXT: addi a1, a2, -24138; RV64I-NEXT: and a0, a0, a139; RV64I-NEXT: slli a1, a0, 840; RV64I-NEXT: add a0, a0, a141; RV64I-NEXT: slli a1, a0, 1642; RV64I-NEXT: add a0, a0, a143; RV64I-NEXT: srliw a0, a0, 2444; RV64I-NEXT: ret45; RV64I-NEXT: .LBB0_2:46; RV64I-NEXT: li a0, 3247; RV64I-NEXT: ret48;49; RV64ZBB-LABEL: ctlz_i32:50; RV64ZBB: # %bb.0:51; RV64ZBB-NEXT: clzw a0, a052; RV64ZBB-NEXT: ret53 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)54 ret i32 %155}56 57define signext i32 @log2_i32(i32 signext %a) nounwind {58; RV64I-LABEL: log2_i32:59; RV64I: # %bb.0:60; RV64I-NEXT: beqz a0, .LBB1_261; RV64I-NEXT: # %bb.1: # %cond.false62; RV64I-NEXT: srliw a1, a0, 163; RV64I-NEXT: lui a2, 34952564; RV64I-NEXT: or a0, a0, a165; RV64I-NEXT: addi a1, a2, 136566; RV64I-NEXT: srliw a2, a0, 267; RV64I-NEXT: or a0, a0, a268; RV64I-NEXT: srliw a2, a0, 469; RV64I-NEXT: or a0, a0, a270; RV64I-NEXT: srliw a2, a0, 871; RV64I-NEXT: or a0, a0, a272; RV64I-NEXT: srliw a2, a0, 1673; RV64I-NEXT: or a0, a0, a274; RV64I-NEXT: not a0, a075; RV64I-NEXT: srli a2, a0, 176; RV64I-NEXT: and a1, a2, a177; RV64I-NEXT: lui a2, 20971578; RV64I-NEXT: addi a2, a2, 81979; RV64I-NEXT: sub a0, a0, a180; RV64I-NEXT: and a1, a0, a281; RV64I-NEXT: srli a0, a0, 282; RV64I-NEXT: and a0, a0, a283; RV64I-NEXT: lui a2, 6168184; RV64I-NEXT: add a0, a1, a085; RV64I-NEXT: srli a1, a0, 486; RV64I-NEXT: add a0, a0, a187; RV64I-NEXT: addi a1, a2, -24188; RV64I-NEXT: and a0, a0, a189; RV64I-NEXT: slli a1, a0, 890; RV64I-NEXT: add a0, a0, a191; RV64I-NEXT: slli a1, a0, 1692; RV64I-NEXT: add a0, a0, a193; RV64I-NEXT: srliw a0, a0, 2494; RV64I-NEXT: j .LBB1_395; RV64I-NEXT: .LBB1_2:96; RV64I-NEXT: li a0, 3297; RV64I-NEXT: .LBB1_3: # %cond.end98; RV64I-NEXT: li a1, 3199; RV64I-NEXT: sub a0, a1, a0100; RV64I-NEXT: ret101;102; RV64ZBB-LABEL: log2_i32:103; RV64ZBB: # %bb.0:104; RV64ZBB-NEXT: clzw a0, a0105; RV64ZBB-NEXT: li a1, 31106; RV64ZBB-NEXT: sub a0, a1, a0107; RV64ZBB-NEXT: ret108 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)109 %2 = sub i32 31, %1110 ret i32 %2111}112 113define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {114; RV64I-LABEL: log2_ceil_i32:115; RV64I: # %bb.0:116; RV64I-NEXT: addiw a1, a0, -1117; RV64I-NEXT: li a0, 32118; RV64I-NEXT: li a2, 32119; RV64I-NEXT: beqz a1, .LBB2_2120; RV64I-NEXT: # %bb.1: # %cond.false121; RV64I-NEXT: srliw a2, a1, 1122; RV64I-NEXT: lui a3, 349525123; RV64I-NEXT: or a1, a1, a2124; RV64I-NEXT: addi a2, a3, 1365125; RV64I-NEXT: srliw a3, a1, 2126; RV64I-NEXT: or a1, a1, a3127; RV64I-NEXT: srliw a3, a1, 4128; RV64I-NEXT: or a1, a1, a3129; RV64I-NEXT: srliw a3, a1, 8130; RV64I-NEXT: or a1, a1, a3131; RV64I-NEXT: srliw a3, a1, 16132; RV64I-NEXT: or a1, a1, a3133; RV64I-NEXT: not a1, a1134; RV64I-NEXT: srli a3, a1, 1135; RV64I-NEXT: and a2, a3, a2136; RV64I-NEXT: lui a3, 209715137; RV64I-NEXT: addi a3, a3, 819138; RV64I-NEXT: sub a1, a1, a2139; RV64I-NEXT: and a2, a1, a3140; RV64I-NEXT: srli a1, a1, 2141; RV64I-NEXT: and a1, a1, a3142; RV64I-NEXT: lui a3, 61681143; RV64I-NEXT: add a1, a2, a1144; RV64I-NEXT: srli a2, a1, 4145; RV64I-NEXT: add a1, a1, a2146; RV64I-NEXT: addi a2, a3, -241147; RV64I-NEXT: and a1, a1, a2148; RV64I-NEXT: slli a2, a1, 8149; RV64I-NEXT: add a1, a1, a2150; RV64I-NEXT: slli a2, a1, 16151; RV64I-NEXT: add a1, a1, a2152; RV64I-NEXT: srliw a2, a1, 24153; RV64I-NEXT: .LBB2_2: # %cond.end154; RV64I-NEXT: sub a0, a0, a2155; RV64I-NEXT: ret156;157; RV64ZBB-LABEL: log2_ceil_i32:158; RV64ZBB: # %bb.0:159; RV64ZBB-NEXT: addi a0, a0, -1160; RV64ZBB-NEXT: clzw a0, a0161; RV64ZBB-NEXT: li a1, 32162; RV64ZBB-NEXT: sub a0, a1, a0163; RV64ZBB-NEXT: ret164 %1 = sub i32 %a, 1165 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)166 %3 = sub i32 32, %2167 ret i32 %3168}169 170define signext i32 @findLastSet_i32(i32 signext %a) nounwind {171; RV64I-LABEL: findLastSet_i32:172; RV64I: # %bb.0:173; RV64I-NEXT: srliw a1, a0, 1174; RV64I-NEXT: lui a2, 349525175; RV64I-NEXT: or a1, a0, a1176; RV64I-NEXT: addi a2, a2, 1365177; RV64I-NEXT: srliw a3, a1, 2178; RV64I-NEXT: or a1, a1, a3179; RV64I-NEXT: srliw a3, a1, 4180; RV64I-NEXT: or a1, a1, a3181; RV64I-NEXT: srliw a3, a1, 8182; RV64I-NEXT: or a1, a1, a3183; RV64I-NEXT: srliw a3, a1, 16184; RV64I-NEXT: or a1, a1, a3185; RV64I-NEXT: not a1, a1186; RV64I-NEXT: srli a3, a1, 1187; RV64I-NEXT: and a2, a3, a2188; RV64I-NEXT: lui a3, 209715189; RV64I-NEXT: addi a3, a3, 819190; RV64I-NEXT: sub a1, a1, a2191; RV64I-NEXT: and a2, a1, a3192; RV64I-NEXT: srli a1, a1, 2193; RV64I-NEXT: and a1, a1, a3194; RV64I-NEXT: lui a3, 61681195; RV64I-NEXT: snez a0, a0196; RV64I-NEXT: addi a3, a3, -241197; RV64I-NEXT: add a1, a2, a1198; RV64I-NEXT: srli a2, a1, 4199; RV64I-NEXT: add a1, a1, a2200; RV64I-NEXT: and a1, a1, a3201; RV64I-NEXT: slli a2, a1, 8202; RV64I-NEXT: add a1, a1, a2203; RV64I-NEXT: slli a2, a1, 16204; RV64I-NEXT: add a1, a1, a2205; RV64I-NEXT: srliw a1, a1, 24206; RV64I-NEXT: xori a1, a1, 31207; RV64I-NEXT: addi a0, a0, -1208; RV64I-NEXT: or a0, a0, a1209; RV64I-NEXT: ret210;211; RV64ZBB-LABEL: findLastSet_i32:212; RV64ZBB: # %bb.0:213; RV64ZBB-NEXT: clzw a1, a0214; RV64ZBB-NEXT: snez a0, a0215; RV64ZBB-NEXT: xori a1, a1, 31216; RV64ZBB-NEXT: addi a0, a0, -1217; RV64ZBB-NEXT: or a0, a0, a1218; RV64ZBB-NEXT: ret219 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)220 %2 = xor i32 31, %1221 %3 = icmp eq i32 %a, 0222 %4 = select i1 %3, i32 -1, i32 %2223 ret i32 %4224}225 226define i32 @ctlz_lshr_i32(i32 signext %a) {227; RV64I-LABEL: ctlz_lshr_i32:228; RV64I: # %bb.0:229; RV64I-NEXT: srliw a0, a0, 1230; RV64I-NEXT: beqz a0, .LBB4_2231; RV64I-NEXT: # %bb.1: # %cond.false232; RV64I-NEXT: srliw a1, a0, 1233; RV64I-NEXT: lui a2, 349525234; RV64I-NEXT: or a0, a0, a1235; RV64I-NEXT: addi a1, a2, 1365236; RV64I-NEXT: srliw a2, a0, 2237; RV64I-NEXT: or a0, a0, a2238; RV64I-NEXT: srliw a2, a0, 4239; RV64I-NEXT: or a0, a0, a2240; RV64I-NEXT: srliw a2, a0, 8241; RV64I-NEXT: or a0, a0, a2242; RV64I-NEXT: srliw a2, a0, 16243; RV64I-NEXT: or a0, a0, a2244; RV64I-NEXT: not a0, a0245; RV64I-NEXT: srli a2, a0, 1246; RV64I-NEXT: and a1, a2, a1247; RV64I-NEXT: lui a2, 209715248; RV64I-NEXT: addi a2, a2, 819249; RV64I-NEXT: sub a0, a0, a1250; RV64I-NEXT: and a1, a0, a2251; RV64I-NEXT: srli a0, a0, 2252; RV64I-NEXT: and a0, a0, a2253; RV64I-NEXT: lui a2, 61681254; RV64I-NEXT: add a0, a1, a0255; RV64I-NEXT: srli a1, a0, 4256; RV64I-NEXT: add a0, a0, a1257; RV64I-NEXT: addi a1, a2, -241258; RV64I-NEXT: and a0, a0, a1259; RV64I-NEXT: slli a1, a0, 8260; RV64I-NEXT: add a0, a0, a1261; RV64I-NEXT: slli a1, a0, 16262; RV64I-NEXT: add a0, a0, a1263; RV64I-NEXT: srliw a0, a0, 24264; RV64I-NEXT: ret265; RV64I-NEXT: .LBB4_2:266; RV64I-NEXT: li a0, 32267; RV64I-NEXT: ret268;269; RV64ZBB-LABEL: ctlz_lshr_i32:270; RV64ZBB: # %bb.0:271; RV64ZBB-NEXT: srliw a0, a0, 1272; RV64ZBB-NEXT: clzw a0, a0273; RV64ZBB-NEXT: ret274 %1 = lshr i32 %a, 1275 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)276 ret i32 %2277}278 279define i64 @ctlz_i64(i64 %a) nounwind {280; RV64I-LABEL: ctlz_i64:281; RV64I: # %bb.0:282; RV64I-NEXT: beqz a0, .LBB5_2283; RV64I-NEXT: # %bb.1: # %cond.false284; RV64I-NEXT: srli a1, a0, 1285; RV64I-NEXT: lui a2, 349525286; RV64I-NEXT: lui a3, 209715287; RV64I-NEXT: or a0, a0, a1288; RV64I-NEXT: addi a1, a2, 1365289; RV64I-NEXT: addi a2, a3, 819290; RV64I-NEXT: srli a3, a0, 2291; RV64I-NEXT: or a0, a0, a3292; RV64I-NEXT: slli a3, a1, 32293; RV64I-NEXT: add a1, a1, a3294; RV64I-NEXT: slli a3, a2, 32295; RV64I-NEXT: add a2, a2, a3296; RV64I-NEXT: srli a3, a0, 4297; RV64I-NEXT: or a0, a0, a3298; RV64I-NEXT: srli a3, a0, 8299; RV64I-NEXT: or a0, a0, a3300; RV64I-NEXT: srli a3, a0, 16301; RV64I-NEXT: or a0, a0, a3302; RV64I-NEXT: srli a3, a0, 32303; RV64I-NEXT: or a0, a0, a3304; RV64I-NEXT: not a0, a0305; RV64I-NEXT: srli a3, a0, 1306; RV64I-NEXT: and a1, a3, a1307; RV64I-NEXT: lui a3, 61681308; RV64I-NEXT: addi a3, a3, -241309; RV64I-NEXT: sub a0, a0, a1310; RV64I-NEXT: and a1, a0, a2311; RV64I-NEXT: srli a0, a0, 2312; RV64I-NEXT: and a0, a0, a2313; RV64I-NEXT: slli a2, a3, 32314; RV64I-NEXT: add a0, a1, a0315; RV64I-NEXT: srli a1, a0, 4316; RV64I-NEXT: add a0, a0, a1317; RV64I-NEXT: add a2, a3, a2318; RV64I-NEXT: and a0, a0, a2319; RV64I-NEXT: slli a1, a0, 8320; RV64I-NEXT: add a0, a0, a1321; RV64I-NEXT: slli a1, a0, 16322; RV64I-NEXT: add a0, a0, a1323; RV64I-NEXT: slli a1, a0, 32324; RV64I-NEXT: add a0, a0, a1325; RV64I-NEXT: srli a0, a0, 56326; RV64I-NEXT: ret327; RV64I-NEXT: .LBB5_2:328; RV64I-NEXT: li a0, 64329; RV64I-NEXT: ret330;331; RV64ZBB-LABEL: ctlz_i64:332; RV64ZBB: # %bb.0:333; RV64ZBB-NEXT: clz a0, a0334; RV64ZBB-NEXT: ret335 %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)336 ret i64 %1337}338 339define signext i32 @cttz_i32(i32 signext %a) nounwind {340; RV64I-LABEL: cttz_i32:341; RV64I: # %bb.0:342; RV64I-NEXT: beqz a0, .LBB6_2343; RV64I-NEXT: # %bb.1: # %cond.false344; RV64I-NEXT: neg a1, a0345; RV64I-NEXT: and a0, a0, a1346; RV64I-NEXT: slli a1, a0, 6347; RV64I-NEXT: slli a2, a0, 8348; RV64I-NEXT: slli a3, a0, 10349; RV64I-NEXT: slli a4, a0, 12350; RV64I-NEXT: add a1, a1, a2351; RV64I-NEXT: slli a2, a0, 16352; RV64I-NEXT: sub a3, a3, a4353; RV64I-NEXT: slli a4, a0, 18354; RV64I-NEXT: sub a2, a2, a4355; RV64I-NEXT: slli a4, a0, 4356; RV64I-NEXT: sub a4, a0, a4357; RV64I-NEXT: add a1, a4, a1358; RV64I-NEXT: slli a4, a0, 14359; RV64I-NEXT: sub a3, a3, a4360; RV64I-NEXT: slli a4, a0, 23361; RV64I-NEXT: sub a2, a2, a4362; RV64I-NEXT: slli a0, a0, 27363; RV64I-NEXT: add a1, a1, a3364; RV64I-NEXT: add a0, a2, a0365; RV64I-NEXT: add a0, a1, a0366; RV64I-NEXT: srliw a0, a0, 27367; RV64I-NEXT: lui a1, %hi(.LCPI6_0)368; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)369; RV64I-NEXT: add a0, a1, a0370; RV64I-NEXT: lbu a0, 0(a0)371; RV64I-NEXT: ret372; RV64I-NEXT: .LBB6_2:373; RV64I-NEXT: li a0, 32374; RV64I-NEXT: ret375;376; RV64ZBB-LABEL: cttz_i32:377; RV64ZBB: # %bb.0:378; RV64ZBB-NEXT: ctzw a0, a0379; RV64ZBB-NEXT: ret380 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)381 ret i32 %1382}383 384define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {385; RV64I-LABEL: cttz_zero_undef_i32:386; RV64I: # %bb.0:387; RV64I-NEXT: neg a1, a0388; RV64I-NEXT: and a0, a0, a1389; RV64I-NEXT: slli a1, a0, 6390; RV64I-NEXT: slli a2, a0, 8391; RV64I-NEXT: slli a3, a0, 10392; RV64I-NEXT: slli a4, a0, 12393; RV64I-NEXT: add a1, a1, a2394; RV64I-NEXT: slli a2, a0, 16395; RV64I-NEXT: sub a3, a3, a4396; RV64I-NEXT: slli a4, a0, 18397; RV64I-NEXT: sub a2, a2, a4398; RV64I-NEXT: slli a4, a0, 4399; RV64I-NEXT: sub a4, a0, a4400; RV64I-NEXT: add a1, a4, a1401; RV64I-NEXT: slli a4, a0, 14402; RV64I-NEXT: sub a3, a3, a4403; RV64I-NEXT: slli a4, a0, 23404; RV64I-NEXT: sub a2, a2, a4405; RV64I-NEXT: slli a0, a0, 27406; RV64I-NEXT: add a1, a1, a3407; RV64I-NEXT: add a0, a2, a0408; RV64I-NEXT: add a0, a1, a0409; RV64I-NEXT: srliw a0, a0, 27410; RV64I-NEXT: lui a1, %hi(.LCPI7_0)411; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)412; RV64I-NEXT: add a0, a1, a0413; RV64I-NEXT: lbu a0, 0(a0)414; RV64I-NEXT: ret415;416; RV64ZBB-LABEL: cttz_zero_undef_i32:417; RV64ZBB: # %bb.0:418; RV64ZBB-NEXT: ctzw a0, a0419; RV64ZBB-NEXT: ret420 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)421 ret i32 %1422}423 424define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {425; RV64I-LABEL: findFirstSet_i32:426; RV64I: # %bb.0:427; RV64I-NEXT: neg a1, a0428; RV64I-NEXT: and a1, a0, a1429; RV64I-NEXT: slli a2, a1, 6430; RV64I-NEXT: slli a3, a1, 8431; RV64I-NEXT: slli a4, a1, 10432; RV64I-NEXT: slli a5, a1, 12433; RV64I-NEXT: add a2, a2, a3434; RV64I-NEXT: slli a3, a1, 16435; RV64I-NEXT: sub a4, a4, a5436; RV64I-NEXT: slli a5, a1, 18437; RV64I-NEXT: sub a3, a3, a5438; RV64I-NEXT: slli a5, a1, 4439; RV64I-NEXT: sub a5, a1, a5440; RV64I-NEXT: add a2, a5, a2441; RV64I-NEXT: slli a5, a1, 14442; RV64I-NEXT: sub a4, a4, a5443; RV64I-NEXT: slli a5, a1, 23444; RV64I-NEXT: sub a3, a3, a5445; RV64I-NEXT: slli a1, a1, 27446; RV64I-NEXT: add a2, a2, a4447; RV64I-NEXT: add a1, a3, a1448; RV64I-NEXT: add a1, a2, a1449; RV64I-NEXT: srliw a1, a1, 27450; RV64I-NEXT: lui a2, %hi(.LCPI8_0)451; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_0)452; RV64I-NEXT: add a1, a2, a1453; RV64I-NEXT: lbu a1, 0(a1)454; RV64I-NEXT: snez a0, a0455; RV64I-NEXT: addi a0, a0, -1456; RV64I-NEXT: or a0, a0, a1457; RV64I-NEXT: ret458;459; RV64ZBB-LABEL: findFirstSet_i32:460; RV64ZBB: # %bb.0:461; RV64ZBB-NEXT: ctzw a1, a0462; RV64ZBB-NEXT: snez a0, a0463; RV64ZBB-NEXT: addi a0, a0, -1464; RV64ZBB-NEXT: or a0, a0, a1465; RV64ZBB-NEXT: ret466 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)467 %2 = icmp eq i32 %a, 0468 %3 = select i1 %2, i32 -1, i32 %1469 ret i32 %3470}471 472define signext i32 @ffs_i32(i32 signext %a) nounwind {473; RV64I-LABEL: ffs_i32:474; RV64I: # %bb.0:475; RV64I-NEXT: neg a1, a0476; RV64I-NEXT: and a1, a0, a1477; RV64I-NEXT: slli a2, a1, 6478; RV64I-NEXT: slli a3, a1, 8479; RV64I-NEXT: slli a4, a1, 10480; RV64I-NEXT: slli a5, a1, 12481; RV64I-NEXT: add a2, a2, a3482; RV64I-NEXT: slli a3, a1, 16483; RV64I-NEXT: sub a4, a4, a5484; RV64I-NEXT: slli a5, a1, 18485; RV64I-NEXT: sub a3, a3, a5486; RV64I-NEXT: slli a5, a1, 4487; RV64I-NEXT: sub a5, a1, a5488; RV64I-NEXT: add a2, a5, a2489; RV64I-NEXT: slli a5, a1, 14490; RV64I-NEXT: sub a4, a4, a5491; RV64I-NEXT: slli a5, a1, 23492; RV64I-NEXT: sub a3, a3, a5493; RV64I-NEXT: add a2, a2, a4494; RV64I-NEXT: lui a4, %hi(.LCPI9_0)495; RV64I-NEXT: addi a4, a4, %lo(.LCPI9_0)496; RV64I-NEXT: slli a1, a1, 27497; RV64I-NEXT: add a1, a3, a1498; RV64I-NEXT: add a1, a2, a1499; RV64I-NEXT: srliw a1, a1, 27500; RV64I-NEXT: add a1, a4, a1501; RV64I-NEXT: lbu a1, 0(a1)502; RV64I-NEXT: seqz a0, a0503; RV64I-NEXT: addi a1, a1, 1504; RV64I-NEXT: addi a0, a0, -1505; RV64I-NEXT: and a0, a0, a1506; RV64I-NEXT: ret507;508; RV64ZBB-LABEL: ffs_i32:509; RV64ZBB: # %bb.0:510; RV64ZBB-NEXT: ctzw a1, a0511; RV64ZBB-NEXT: seqz a0, a0512; RV64ZBB-NEXT: addi a1, a1, 1513; RV64ZBB-NEXT: addi a0, a0, -1514; RV64ZBB-NEXT: and a0, a0, a1515; RV64ZBB-NEXT: ret516 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)517 %2 = add i32 %1, 1518 %3 = icmp eq i32 %a, 0519 %4 = select i1 %3, i32 0, i32 %2520 ret i32 %4521}522 523define i64 @cttz_i64(i64 %a) nounwind {524; RV64I-LABEL: cttz_i64:525; RV64I: # %bb.0:526; RV64I-NEXT: beqz a0, .LBB10_2527; RV64I-NEXT: # %bb.1: # %cond.false528; RV64I-NEXT: addi sp, sp, -16529; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill530; RV64I-NEXT: neg a1, a0531; RV64I-NEXT: and a0, a0, a1532; RV64I-NEXT: lui a1, %hi(.LCPI10_0)533; RV64I-NEXT: ld a1, %lo(.LCPI10_0)(a1)534; RV64I-NEXT: call __muldi3535; RV64I-NEXT: srli a0, a0, 58536; RV64I-NEXT: lui a1, %hi(.LCPI10_1)537; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_1)538; RV64I-NEXT: add a0, a1, a0539; RV64I-NEXT: lbu a0, 0(a0)540; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload541; RV64I-NEXT: addi sp, sp, 16542; RV64I-NEXT: ret543; RV64I-NEXT: .LBB10_2:544; RV64I-NEXT: li a0, 64545; RV64I-NEXT: ret546;547; RV64ZBB-LABEL: cttz_i64:548; RV64ZBB: # %bb.0:549; RV64ZBB-NEXT: ctz a0, a0550; RV64ZBB-NEXT: ret551 %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)552 ret i64 %1553}554 555define signext i32 @ctpop_i32(i32 signext %a) nounwind {556; RV64I-LABEL: ctpop_i32:557; RV64I: # %bb.0:558; RV64I-NEXT: srli a1, a0, 1559; RV64I-NEXT: lui a2, 349525560; RV64I-NEXT: addi a2, a2, 1365561; RV64I-NEXT: and a1, a1, a2562; RV64I-NEXT: lui a2, 209715563; RV64I-NEXT: addi a2, a2, 819564; RV64I-NEXT: sub a0, a0, a1565; RV64I-NEXT: and a1, a0, a2566; RV64I-NEXT: srli a0, a0, 2567; RV64I-NEXT: and a0, a0, a2568; RV64I-NEXT: lui a2, 61681569; RV64I-NEXT: add a0, a1, a0570; RV64I-NEXT: srli a1, a0, 4571; RV64I-NEXT: add a0, a0, a1572; RV64I-NEXT: addi a1, a2, -241573; RV64I-NEXT: and a0, a0, a1574; RV64I-NEXT: slli a1, a0, 8575; RV64I-NEXT: add a0, a0, a1576; RV64I-NEXT: slli a1, a0, 16577; RV64I-NEXT: add a0, a0, a1578; RV64I-NEXT: srliw a0, a0, 24579; RV64I-NEXT: ret580;581; RV64ZBB-LABEL: ctpop_i32:582; RV64ZBB: # %bb.0:583; RV64ZBB-NEXT: cpopw a0, a0584; RV64ZBB-NEXT: ret585 %1 = call i32 @llvm.ctpop.i32(i32 %a)586 ret i32 %1587}588 589define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind {590; RV64I-LABEL: ctpop_i32_ult_two:591; RV64I: # %bb.0:592; RV64I-NEXT: addiw a1, a0, -1593; RV64I-NEXT: and a0, a0, a1594; RV64I-NEXT: seqz a0, a0595; RV64I-NEXT: ret596;597; RV64ZBB-LABEL: ctpop_i32_ult_two:598; RV64ZBB: # %bb.0:599; RV64ZBB-NEXT: cpopw a0, a0600; RV64ZBB-NEXT: sltiu a0, a0, 2601; RV64ZBB-NEXT: ret602 %1 = call i32 @llvm.ctpop.i32(i32 %a)603 %2 = icmp ult i32 %1, 2604 ret i1 %2605}606 607define i1 @ctpop_i32_ugt_one(i32 signext %a) nounwind {608; RV64I-LABEL: ctpop_i32_ugt_one:609; RV64I: # %bb.0:610; RV64I-NEXT: addiw a1, a0, -1611; RV64I-NEXT: and a0, a0, a1612; RV64I-NEXT: snez a0, a0613; RV64I-NEXT: ret614;615; RV64ZBB-LABEL: ctpop_i32_ugt_one:616; RV64ZBB: # %bb.0:617; RV64ZBB-NEXT: cpopw a0, a0618; RV64ZBB-NEXT: sltiu a0, a0, 2619; RV64ZBB-NEXT: xori a0, a0, 1620; RV64ZBB-NEXT: ret621 %1 = call i32 @llvm.ctpop.i32(i32 %a)622 %2 = icmp ugt i32 %1, 1623 ret i1 %2624}625 626define i1 @ctpop_i32_eq_one(i32 signext %a) nounwind {627; RV64I-LABEL: ctpop_i32_eq_one:628; RV64I: # %bb.0:629; RV64I-NEXT: addiw a1, a0, -1630; RV64I-NEXT: xor a0, a0, a1631; RV64I-NEXT: sltu a0, a1, a0632; RV64I-NEXT: ret633;634; RV64ZBB-LABEL: ctpop_i32_eq_one:635; RV64ZBB: # %bb.0:636; RV64ZBB-NEXT: cpopw a0, a0637; RV64ZBB-NEXT: addi a0, a0, -1638; RV64ZBB-NEXT: seqz a0, a0639; RV64ZBB-NEXT: ret640 %1 = call i32 @llvm.ctpop.i32(i32 %a)641 %2 = icmp eq i32 %1, 1642 ret i1 %2643}644 645define i1 @ctpop_i32_ne_one(i32 signext %a) nounwind {646; RV64I-LABEL: ctpop_i32_ne_one:647; RV64I: # %bb.0:648; RV64I-NEXT: addiw a1, a0, -1649; RV64I-NEXT: xor a0, a0, a1650; RV64I-NEXT: sltu a0, a1, a0651; RV64I-NEXT: xori a0, a0, 1652; RV64I-NEXT: ret653;654; RV64ZBB-LABEL: ctpop_i32_ne_one:655; RV64ZBB: # %bb.0:656; RV64ZBB-NEXT: cpopw a0, a0657; RV64ZBB-NEXT: addi a0, a0, -1658; RV64ZBB-NEXT: snez a0, a0659; RV64ZBB-NEXT: ret660 %1 = call i32 @llvm.ctpop.i32(i32 %a)661 %2 = icmp ne i32 %1, 1662 ret i1 %2663}664 665define signext i32 @ctpop_i32_load(ptr %p) nounwind {666; RV64I-LABEL: ctpop_i32_load:667; RV64I: # %bb.0:668; RV64I-NEXT: lw a0, 0(a0)669; RV64I-NEXT: lui a1, 349525670; RV64I-NEXT: addi a1, a1, 1365671; RV64I-NEXT: srli a2, a0, 1672; RV64I-NEXT: and a1, a2, a1673; RV64I-NEXT: lui a2, 209715674; RV64I-NEXT: addi a2, a2, 819675; RV64I-NEXT: sub a0, a0, a1676; RV64I-NEXT: and a1, a0, a2677; RV64I-NEXT: srli a0, a0, 2678; RV64I-NEXT: and a0, a0, a2679; RV64I-NEXT: lui a2, 61681680; RV64I-NEXT: add a0, a1, a0681; RV64I-NEXT: srli a1, a0, 4682; RV64I-NEXT: add a0, a0, a1683; RV64I-NEXT: addi a1, a2, -241684; RV64I-NEXT: and a0, a0, a1685; RV64I-NEXT: slli a1, a0, 8686; RV64I-NEXT: add a0, a0, a1687; RV64I-NEXT: slli a1, a0, 16688; RV64I-NEXT: add a0, a0, a1689; RV64I-NEXT: srliw a0, a0, 24690; RV64I-NEXT: ret691;692; RV64ZBB-LABEL: ctpop_i32_load:693; RV64ZBB: # %bb.0:694; RV64ZBB-NEXT: lw a0, 0(a0)695; RV64ZBB-NEXT: cpopw a0, a0696; RV64ZBB-NEXT: ret697 %a = load i32, ptr %p698 %1 = call i32 @llvm.ctpop.i32(i32 %a)699 ret i32 %1700}701 702define <2 x i32> @ctpop_v2i32(<2 x i32> %a) nounwind {703; RV64I-LABEL: ctpop_v2i32:704; RV64I: # %bb.0:705; RV64I-NEXT: srli a2, a0, 1706; RV64I-NEXT: lui a3, 349525707; RV64I-NEXT: lui a4, 209715708; RV64I-NEXT: srli a5, a1, 1709; RV64I-NEXT: addi a3, a3, 1365710; RV64I-NEXT: and a2, a2, a3711; RV64I-NEXT: and a3, a5, a3712; RV64I-NEXT: lui a5, 61681713; RV64I-NEXT: addi a4, a4, 819714; RV64I-NEXT: addi a5, a5, -241715; RV64I-NEXT: sub a0, a0, a2716; RV64I-NEXT: sub a1, a1, a3717; RV64I-NEXT: and a2, a0, a4718; RV64I-NEXT: srli a0, a0, 2719; RV64I-NEXT: and a3, a1, a4720; RV64I-NEXT: srli a1, a1, 2721; RV64I-NEXT: and a0, a0, a4722; RV64I-NEXT: and a1, a1, a4723; RV64I-NEXT: add a0, a2, a0724; RV64I-NEXT: add a1, a3, a1725; RV64I-NEXT: srli a2, a0, 4726; RV64I-NEXT: srli a3, a1, 4727; RV64I-NEXT: add a0, a0, a2728; RV64I-NEXT: add a1, a1, a3729; RV64I-NEXT: and a0, a0, a5730; RV64I-NEXT: and a1, a1, a5731; RV64I-NEXT: slli a2, a0, 8732; RV64I-NEXT: slli a3, a1, 8733; RV64I-NEXT: add a0, a0, a2734; RV64I-NEXT: add a1, a1, a3735; RV64I-NEXT: slli a2, a0, 16736; RV64I-NEXT: slli a3, a1, 16737; RV64I-NEXT: add a0, a0, a2738; RV64I-NEXT: add a1, a1, a3739; RV64I-NEXT: srliw a0, a0, 24740; RV64I-NEXT: srliw a1, a1, 24741; RV64I-NEXT: ret742;743; RV64ZBB-LABEL: ctpop_v2i32:744; RV64ZBB: # %bb.0:745; RV64ZBB-NEXT: cpopw a0, a0746; RV64ZBB-NEXT: cpopw a1, a1747; RV64ZBB-NEXT: ret748 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)749 ret <2 x i32> %1750}751 752define <2 x i1> @ctpop_v2i32_ult_two(<2 x i32> %a) nounwind {753; CHECK-LABEL: ctpop_v2i32_ult_two:754; CHECK: # %bb.0:755; CHECK-NEXT: addi a2, a0, -1756; CHECK-NEXT: addi a3, a1, -1757; CHECK-NEXT: and a1, a1, a3758; CHECK-NEXT: and a0, a0, a2759; CHECK-NEXT: sext.w a1, a1760; CHECK-NEXT: sext.w a0, a0761; CHECK-NEXT: seqz a0, a0762; CHECK-NEXT: seqz a1, a1763; CHECK-NEXT: ret764 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)765 %2 = icmp ult <2 x i32> %1, <i32 2, i32 2>766 ret <2 x i1> %2767}768 769define <2 x i1> @ctpop_v2i32_ugt_one(<2 x i32> %a) nounwind {770; CHECK-LABEL: ctpop_v2i32_ugt_one:771; CHECK: # %bb.0:772; CHECK-NEXT: addi a2, a0, -1773; CHECK-NEXT: addi a3, a1, -1774; CHECK-NEXT: and a1, a1, a3775; CHECK-NEXT: and a0, a0, a2776; CHECK-NEXT: sext.w a1, a1777; CHECK-NEXT: sext.w a0, a0778; CHECK-NEXT: snez a0, a0779; CHECK-NEXT: snez a1, a1780; CHECK-NEXT: ret781 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)782 %2 = icmp ugt <2 x i32> %1, <i32 1, i32 1>783 ret <2 x i1> %2784}785 786define <2 x i1> @ctpop_v2i32_eq_one(<2 x i32> %a) nounwind {787; CHECK-LABEL: ctpop_v2i32_eq_one:788; CHECK: # %bb.0:789; CHECK-NEXT: addiw a2, a0, -1790; CHECK-NEXT: addiw a3, a1, -1791; CHECK-NEXT: xor a1, a1, a3792; CHECK-NEXT: xor a0, a0, a2793; CHECK-NEXT: sext.w a1, a1794; CHECK-NEXT: sext.w a0, a0795; CHECK-NEXT: sltu a0, a2, a0796; CHECK-NEXT: sltu a1, a3, a1797; CHECK-NEXT: ret798 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)799 %2 = icmp eq <2 x i32> %1, <i32 1, i32 1>800 ret <2 x i1> %2801}802 803define <2 x i1> @ctpop_v2i32_ne_one(<2 x i32> %a) nounwind {804; CHECK-LABEL: ctpop_v2i32_ne_one:805; CHECK: # %bb.0:806; CHECK-NEXT: addiw a2, a0, -1807; CHECK-NEXT: addiw a3, a1, -1808; CHECK-NEXT: xor a1, a1, a3809; CHECK-NEXT: xor a0, a0, a2810; CHECK-NEXT: sext.w a1, a1811; CHECK-NEXT: sext.w a0, a0812; CHECK-NEXT: sltu a0, a2, a0813; CHECK-NEXT: sltu a1, a3, a1814; CHECK-NEXT: xori a0, a0, 1815; CHECK-NEXT: xori a1, a1, 1816; CHECK-NEXT: ret817 %1 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)818 %2 = icmp ne <2 x i32> %1, <i32 1, i32 1>819 ret <2 x i1> %2820}821 822define i64 @ctpop_i64(i64 %a) nounwind {823; RV64I-LABEL: ctpop_i64:824; RV64I: # %bb.0:825; RV64I-NEXT: lui a1, 349525826; RV64I-NEXT: lui a2, 209715827; RV64I-NEXT: addi a1, a1, 1365828; RV64I-NEXT: addi a2, a2, 819829; RV64I-NEXT: slli a3, a1, 32830; RV64I-NEXT: add a1, a1, a3831; RV64I-NEXT: slli a3, a2, 32832; RV64I-NEXT: add a2, a2, a3833; RV64I-NEXT: srli a3, a0, 1834; RV64I-NEXT: and a1, a3, a1835; RV64I-NEXT: lui a3, 61681836; RV64I-NEXT: addi a3, a3, -241837; RV64I-NEXT: sub a0, a0, a1838; RV64I-NEXT: and a1, a0, a2839; RV64I-NEXT: srli a0, a0, 2840; RV64I-NEXT: and a0, a0, a2841; RV64I-NEXT: slli a2, a3, 32842; RV64I-NEXT: add a0, a1, a0843; RV64I-NEXT: srli a1, a0, 4844; RV64I-NEXT: add a0, a0, a1845; RV64I-NEXT: add a2, a3, a2846; RV64I-NEXT: and a0, a0, a2847; RV64I-NEXT: slli a1, a0, 8848; RV64I-NEXT: add a0, a0, a1849; RV64I-NEXT: slli a1, a0, 16850; RV64I-NEXT: add a0, a0, a1851; RV64I-NEXT: slli a1, a0, 32852; RV64I-NEXT: add a0, a0, a1853; RV64I-NEXT: srli a0, a0, 56854; RV64I-NEXT: ret855;856; RV64ZBB-LABEL: ctpop_i64:857; RV64ZBB: # %bb.0:858; RV64ZBB-NEXT: cpop a0, a0859; RV64ZBB-NEXT: ret860 %1 = call i64 @llvm.ctpop.i64(i64 %a)861 ret i64 %1862}863 864define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {865; RV64I-LABEL: ctpop_i64_ugt_two:866; RV64I: # %bb.0:867; RV64I-NEXT: addi a1, a0, -1868; RV64I-NEXT: and a0, a0, a1869; RV64I-NEXT: seqz a0, a0870; RV64I-NEXT: ret871;872; RV64ZBB-LABEL: ctpop_i64_ugt_two:873; RV64ZBB: # %bb.0:874; RV64ZBB-NEXT: cpop a0, a0875; RV64ZBB-NEXT: sltiu a0, a0, 2876; RV64ZBB-NEXT: ret877 %1 = call i64 @llvm.ctpop.i64(i64 %a)878 %2 = icmp ult i64 %1, 2879 ret i1 %2880}881 882define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {883; RV64I-LABEL: ctpop_i64_ugt_one:884; RV64I: # %bb.0:885; RV64I-NEXT: addi a1, a0, -1886; RV64I-NEXT: and a0, a0, a1887; RV64I-NEXT: snez a0, a0888; RV64I-NEXT: ret889;890; RV64ZBB-LABEL: ctpop_i64_ugt_one:891; RV64ZBB: # %bb.0:892; RV64ZBB-NEXT: cpop a0, a0893; RV64ZBB-NEXT: sltiu a0, a0, 2894; RV64ZBB-NEXT: xori a0, a0, 1895; RV64ZBB-NEXT: ret896 %1 = call i64 @llvm.ctpop.i64(i64 %a)897 %2 = icmp ugt i64 %1, 1898 ret i1 %2899}900 901define i1 @ctpop_i64_eq_one(i64 %a) nounwind {902; RV64I-LABEL: ctpop_i64_eq_one:903; RV64I: # %bb.0:904; RV64I-NEXT: addi a1, a0, -1905; RV64I-NEXT: xor a0, a0, a1906; RV64I-NEXT: sltu a0, a1, a0907; RV64I-NEXT: ret908;909; RV64ZBB-LABEL: ctpop_i64_eq_one:910; RV64ZBB: # %bb.0:911; RV64ZBB-NEXT: cpop a0, a0912; RV64ZBB-NEXT: addi a0, a0, -1913; RV64ZBB-NEXT: seqz a0, a0914; RV64ZBB-NEXT: ret915 %1 = call i64 @llvm.ctpop.i64(i64 %a)916 %2 = icmp eq i64 %1, 1917 ret i1 %2918}919 920define i1 @ctpop_i64_ne_one(i64 %a) nounwind {921; RV64I-LABEL: ctpop_i64_ne_one:922; RV64I: # %bb.0:923; RV64I-NEXT: addi a1, a0, -1924; RV64I-NEXT: xor a0, a0, a1925; RV64I-NEXT: sltu a0, a1, a0926; RV64I-NEXT: xori a0, a0, 1927; RV64I-NEXT: ret928;929; RV64ZBB-LABEL: ctpop_i64_ne_one:930; RV64ZBB: # %bb.0:931; RV64ZBB-NEXT: cpop a0, a0932; RV64ZBB-NEXT: addi a0, a0, -1933; RV64ZBB-NEXT: snez a0, a0934; RV64ZBB-NEXT: ret935 %1 = call i64 @llvm.ctpop.i64(i64 %a)936 %2 = icmp ne i64 %1, 1937 ret i1 %2938}939 940define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {941; RV64I-LABEL: ctpop_v2i64:942; RV64I: # %bb.0:943; RV64I-NEXT: srli a2, a0, 1944; RV64I-NEXT: lui a3, 349525945; RV64I-NEXT: lui a4, 209715946; RV64I-NEXT: lui a5, 61681947; RV64I-NEXT: addi a3, a3, 1365948; RV64I-NEXT: addi a4, a4, 819949; RV64I-NEXT: addi a5, a5, -241950; RV64I-NEXT: slli a6, a3, 32951; RV64I-NEXT: add a3, a3, a6952; RV64I-NEXT: slli a6, a4, 32953; RV64I-NEXT: add a4, a4, a6954; RV64I-NEXT: slli a6, a5, 32955; RV64I-NEXT: add a5, a5, a6956; RV64I-NEXT: srli a6, a1, 1957; RV64I-NEXT: and a2, a2, a3958; RV64I-NEXT: and a3, a6, a3959; RV64I-NEXT: sub a0, a0, a2960; RV64I-NEXT: sub a1, a1, a3961; RV64I-NEXT: and a2, a0, a4962; RV64I-NEXT: srli a0, a0, 2963; RV64I-NEXT: and a3, a1, a4964; RV64I-NEXT: srli a1, a1, 2965; RV64I-NEXT: and a0, a0, a4966; RV64I-NEXT: and a1, a1, a4967; RV64I-NEXT: add a0, a2, a0968; RV64I-NEXT: add a1, a3, a1969; RV64I-NEXT: srli a2, a0, 4970; RV64I-NEXT: srli a3, a1, 4971; RV64I-NEXT: add a0, a0, a2972; RV64I-NEXT: add a1, a1, a3973; RV64I-NEXT: and a0, a0, a5974; RV64I-NEXT: and a1, a1, a5975; RV64I-NEXT: slli a2, a0, 8976; RV64I-NEXT: slli a3, a1, 8977; RV64I-NEXT: add a0, a0, a2978; RV64I-NEXT: add a1, a1, a3979; RV64I-NEXT: slli a2, a0, 16980; RV64I-NEXT: slli a3, a1, 16981; RV64I-NEXT: add a0, a0, a2982; RV64I-NEXT: add a1, a1, a3983; RV64I-NEXT: slli a2, a0, 32984; RV64I-NEXT: slli a3, a1, 32985; RV64I-NEXT: add a0, a0, a2986; RV64I-NEXT: add a1, a1, a3987; RV64I-NEXT: srli a0, a0, 56988; RV64I-NEXT: srli a1, a1, 56989; RV64I-NEXT: ret990;991; RV64ZBB-LABEL: ctpop_v2i64:992; RV64ZBB: # %bb.0:993; RV64ZBB-NEXT: cpop a0, a0994; RV64ZBB-NEXT: cpop a1, a1995; RV64ZBB-NEXT: ret996 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)997 ret <2 x i64> %1998}999 1000define <2 x i1> @ctpop_v2i64_ult_two(<2 x i64> %a) nounwind {1001; CHECK-LABEL: ctpop_v2i64_ult_two:1002; CHECK: # %bb.0:1003; CHECK-NEXT: addi a2, a0, -11004; CHECK-NEXT: addi a3, a1, -11005; CHECK-NEXT: and a1, a1, a31006; CHECK-NEXT: and a0, a0, a21007; CHECK-NEXT: seqz a0, a01008; CHECK-NEXT: seqz a1, a11009; CHECK-NEXT: ret1010 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)1011 %2 = icmp ult <2 x i64> %1, <i64 2, i64 2>1012 ret <2 x i1> %21013}1014 1015define <2 x i1> @ctpop_v2i64_ugt_one(<2 x i64> %a) nounwind {1016; CHECK-LABEL: ctpop_v2i64_ugt_one:1017; CHECK: # %bb.0:1018; CHECK-NEXT: addi a2, a0, -11019; CHECK-NEXT: addi a3, a1, -11020; CHECK-NEXT: and a1, a1, a31021; CHECK-NEXT: and a0, a0, a21022; CHECK-NEXT: snez a0, a01023; CHECK-NEXT: snez a1, a11024; CHECK-NEXT: ret1025 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)1026 %2 = icmp ugt <2 x i64> %1, <i64 1, i64 1>1027 ret <2 x i1> %21028}1029 1030define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {1031; CHECK-LABEL: ctpop_v2i64_eq_one:1032; CHECK: # %bb.0:1033; CHECK-NEXT: addi a2, a0, -11034; CHECK-NEXT: addi a3, a1, -11035; CHECK-NEXT: xor a1, a1, a31036; CHECK-NEXT: xor a0, a0, a21037; CHECK-NEXT: sltu a0, a2, a01038; CHECK-NEXT: sltu a1, a3, a11039; CHECK-NEXT: ret1040 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)1041 %2 = icmp eq <2 x i64> %1, <i64 1, i64 1>1042 ret <2 x i1> %21043}1044 1045define <2 x i1> @ctpop_v2i64_ne_one(<2 x i64> %a) nounwind {1046; CHECK-LABEL: ctpop_v2i64_ne_one:1047; CHECK: # %bb.0:1048; CHECK-NEXT: addi a2, a0, -11049; CHECK-NEXT: addi a3, a1, -11050; CHECK-NEXT: xor a1, a1, a31051; CHECK-NEXT: xor a0, a0, a21052; CHECK-NEXT: sltu a0, a2, a01053; CHECK-NEXT: sltu a1, a3, a11054; CHECK-NEXT: xori a0, a0, 11055; CHECK-NEXT: xori a1, a1, 11056; CHECK-NEXT: ret1057 %1 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a)1058 %2 = icmp ne <2 x i64> %1, <i64 1, i64 1>1059 ret <2 x i1> %21060}1061 1062define signext i32 @sextb_i32(i32 signext %a) nounwind {1063; RV64I-LABEL: sextb_i32:1064; RV64I: # %bb.0:1065; RV64I-NEXT: slli a0, a0, 561066; RV64I-NEXT: srai a0, a0, 561067; RV64I-NEXT: ret1068;1069; RV64ZBB-LABEL: sextb_i32:1070; RV64ZBB: # %bb.0:1071; RV64ZBB-NEXT: sext.b a0, a01072; RV64ZBB-NEXT: ret1073 %shl = shl i32 %a, 241074 %shr = ashr exact i32 %shl, 241075 ret i32 %shr1076}1077 1078define i64 @sextb_i64(i64 %a) nounwind {1079; RV64I-LABEL: sextb_i64:1080; RV64I: # %bb.0:1081; RV64I-NEXT: slli a0, a0, 561082; RV64I-NEXT: srai a0, a0, 561083; RV64I-NEXT: ret1084;1085; RV64ZBB-LABEL: sextb_i64:1086; RV64ZBB: # %bb.0:1087; RV64ZBB-NEXT: sext.b a0, a01088; RV64ZBB-NEXT: ret1089 %shl = shl i64 %a, 561090 %shr = ashr exact i64 %shl, 561091 ret i64 %shr1092}1093 1094define signext i32 @sexth_i32(i32 signext %a) nounwind {1095; RV64I-LABEL: sexth_i32:1096; RV64I: # %bb.0:1097; RV64I-NEXT: slli a0, a0, 481098; RV64I-NEXT: srai a0, a0, 481099; RV64I-NEXT: ret1100;1101; RV64ZBB-LABEL: sexth_i32:1102; RV64ZBB: # %bb.0:1103; RV64ZBB-NEXT: sext.h a0, a01104; RV64ZBB-NEXT: ret1105 %shl = shl i32 %a, 161106 %shr = ashr exact i32 %shl, 161107 ret i32 %shr1108}1109 1110define i64 @sexth_i64(i64 %a) nounwind {1111; RV64I-LABEL: sexth_i64:1112; RV64I: # %bb.0:1113; RV64I-NEXT: slli a0, a0, 481114; RV64I-NEXT: srai a0, a0, 481115; RV64I-NEXT: ret1116;1117; RV64ZBB-LABEL: sexth_i64:1118; RV64ZBB: # %bb.0:1119; RV64ZBB-NEXT: sext.h a0, a01120; RV64ZBB-NEXT: ret1121 %shl = shl i64 %a, 481122 %shr = ashr exact i64 %shl, 481123 ret i64 %shr1124}1125 1126define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind {1127; RV64I-LABEL: min_i32:1128; RV64I: # %bb.0:1129; RV64I-NEXT: blt a0, a1, .LBB36_21130; RV64I-NEXT: # %bb.1:1131; RV64I-NEXT: mv a0, a11132; RV64I-NEXT: .LBB36_2:1133; RV64I-NEXT: ret1134;1135; RV64ZBB-LABEL: min_i32:1136; RV64ZBB: # %bb.0:1137; RV64ZBB-NEXT: min a0, a0, a11138; RV64ZBB-NEXT: ret1139 %cmp = icmp slt i32 %a, %b1140 %cond = select i1 %cmp, i32 %a, i32 %b1141 ret i32 %cond1142}1143 1144define i64 @min_i64(i64 %a, i64 %b) nounwind {1145; RV64I-LABEL: min_i64:1146; RV64I: # %bb.0:1147; RV64I-NEXT: blt a0, a1, .LBB37_21148; RV64I-NEXT: # %bb.1:1149; RV64I-NEXT: mv a0, a11150; RV64I-NEXT: .LBB37_2:1151; RV64I-NEXT: ret1152;1153; RV64ZBB-LABEL: min_i64:1154; RV64ZBB: # %bb.0:1155; RV64ZBB-NEXT: min a0, a0, a11156; RV64ZBB-NEXT: ret1157 %cmp = icmp slt i64 %a, %b1158 %cond = select i1 %cmp, i64 %a, i64 %b1159 ret i64 %cond1160}1161 1162define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind {1163; RV64I-LABEL: max_i32:1164; RV64I: # %bb.0:1165; RV64I-NEXT: blt a1, a0, .LBB38_21166; RV64I-NEXT: # %bb.1:1167; RV64I-NEXT: mv a0, a11168; RV64I-NEXT: .LBB38_2:1169; RV64I-NEXT: ret1170;1171; RV64ZBB-LABEL: max_i32:1172; RV64ZBB: # %bb.0:1173; RV64ZBB-NEXT: max a0, a0, a11174; RV64ZBB-NEXT: ret1175 %cmp = icmp sgt i32 %a, %b1176 %cond = select i1 %cmp, i32 %a, i32 %b1177 ret i32 %cond1178}1179 1180define i64 @max_i64(i64 %a, i64 %b) nounwind {1181; RV64I-LABEL: max_i64:1182; RV64I: # %bb.0:1183; RV64I-NEXT: blt a1, a0, .LBB39_21184; RV64I-NEXT: # %bb.1:1185; RV64I-NEXT: mv a0, a11186; RV64I-NEXT: .LBB39_2:1187; RV64I-NEXT: ret1188;1189; RV64ZBB-LABEL: max_i64:1190; RV64ZBB: # %bb.0:1191; RV64ZBB-NEXT: max a0, a0, a11192; RV64ZBB-NEXT: ret1193 %cmp = icmp sgt i64 %a, %b1194 %cond = select i1 %cmp, i64 %a, i64 %b1195 ret i64 %cond1196}1197 1198define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {1199; RV64I-LABEL: minu_i32:1200; RV64I: # %bb.0:1201; RV64I-NEXT: bltu a0, a1, .LBB40_21202; RV64I-NEXT: # %bb.1:1203; RV64I-NEXT: mv a0, a11204; RV64I-NEXT: .LBB40_2:1205; RV64I-NEXT: ret1206;1207; RV64ZBB-LABEL: minu_i32:1208; RV64ZBB: # %bb.0:1209; RV64ZBB-NEXT: minu a0, a0, a11210; RV64ZBB-NEXT: ret1211 %cmp = icmp ult i32 %a, %b1212 %cond = select i1 %cmp, i32 %a, i32 %b1213 ret i32 %cond1214}1215 1216define i64 @minu_i64(i64 %a, i64 %b) nounwind {1217; RV64I-LABEL: minu_i64:1218; RV64I: # %bb.0:1219; RV64I-NEXT: bltu a0, a1, .LBB41_21220; RV64I-NEXT: # %bb.1:1221; RV64I-NEXT: mv a0, a11222; RV64I-NEXT: .LBB41_2:1223; RV64I-NEXT: ret1224;1225; RV64ZBB-LABEL: minu_i64:1226; RV64ZBB: # %bb.0:1227; RV64ZBB-NEXT: minu a0, a0, a11228; RV64ZBB-NEXT: ret1229 %cmp = icmp ult i64 %a, %b1230 %cond = select i1 %cmp, i64 %a, i64 %b1231 ret i64 %cond1232}1233 1234define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {1235; RV64I-LABEL: maxu_i32:1236; RV64I: # %bb.0:1237; RV64I-NEXT: bltu a1, a0, .LBB42_21238; RV64I-NEXT: # %bb.1:1239; RV64I-NEXT: mv a0, a11240; RV64I-NEXT: .LBB42_2:1241; RV64I-NEXT: ret1242;1243; RV64ZBB-LABEL: maxu_i32:1244; RV64ZBB: # %bb.0:1245; RV64ZBB-NEXT: maxu a0, a0, a11246; RV64ZBB-NEXT: ret1247 %cmp = icmp ugt i32 %a, %b1248 %cond = select i1 %cmp, i32 %a, i32 %b1249 ret i32 %cond1250}1251 1252define i64 @maxu_i64(i64 %a, i64 %b) nounwind {1253; RV64I-LABEL: maxu_i64:1254; RV64I: # %bb.0:1255; RV64I-NEXT: bltu a1, a0, .LBB43_21256; RV64I-NEXT: # %bb.1:1257; RV64I-NEXT: mv a0, a11258; RV64I-NEXT: .LBB43_2:1259; RV64I-NEXT: ret1260;1261; RV64ZBB-LABEL: maxu_i64:1262; RV64ZBB: # %bb.0:1263; RV64ZBB-NEXT: maxu a0, a0, a11264; RV64ZBB-NEXT: ret1265 %cmp = icmp ugt i64 %a, %b1266 %cond = select i1 %cmp, i64 %a, i64 %b1267 ret i64 %cond1268}1269 1270define i32 @abs_i32(i32 %x) {1271; RV64I-LABEL: abs_i32:1272; RV64I: # %bb.0:1273; RV64I-NEXT: sraiw a1, a0, 311274; RV64I-NEXT: xor a0, a0, a11275; RV64I-NEXT: subw a0, a0, a11276; RV64I-NEXT: ret1277;1278; RV64ZBB-LABEL: abs_i32:1279; RV64ZBB: # %bb.0:1280; RV64ZBB-NEXT: sext.w a0, a01281; RV64ZBB-NEXT: negw a1, a01282; RV64ZBB-NEXT: max a0, a0, a11283; RV64ZBB-NEXT: ret1284 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)1285 ret i32 %abs1286}1287 1288define signext i32 @abs_i32_sext(i32 signext %x) {1289; RV64I-LABEL: abs_i32_sext:1290; RV64I: # %bb.0:1291; RV64I-NEXT: sraiw a1, a0, 311292; RV64I-NEXT: xor a0, a0, a11293; RV64I-NEXT: subw a0, a0, a11294; RV64I-NEXT: ret1295;1296; RV64ZBB-LABEL: abs_i32_sext:1297; RV64ZBB: # %bb.0:1298; RV64ZBB-NEXT: negw a1, a01299; RV64ZBB-NEXT: max a0, a0, a11300; RV64ZBB-NEXT: ret1301 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)1302 ret i32 %abs1303}1304 1305define i64 @abs_i64(i64 %x) {1306; RV64I-LABEL: abs_i64:1307; RV64I: # %bb.0:1308; RV64I-NEXT: srai a1, a0, 631309; RV64I-NEXT: xor a0, a0, a11310; RV64I-NEXT: sub a0, a0, a11311; RV64I-NEXT: ret1312;1313; RV64ZBB-LABEL: abs_i64:1314; RV64ZBB: # %bb.0:1315; RV64ZBB-NEXT: neg a1, a01316; RV64ZBB-NEXT: max a0, a0, a11317; RV64ZBB-NEXT: ret1318 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)1319 ret i64 %abs1320}1321 1322define i32 @zexth_i32(i32 %a) nounwind {1323; RV64I-LABEL: zexth_i32:1324; RV64I: # %bb.0:1325; RV64I-NEXT: slli a0, a0, 481326; RV64I-NEXT: srli a0, a0, 481327; RV64I-NEXT: ret1328;1329; RV64ZBB-LABEL: zexth_i32:1330; RV64ZBB: # %bb.0:1331; RV64ZBB-NEXT: zext.h a0, a01332; RV64ZBB-NEXT: ret1333 %and = and i32 %a, 655351334 ret i32 %and1335}1336 1337define i64 @zexth_i64(i64 %a) nounwind {1338; RV64I-LABEL: zexth_i64:1339; RV64I: # %bb.0:1340; RV64I-NEXT: slli a0, a0, 481341; RV64I-NEXT: srli a0, a0, 481342; RV64I-NEXT: ret1343;1344; RV64ZBB-LABEL: zexth_i64:1345; RV64ZBB: # %bb.0:1346; RV64ZBB-NEXT: zext.h a0, a01347; RV64ZBB-NEXT: ret1348 %and = and i64 %a, 655351349 ret i64 %and1350}1351 1352define signext i32 @bswap_i32(i32 signext %a) nounwind {1353; RV64I-LABEL: bswap_i32:1354; RV64I: # %bb.0:1355; RV64I-NEXT: srli a1, a0, 81356; RV64I-NEXT: lui a2, 161357; RV64I-NEXT: srliw a3, a0, 241358; RV64I-NEXT: addi a2, a2, -2561359; RV64I-NEXT: and a1, a1, a21360; RV64I-NEXT: and a2, a0, a21361; RV64I-NEXT: or a1, a1, a31362; RV64I-NEXT: slli a2, a2, 81363; RV64I-NEXT: slliw a0, a0, 241364; RV64I-NEXT: or a0, a0, a21365; RV64I-NEXT: or a0, a0, a11366; RV64I-NEXT: ret1367;1368; RV64ZBB-LABEL: bswap_i32:1369; RV64ZBB: # %bb.0:1370; RV64ZBB-NEXT: rev8 a0, a01371; RV64ZBB-NEXT: srai a0, a0, 321372; RV64ZBB-NEXT: ret1373 %1 = tail call i32 @llvm.bswap.i32(i32 %a)1374 ret i32 %11375}1376 1377; Similar to bswap_i32 but the result is not sign extended.1378define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind {1379; RV64I-LABEL: bswap_i32_nosext:1380; RV64I: # %bb.0:1381; RV64I-NEXT: srli a2, a0, 81382; RV64I-NEXT: lui a3, 161383; RV64I-NEXT: srliw a4, a0, 241384; RV64I-NEXT: addi a3, a3, -2561385; RV64I-NEXT: and a2, a2, a31386; RV64I-NEXT: and a3, a0, a31387; RV64I-NEXT: or a2, a2, a41388; RV64I-NEXT: slli a3, a3, 81389; RV64I-NEXT: slli a0, a0, 241390; RV64I-NEXT: or a0, a0, a31391; RV64I-NEXT: or a0, a0, a21392; RV64I-NEXT: sw a0, 0(a1)1393; RV64I-NEXT: ret1394;1395; RV64ZBB-LABEL: bswap_i32_nosext:1396; RV64ZBB: # %bb.0:1397; RV64ZBB-NEXT: rev8 a0, a01398; RV64ZBB-NEXT: srli a0, a0, 321399; RV64ZBB-NEXT: sw a0, 0(a1)1400; RV64ZBB-NEXT: ret1401 %1 = tail call i32 @llvm.bswap.i32(i32 %a)1402 store i32 %1, ptr %x1403 ret void1404}1405 1406define i64 @bswap_i64(i64 %a) {1407; RV64I-LABEL: bswap_i64:1408; RV64I: # %bb.0:1409; RV64I-NEXT: srli a1, a0, 401410; RV64I-NEXT: lui a2, 161411; RV64I-NEXT: srli a3, a0, 561412; RV64I-NEXT: srli a4, a0, 241413; RV64I-NEXT: lui a5, 40801414; RV64I-NEXT: addi a2, a2, -2561415; RV64I-NEXT: and a1, a1, a21416; RV64I-NEXT: or a1, a1, a31417; RV64I-NEXT: srli a3, a0, 81418; RV64I-NEXT: and a4, a4, a51419; RV64I-NEXT: srliw a3, a3, 241420; RV64I-NEXT: slli a3, a3, 241421; RV64I-NEXT: or a3, a3, a41422; RV64I-NEXT: srliw a4, a0, 241423; RV64I-NEXT: and a5, a0, a51424; RV64I-NEXT: and a2, a0, a21425; RV64I-NEXT: slli a0, a0, 561426; RV64I-NEXT: slli a4, a4, 321427; RV64I-NEXT: slli a5, a5, 241428; RV64I-NEXT: or a4, a5, a41429; RV64I-NEXT: slli a2, a2, 401430; RV64I-NEXT: or a1, a3, a11431; RV64I-NEXT: or a0, a0, a21432; RV64I-NEXT: or a0, a0, a41433; RV64I-NEXT: or a0, a0, a11434; RV64I-NEXT: ret1435;1436; RV64ZBB-LABEL: bswap_i64:1437; RV64ZBB: # %bb.0:1438; RV64ZBB-NEXT: rev8 a0, a01439; RV64ZBB-NEXT: ret1440 %1 = call i64 @llvm.bswap.i64(i64 %a)1441 ret i64 %11442}1443 1444define i16 @orc_b_i16(i16 %a) {1445; RV64I-LABEL: orc_b_i16:1446; RV64I: # %bb.0:1447; RV64I-NEXT: andi a0, a0, 2571448; RV64I-NEXT: slli a1, a0, 81449; RV64I-NEXT: sub a0, a1, a01450; RV64I-NEXT: ret1451;1452; RV64ZBB-LABEL: orc_b_i16:1453; RV64ZBB: # %bb.0:1454; RV64ZBB-NEXT: andi a0, a0, 2571455; RV64ZBB-NEXT: orc.b a0, a01456; RV64ZBB-NEXT: ret1457 %1 = and i16 %a, 2571458 %2 = mul nuw i16 %1, 2551459 ret i16 %21460}1461 1462define i32 @orc_b_i32(i32 %a) {1463; RV64I-LABEL: orc_b_i32:1464; RV64I: # %bb.0:1465; RV64I-NEXT: lui a1, 41121466; RV64I-NEXT: addi a1, a1, 2571467; RV64I-NEXT: and a0, a0, a11468; RV64I-NEXT: slli a1, a0, 81469; RV64I-NEXT: subw a0, a1, a01470; RV64I-NEXT: ret1471;1472; RV64ZBB-LABEL: orc_b_i32:1473; RV64ZBB: # %bb.0:1474; RV64ZBB-NEXT: lui a1, 41121475; RV64ZBB-NEXT: addi a1, a1, 2571476; RV64ZBB-NEXT: and a0, a0, a11477; RV64ZBB-NEXT: orc.b a0, a01478; RV64ZBB-NEXT: ret1479 %1 = and i32 %a, 168430091480 %2 = mul nuw i32 %1, 2551481 ret i32 %21482}1483 1484define i64 @orc_b_i64(i64 %a) {1485; RV64I-LABEL: orc_b_i64:1486; RV64I: # %bb.0:1487; RV64I-NEXT: lui a1, 41121488; RV64I-NEXT: addi a1, a1, 2571489; RV64I-NEXT: slli a2, a1, 321490; RV64I-NEXT: add a1, a1, a21491; RV64I-NEXT: and a0, a0, a11492; RV64I-NEXT: slli a1, a0, 81493; RV64I-NEXT: sub a0, a1, a01494; RV64I-NEXT: ret1495;1496; RV64ZBB-LABEL: orc_b_i64:1497; RV64ZBB: # %bb.0:1498; RV64ZBB-NEXT: lui a1, 41121499; RV64ZBB-NEXT: addi a1, a1, 2571500; RV64ZBB-NEXT: slli a2, a1, 321501; RV64ZBB-NEXT: add a1, a1, a21502; RV64ZBB-NEXT: and a0, a0, a11503; RV64ZBB-NEXT: orc.b a0, a01504; RV64ZBB-NEXT: ret1505 %1 = and i64 %a, 723401728380766731506 %2 = mul nuw i64 %1, 2551507 ret i64 %21508}1509 1510define i64 @srai_slli(i16 signext %0) {1511; CHECK-LABEL: srai_slli:1512; CHECK: # %bb.0:1513; CHECK-NEXT: slli a0, a0, 571514; CHECK-NEXT: srai a0, a0, 631515; CHECK-NEXT: ret1516 %2 = shl i16 %0, 91517 %sext = ashr i16 %2, 151518 %3 = sext i16 %sext to i641519 ret i64 %31520}1521 1522define i64 @srai_slli2(i16 signext %0) {1523; CHECK-LABEL: srai_slli2:1524; CHECK: # %bb.0:1525; CHECK-NEXT: slli a0, a0, 571526; CHECK-NEXT: srai a0, a0, 621527; CHECK-NEXT: ret1528 %2 = shl i16 %0, 91529 %sext = ashr i16 %2, 141530 %3 = sext i16 %sext to i641531 ret i64 %31532}1533 1534define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 {1535; CHECK-LABEL: func0000000000000001:1536; CHECK: # %bb.0: # %entry1537; CHECK-NEXT: slli a1, a1, 591538; CHECK-NEXT: srai a1, a1, 631539; CHECK-NEXT: addw a0, a1, a01540; CHECK-NEXT: ret1541entry:1542 %2 = shl i8 %1, 31543 %3 = ashr i8 %2, 71544 %4 = sext i8 %3 to i321545 %5 = add nsw i32 %4, %01546 ret i32 %51547}1548 1549define i1 @ctpop32_eq_one_nonzero(i32 %x) {1550; RV64I-LABEL: ctpop32_eq_one_nonzero:1551; RV64I: # %bb.0: # %entry1552; RV64I-NEXT: addi a1, a0, -11553; RV64I-NEXT: and a0, a0, a11554; RV64I-NEXT: sext.w a0, a01555; RV64I-NEXT: seqz a0, a01556; RV64I-NEXT: ret1557;1558; RV64ZBB-LABEL: ctpop32_eq_one_nonzero:1559; RV64ZBB: # %bb.0: # %entry1560; RV64ZBB-NEXT: cpopw a0, a01561; RV64ZBB-NEXT: sltiu a0, a0, 21562; RV64ZBB-NEXT: ret1563entry:1564 %popcnt = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)1565 %cmp = icmp eq i32 %popcnt, 11566 ret i1 %cmp1567}1568 1569define i1 @ctpop32_ne_one_nonzero(i32 %x) {1570; RV64I-LABEL: ctpop32_ne_one_nonzero:1571; RV64I: # %bb.0: # %entry1572; RV64I-NEXT: addi a1, a0, -11573; RV64I-NEXT: and a0, a0, a11574; RV64I-NEXT: sext.w a0, a01575; RV64I-NEXT: snez a0, a01576; RV64I-NEXT: ret1577;1578; RV64ZBB-LABEL: ctpop32_ne_one_nonzero:1579; RV64ZBB: # %bb.0: # %entry1580; RV64ZBB-NEXT: cpopw a0, a01581; RV64ZBB-NEXT: sltiu a0, a0, 21582; RV64ZBB-NEXT: xori a0, a0, 11583; RV64ZBB-NEXT: ret1584entry:1585 %popcnt = tail call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 %x)1586 %cmp = icmp ne i32 %popcnt, 11587 ret i1 %cmp1588}1589 1590define i1 @ctpop64_eq_one_nonzero(i64 %x) {1591; RV64I-LABEL: ctpop64_eq_one_nonzero:1592; RV64I: # %bb.0: # %entry1593; RV64I-NEXT: addi a1, a0, -11594; RV64I-NEXT: and a0, a0, a11595; RV64I-NEXT: seqz a0, a01596; RV64I-NEXT: ret1597;1598; RV64ZBB-LABEL: ctpop64_eq_one_nonzero:1599; RV64ZBB: # %bb.0: # %entry1600; RV64ZBB-NEXT: cpop a0, a01601; RV64ZBB-NEXT: sltiu a0, a0, 21602; RV64ZBB-NEXT: ret1603entry:1604 %popcnt = call range(i64 1, 65) i64 @llvm.ctpop.i64(i64 %x)1605 %cmp = icmp eq i64 %popcnt, 11606 ret i1 %cmp1607}1608 1609define i1 @ctpop32_eq_one_maybezero(i32 %x) {1610; RV64I-LABEL: ctpop32_eq_one_maybezero:1611; RV64I: # %bb.0: # %entry1612; RV64I-NEXT: addiw a1, a0, -11613; RV64I-NEXT: xor a0, a0, a11614; RV64I-NEXT: sext.w a0, a01615; RV64I-NEXT: sltu a0, a1, a01616; RV64I-NEXT: ret1617;1618; RV64ZBB-LABEL: ctpop32_eq_one_maybezero:1619; RV64ZBB: # %bb.0: # %entry1620; RV64ZBB-NEXT: cpopw a0, a01621; RV64ZBB-NEXT: addi a0, a0, -11622; RV64ZBB-NEXT: seqz a0, a01623; RV64ZBB-NEXT: ret1624entry:1625 %popcnt = call range(i32 0, 16) i32 @llvm.ctpop.i32(i32 %x)1626 %cmp = icmp eq i32 %popcnt, 11627 ret i1 %cmp1628}1629 1630define i8 @sub_if_uge_i8(i8 %x, i8 %y) {1631; RV64I-LABEL: sub_if_uge_i8:1632; RV64I: # %bb.0:1633; RV64I-NEXT: zext.b a2, a11634; RV64I-NEXT: zext.b a3, a01635; RV64I-NEXT: sltu a2, a3, a21636; RV64I-NEXT: addi a2, a2, -11637; RV64I-NEXT: and a1, a2, a11638; RV64I-NEXT: sub a0, a0, a11639; RV64I-NEXT: ret1640;1641; RV64ZBB-LABEL: sub_if_uge_i8:1642; RV64ZBB: # %bb.0:1643; RV64ZBB-NEXT: zext.b a2, a01644; RV64ZBB-NEXT: sub a0, a0, a11645; RV64ZBB-NEXT: zext.b a0, a01646; RV64ZBB-NEXT: minu a0, a2, a01647; RV64ZBB-NEXT: ret1648 %cmp = icmp ult i8 %x, %y1649 %select = select i1 %cmp, i8 0, i8 %y1650 %sub = sub nuw i8 %x, %select1651 ret i8 %sub1652}1653 1654define i16 @sub_if_uge_i16(i16 %x, i16 %y) {1655; RV64I-LABEL: sub_if_uge_i16:1656; RV64I: # %bb.0:1657; RV64I-NEXT: lui a2, 161658; RV64I-NEXT: addi a2, a2, -11659; RV64I-NEXT: and a3, a1, a21660; RV64I-NEXT: and a2, a0, a21661; RV64I-NEXT: sltu a2, a2, a31662; RV64I-NEXT: addi a2, a2, -11663; RV64I-NEXT: and a1, a2, a11664; RV64I-NEXT: sub a0, a0, a11665; RV64I-NEXT: ret1666;1667; RV64ZBB-LABEL: sub_if_uge_i16:1668; RV64ZBB: # %bb.0:1669; RV64ZBB-NEXT: zext.h a2, a01670; RV64ZBB-NEXT: sub a0, a0, a11671; RV64ZBB-NEXT: zext.h a0, a01672; RV64ZBB-NEXT: minu a0, a2, a01673; RV64ZBB-NEXT: ret1674 %cmp = icmp ult i16 %x, %y1675 %select = select i1 %cmp, i16 0, i16 %y1676 %sub = sub nuw i16 %x, %select1677 ret i16 %sub1678}1679 1680define i32 @sub_if_uge_i32(i32 %x, i32 %y) {1681; RV64I-LABEL: sub_if_uge_i32:1682; RV64I: # %bb.0:1683; RV64I-NEXT: sext.w a2, a11684; RV64I-NEXT: sext.w a3, a01685; RV64I-NEXT: sltu a2, a3, a21686; RV64I-NEXT: addi a2, a2, -11687; RV64I-NEXT: and a1, a2, a11688; RV64I-NEXT: subw a0, a0, a11689; RV64I-NEXT: ret1690;1691; RV64ZBB-LABEL: sub_if_uge_i32:1692; RV64ZBB: # %bb.0:1693; RV64ZBB-NEXT: sext.w a2, a01694; RV64ZBB-NEXT: subw a0, a0, a11695; RV64ZBB-NEXT: minu a0, a2, a01696; RV64ZBB-NEXT: ret1697 %cmp = icmp ult i32 %x, %y1698 %select = select i1 %cmp, i32 0, i32 %y1699 %sub = sub nuw i32 %x, %select1700 ret i32 %sub1701}1702 1703define i64 @sub_if_uge_i64(i64 %x, i64 %y) {1704; RV64I-LABEL: sub_if_uge_i64:1705; RV64I: # %bb.0:1706; RV64I-NEXT: sltu a2, a0, a11707; RV64I-NEXT: addi a2, a2, -11708; RV64I-NEXT: and a1, a2, a11709; RV64I-NEXT: sub a0, a0, a11710; RV64I-NEXT: ret1711;1712; RV64ZBB-LABEL: sub_if_uge_i64:1713; RV64ZBB: # %bb.0:1714; RV64ZBB-NEXT: sub a1, a0, a11715; RV64ZBB-NEXT: minu a0, a0, a11716; RV64ZBB-NEXT: ret1717 %cmp = icmp ult i64 %x, %y1718 %select = select i1 %cmp, i64 0, i64 %y1719 %sub = sub nuw i64 %x, %select1720 ret i64 %sub1721}1722 1723define i128 @sub_if_uge_i128(i128 %x, i128 %y) {1724; CHECK-LABEL: sub_if_uge_i128:1725; CHECK: # %bb.0:1726; CHECK-NEXT: beq a1, a3, .LBB66_21727; CHECK-NEXT: # %bb.1:1728; CHECK-NEXT: sltu a4, a1, a31729; CHECK-NEXT: j .LBB66_31730; CHECK-NEXT: .LBB66_2:1731; CHECK-NEXT: sltu a4, a0, a21732; CHECK-NEXT: .LBB66_3:1733; CHECK-NEXT: addi a4, a4, -11734; CHECK-NEXT: and a3, a4, a31735; CHECK-NEXT: and a2, a4, a21736; CHECK-NEXT: sltu a4, a0, a21737; CHECK-NEXT: sub a1, a1, a31738; CHECK-NEXT: sub a1, a1, a41739; CHECK-NEXT: sub a0, a0, a21740; CHECK-NEXT: ret1741 %cmp = icmp ult i128 %x, %y1742 %select = select i1 %cmp, i128 0, i128 %y1743 %sub = sub nuw i128 %x, %select1744 ret i128 %sub1745}1746 1747define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {1748; CHECK-LABEL: sub_if_uge_multiuse_select_i32:1749; CHECK: # %bb.0:1750; CHECK-NEXT: sext.w a2, a11751; CHECK-NEXT: sext.w a3, a01752; CHECK-NEXT: sltu a2, a3, a21753; CHECK-NEXT: addi a2, a2, -11754; CHECK-NEXT: and a1, a2, a11755; CHECK-NEXT: sub a0, a0, a11756; CHECK-NEXT: sllw a0, a0, a11757; CHECK-NEXT: ret1758 %cmp = icmp ult i32 %x, %y1759 %select = select i1 %cmp, i32 0, i32 %y1760 %sub = sub nuw i32 %x, %select1761 %shl = shl i32 %sub, %select1762 ret i32 %shl1763}1764 1765define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {1766; RV64I-LABEL: sub_if_uge_multiuse_cmp_i32:1767; RV64I: # %bb.0:1768; RV64I-NEXT: sext.w a2, a11769; RV64I-NEXT: sext.w a3, a01770; RV64I-NEXT: sltu a4, a3, a21771; RV64I-NEXT: addi a4, a4, -11772; RV64I-NEXT: and a1, a4, a11773; RV64I-NEXT: sub a0, a0, a11774; RV64I-NEXT: bltu a3, a2, .LBB68_21775; RV64I-NEXT: # %bb.1:1776; RV64I-NEXT: li a1, 41777; RV64I-NEXT: sllw a0, a0, a11778; RV64I-NEXT: ret1779; RV64I-NEXT: .LBB68_2:1780; RV64I-NEXT: li a1, 21781; RV64I-NEXT: sllw a0, a0, a11782; RV64I-NEXT: ret1783;1784; RV64ZBB-LABEL: sub_if_uge_multiuse_cmp_i32:1785; RV64ZBB: # %bb.0:1786; RV64ZBB-NEXT: sext.w a2, a11787; RV64ZBB-NEXT: sext.w a3, a01788; RV64ZBB-NEXT: subw a0, a0, a11789; RV64ZBB-NEXT: minu a0, a3, a01790; RV64ZBB-NEXT: bltu a3, a2, .LBB68_21791; RV64ZBB-NEXT: # %bb.1:1792; RV64ZBB-NEXT: li a1, 41793; RV64ZBB-NEXT: sllw a0, a0, a11794; RV64ZBB-NEXT: ret1795; RV64ZBB-NEXT: .LBB68_2:1796; RV64ZBB-NEXT: li a1, 21797; RV64ZBB-NEXT: sllw a0, a0, a11798; RV64ZBB-NEXT: ret1799 %cmp = icmp ult i32 %x, %y1800 %select = select i1 %cmp, i32 0, i32 %y1801 %sub = sub nuw i32 %x, %select1802 %select2 = select i1 %cmp, i32 2, i32 41803 %shl = shl i32 %sub, %select21804 ret i32 %shl1805}1806 1807define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) {1808; RV64I-LABEL: sub_if_uge_multiuse_cmp_store_i32:1809; RV64I: # %bb.0:1810; RV64I-NEXT: sltu a3, a0, a11811; RV64I-NEXT: xori a4, a3, 11812; RV64I-NEXT: addi a3, a3, -11813; RV64I-NEXT: and a1, a3, a11814; RV64I-NEXT: subw a0, a0, a11815; RV64I-NEXT: sw a4, 0(a2)1816; RV64I-NEXT: ret1817;1818; RV64ZBB-LABEL: sub_if_uge_multiuse_cmp_store_i32:1819; RV64ZBB: # %bb.0:1820; RV64ZBB-NEXT: sltu a3, a0, a11821; RV64ZBB-NEXT: subw a1, a0, a11822; RV64ZBB-NEXT: xori a3, a3, 11823; RV64ZBB-NEXT: minu a0, a0, a11824; RV64ZBB-NEXT: sw a3, 0(a2)1825; RV64ZBB-NEXT: ret1826 %cmp = icmp uge i32 %x, %y1827 %conv = zext i1 %cmp to i321828 store i32 %conv, ptr %z, align 41829 %select = select i1 %cmp, i32 %y, i32 01830 %sub = sub nuw i32 %x, %select1831 ret i32 %sub1832}1833 1834define i8 @sub_if_uge_C_i8(i8 zeroext %x) {1835; RV64I-LABEL: sub_if_uge_C_i8:1836; RV64I: # %bb.0:1837; RV64I-NEXT: sltiu a1, a0, 131838; RV64I-NEXT: addi a1, a1, -11839; RV64I-NEXT: andi a1, a1, -131840; RV64I-NEXT: add a0, a0, a11841; RV64I-NEXT: ret1842;1843; RV64ZBB-LABEL: sub_if_uge_C_i8:1844; RV64ZBB: # %bb.0:1845; RV64ZBB-NEXT: addi a1, a0, -131846; RV64ZBB-NEXT: zext.b a1, a11847; RV64ZBB-NEXT: minu a0, a1, a01848; RV64ZBB-NEXT: ret1849 %cmp = icmp ugt i8 %x, 121850 %sub = add i8 %x, -131851 %conv4 = select i1 %cmp, i8 %sub, i8 %x1852 ret i8 %conv41853}1854 1855define i16 @sub_if_uge_C_i16(i16 zeroext %x) {1856; RV64I-LABEL: sub_if_uge_C_i16:1857; RV64I: # %bb.0:1858; RV64I-NEXT: sltiu a1, a0, 2511859; RV64I-NEXT: addi a1, a1, -11860; RV64I-NEXT: andi a1, a1, -2511861; RV64I-NEXT: add a0, a0, a11862; RV64I-NEXT: ret1863;1864; RV64ZBB-LABEL: sub_if_uge_C_i16:1865; RV64ZBB: # %bb.0:1866; RV64ZBB-NEXT: addi a1, a0, -2511867; RV64ZBB-NEXT: zext.h a1, a11868; RV64ZBB-NEXT: minu a0, a1, a01869; RV64ZBB-NEXT: ret1870 %cmp = icmp ugt i16 %x, 2501871 %sub = add i16 %x, -2511872 %conv4 = select i1 %cmp, i16 %sub, i16 %x1873 ret i16 %conv41874}1875 1876define i32 @sub_if_uge_C_i32(i32 signext %x) {1877; RV64I-LABEL: sub_if_uge_C_i32:1878; RV64I: # %bb.0:1879; RV64I-NEXT: lui a1, 161880; RV64I-NEXT: lui a2, 10485601881; RV64I-NEXT: addi a1, a1, -161882; RV64I-NEXT: sltu a1, a1, a01883; RV64I-NEXT: neg a1, a11884; RV64I-NEXT: addi a2, a2, 151885; RV64I-NEXT: and a1, a1, a21886; RV64I-NEXT: addw a0, a0, a11887; RV64I-NEXT: ret1888;1889; RV64ZBB-LABEL: sub_if_uge_C_i32:1890; RV64ZBB: # %bb.0:1891; RV64ZBB-NEXT: lui a1, 10485601892; RV64ZBB-NEXT: addi a1, a1, 151893; RV64ZBB-NEXT: addw a1, a0, a11894; RV64ZBB-NEXT: minu a0, a1, a01895; RV64ZBB-NEXT: ret1896 %cmp = icmp ugt i32 %x, 655201897 %sub = add i32 %x, -655211898 %cond = select i1 %cmp, i32 %sub, i32 %x1899 ret i32 %cond1900}1901 1902define i64 @sub_if_uge_C_i64(i64 %x) {1903; RV64I-LABEL: sub_if_uge_C_i64:1904; RV64I: # %bb.0:1905; RV64I-NEXT: lui a1, 2981906; RV64I-NEXT: lui a2, 10461921907; RV64I-NEXT: addi a1, a1, 951908; RV64I-NEXT: addi a2, a2, -7611909; RV64I-NEXT: slli a1, a1, 121910; RV64I-NEXT: addi a1, a1, 5111911; RV64I-NEXT: sltu a1, a1, a01912; RV64I-NEXT: neg a1, a11913; RV64I-NEXT: slli a2, a2, 91914; RV64I-NEXT: and a1, a1, a21915; RV64I-NEXT: add a0, a0, a11916; RV64I-NEXT: ret1917;1918; RV64ZBB-LABEL: sub_if_uge_C_i64:1919; RV64ZBB: # %bb.0:1920; RV64ZBB-NEXT: lui a1, 10461921921; RV64ZBB-NEXT: addi a1, a1, -7611922; RV64ZBB-NEXT: slli a1, a1, 91923; RV64ZBB-NEXT: add a1, a0, a11924; RV64ZBB-NEXT: minu a0, a1, a01925; RV64ZBB-NEXT: ret1926 %cmp = icmp ugt i64 %x, 49999999991927 %sub = add i64 %x, -50000000001928 %cond = select i1 %cmp, i64 %sub, i64 %x1929 ret i64 %cond1930}1931 1932define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {1933; RV64I-LABEL: sub_if_uge_C_multiuse_cmp_i32:1934; RV64I: # %bb.0:1935; RV64I-NEXT: lui a2, 161936; RV64I-NEXT: lui a3, 10485601937; RV64I-NEXT: addi a2, a2, -161938; RV64I-NEXT: sltu a2, a2, a01939; RV64I-NEXT: neg a4, a21940; RV64I-NEXT: addi a3, a3, 151941; RV64I-NEXT: and a3, a4, a31942; RV64I-NEXT: addw a0, a0, a31943; RV64I-NEXT: sw a2, 0(a1)1944; RV64I-NEXT: ret1945;1946; RV64ZBB-LABEL: sub_if_uge_C_multiuse_cmp_i32:1947; RV64ZBB: # %bb.0:1948; RV64ZBB-NEXT: lui a2, 161949; RV64ZBB-NEXT: lui a3, 10485601950; RV64ZBB-NEXT: addi a2, a2, -161951; RV64ZBB-NEXT: addi a3, a3, 151952; RV64ZBB-NEXT: sltu a2, a2, a01953; RV64ZBB-NEXT: addw a3, a0, a31954; RV64ZBB-NEXT: minu a0, a3, a01955; RV64ZBB-NEXT: sw a2, 0(a1)1956; RV64ZBB-NEXT: ret1957 %cmp = icmp ugt i32 %x, 655201958 %conv = zext i1 %cmp to i321959 store i32 %conv, ptr %z, align 41960 %sub = add i32 %x, -655211961 %cond = select i1 %cmp, i32 %sub, i32 %x1962 ret i32 %cond1963}1964 1965define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {1966; RV64I-LABEL: sub_if_uge_C_multiuse_sub_i32:1967; RV64I: # %bb.0:1968; RV64I-NEXT: lui a2, 10485601969; RV64I-NEXT: lui a3, 161970; RV64I-NEXT: addi a2, a2, 151971; RV64I-NEXT: addw a2, a0, a21972; RV64I-NEXT: addi a3, a3, -161973; RV64I-NEXT: sw a2, 0(a1)1974; RV64I-NEXT: bltu a3, a0, .LBB75_21975; RV64I-NEXT: # %bb.1:1976; RV64I-NEXT: mv a2, a01977; RV64I-NEXT: .LBB75_2:1978; RV64I-NEXT: mv a0, a21979; RV64I-NEXT: ret1980;1981; RV64ZBB-LABEL: sub_if_uge_C_multiuse_sub_i32:1982; RV64ZBB: # %bb.0:1983; RV64ZBB-NEXT: lui a2, 10485601984; RV64ZBB-NEXT: addi a2, a2, 151985; RV64ZBB-NEXT: addw a2, a0, a21986; RV64ZBB-NEXT: minu a0, a2, a01987; RV64ZBB-NEXT: sw a2, 0(a1)1988; RV64ZBB-NEXT: ret1989 %sub = add i32 %x, -655211990 store i32 %sub, ptr %z, align 41991 %cmp = icmp ugt i32 %x, 655201992 %cond = select i1 %cmp, i32 %sub, i32 %x1993 ret i32 %cond1994}1995 1996define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {1997; RV64I-LABEL: sub_if_uge_C_swapped_i32:1998; RV64I: # %bb.0:1999; RV64I-NEXT: lui a1, 162000; RV64I-NEXT: lui a2, 10485602001; RV64I-NEXT: addi a1, a1, -152002; RV64I-NEXT: sltu a1, a0, a12003; RV64I-NEXT: addi a1, a1, -12004; RV64I-NEXT: addi a2, a2, 152005; RV64I-NEXT: and a1, a1, a22006; RV64I-NEXT: addw a0, a0, a12007; RV64I-NEXT: ret2008;2009; RV64ZBB-LABEL: sub_if_uge_C_swapped_i32:2010; RV64ZBB: # %bb.0:2011; RV64ZBB-NEXT: lui a1, 10485602012; RV64ZBB-NEXT: addi a1, a1, 152013; RV64ZBB-NEXT: addw a1, a0, a12014; RV64ZBB-NEXT: minu a0, a0, a12015; RV64ZBB-NEXT: ret2016 %cmp = icmp ult i32 %x, 655212017 %sub = add i32 %x, -655212018 %cond = select i1 %cmp, i32 %x, i32 %sub2019 ret i32 %cond2020}2021 2022define i7 @sub_if_uge_C_nsw_i7(i7 %a) {2023; RV64I-LABEL: sub_if_uge_C_nsw_i7:2024; RV64I: # %bb.0:2025; RV64I-NEXT: ori a0, a0, 512026; RV64I-NEXT: andi a1, a0, 1272027; RV64I-NEXT: sltiu a1, a1, 1112028; RV64I-NEXT: addi a1, a1, -12029; RV64I-NEXT: andi a1, a1, 172030; RV64I-NEXT: add a0, a0, a12031; RV64I-NEXT: ret2032;2033; RV64ZBB-LABEL: sub_if_uge_C_nsw_i7:2034; RV64ZBB: # %bb.0:2035; RV64ZBB-NEXT: ori a0, a0, 512036; RV64ZBB-NEXT: andi a1, a0, 1272037; RV64ZBB-NEXT: addi a0, a0, 172038; RV64ZBB-NEXT: andi a0, a0, 922039; RV64ZBB-NEXT: minu a0, a0, a12040; RV64ZBB-NEXT: ret2041 %x = or i7 %a, 512042 %c = icmp ugt i7 %x, -182043 %add = add nsw i7 %x, 172044 %s = select i1 %c, i7 %add, i7 %x2045 ret i7 %s2046}2047 2048define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {2049; RV64I-LABEL: sub_if_uge_C_swapped_nsw_i7:2050; RV64I: # %bb.0:2051; RV64I-NEXT: ori a0, a0, 512052; RV64I-NEXT: andi a1, a0, 1272053; RV64I-NEXT: sltiu a1, a1, 1112054; RV64I-NEXT: addi a1, a1, -12055; RV64I-NEXT: andi a1, a1, 172056; RV64I-NEXT: add a0, a0, a12057; RV64I-NEXT: ret2058;2059; RV64ZBB-LABEL: sub_if_uge_C_swapped_nsw_i7:2060; RV64ZBB: # %bb.0:2061; RV64ZBB-NEXT: ori a0, a0, 512062; RV64ZBB-NEXT: andi a1, a0, 1272063; RV64ZBB-NEXT: addi a0, a0, 172064; RV64ZBB-NEXT: andi a0, a0, 922065; RV64ZBB-NEXT: minu a0, a1, a02066; RV64ZBB-NEXT: ret2067 %x = or i7 %a, 512068 %c = icmp ult i7 %x, -172069 %add = add nsw i7 %x, 172070 %s = select i1 %c, i7 %x, i7 %add2071 ret i7 %s2072}2073