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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64ZBC4 5define i64 @clmul64r(i64 %a, i64 %b) nounwind {6; RV64ZBC-LABEL: clmul64r:7; RV64ZBC: # %bb.0:8; RV64ZBC-NEXT: clmulr a0, a0, a19; RV64ZBC-NEXT: ret10 %tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)11 ret i64 %tmp12}13 14define signext i32 @clmul32r(i32 signext %a, i32 signext %b) nounwind {15; RV64ZBC-LABEL: clmul32r:16; RV64ZBC: # %bb.0:17; RV64ZBC-NEXT: slli a1, a1, 3218; RV64ZBC-NEXT: slli a0, a0, 3219; RV64ZBC-NEXT: clmulr a0, a0, a120; RV64ZBC-NEXT: srai a0, a0, 3221; RV64ZBC-NEXT: ret22 %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)23 ret i32 %tmp24}25 26; FIXME: We could avoid the slli instructions by using clmul+srli+sext.w since27; the inputs are zero extended.28define signext i32 @clmul32r_zext(i32 zeroext %a, i32 zeroext %b) nounwind {29; RV64ZBC-LABEL: clmul32r_zext:30; RV64ZBC: # %bb.0:31; RV64ZBC-NEXT: slli a1, a1, 3232; RV64ZBC-NEXT: slli a0, a0, 3233; RV64ZBC-NEXT: clmulr a0, a0, a134; RV64ZBC-NEXT: srai a0, a0, 3235; RV64ZBC-NEXT: ret36 %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)37 ret i32 %tmp38}39