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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64ZBC-ZBKC4; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64ZBC-ZBKC6 7define i64 @clmul64(i64 %a, i64 %b) nounwind {8; RV64ZBC-ZBKC-LABEL: clmul64:9; RV64ZBC-ZBKC: # %bb.0:10; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a111; RV64ZBC-ZBKC-NEXT: ret12 %tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)13 ret i64 %tmp14}15 16define i64 @clmul64h(i64 %a, i64 %b) nounwind {17; RV64ZBC-ZBKC-LABEL: clmul64h:18; RV64ZBC-ZBKC: # %bb.0:19; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a120; RV64ZBC-ZBKC-NEXT: ret21 %tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)22 ret i64 %tmp23}24 25define signext i32 @clmul32(i32 signext %a, i32 signext %b) nounwind {26; RV64ZBC-ZBKC-LABEL: clmul32:27; RV64ZBC-ZBKC: # %bb.0:28; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a129; RV64ZBC-ZBKC-NEXT: sext.w a0, a030; RV64ZBC-ZBKC-NEXT: ret31 %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)32 ret i32 %tmp33}34 35define signext i32 @clmul32h(i32 signext %a, i32 signext %b) nounwind {36; RV64ZBC-ZBKC-LABEL: clmul32h:37; RV64ZBC-ZBKC: # %bb.0:38; RV64ZBC-ZBKC-NEXT: slli a1, a1, 3239; RV64ZBC-ZBKC-NEXT: slli a0, a0, 3240; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a141; RV64ZBC-ZBKC-NEXT: srai a0, a0, 3242; RV64ZBC-ZBKC-NEXT: ret43 %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)44 ret i32 %tmp45}46 47; FIXME: We could avoid the slli instructions by using clmul+srai since the48; inputs are zero extended.49define signext i32 @clmul32h_zext(i32 zeroext %a, i32 zeroext %b) nounwind {50; RV64ZBC-ZBKC-LABEL: clmul32h_zext:51; RV64ZBC-ZBKC: # %bb.0:52; RV64ZBC-ZBKC-NEXT: slli a1, a1, 3253; RV64ZBC-ZBKC-NEXT: slli a0, a0, 3254; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a155; RV64ZBC-ZBKC-NEXT: srai a0, a0, 3256; RV64ZBC-ZBKC-NEXT: ret57 %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)58 ret i32 %tmp59}60