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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64ZBKB4 5define i64 @brev8(i64 %a) nounwind {6; RV64ZBKB-LABEL: brev8:7; RV64ZBKB: # %bb.0:8; RV64ZBKB-NEXT: brev8 a0, a09; RV64ZBKB-NEXT: ret10 %val = call i64 @llvm.riscv.brev8.i64(i64 %a)11 ret i64 %val12}13 14; Test that rev8 is recognized as preserving zero extension.15define zeroext i16 @brev8_knownbits(i16 zeroext %a) nounwind {16; RV64ZBKB-LABEL: brev8_knownbits:17; RV64ZBKB: # %bb.0:18; RV64ZBKB-NEXT: brev8 a0, a019; RV64ZBKB-NEXT: ret20 %zext = zext i16 %a to i6421 %val = call i64 @llvm.riscv.brev8.i64(i64 %zext)22 %trunc = trunc i64 %val to i1623 ret i16 %trunc24}25 26define i64 @rev8_i64(i64 %a) {27; RV64ZBKB-LABEL: rev8_i64:28; RV64ZBKB: # %bb.0:29; RV64ZBKB-NEXT: rev8 a0, a030; RV64ZBKB-NEXT: ret31 %1 = call i64 @llvm.bswap.i64(i64 %a)32 ret i64 %133}34 35define signext i32 @brev8_i32(i32 signext %a) nounwind {36; RV64ZBKB-LABEL: brev8_i32:37; RV64ZBKB: # %bb.0:38; RV64ZBKB-NEXT: brev8 a0, a039; RV64ZBKB-NEXT: sext.w a0, a040; RV64ZBKB-NEXT: ret41 %val = call i32 @llvm.riscv.brev8.i32(i32 %a)42 ret i32 %val43}44 45; Test that rev8 is recognized as preserving zero extension.46define zeroext i16 @brev8_i32_knownbits(i16 zeroext %a) nounwind {47; RV64ZBKB-LABEL: brev8_i32_knownbits:48; RV64ZBKB: # %bb.0:49; RV64ZBKB-NEXT: brev8 a0, a050; RV64ZBKB-NEXT: ret51 %zext = zext i16 %a to i3252 %val = call i32 @llvm.riscv.brev8.i32(i32 %zext)53 %trunc = trunc i32 %val to i1654 ret i16 %trunc55}56 57define signext i32 @rev8_i32(i32 signext %a) {58; RV64ZBKB-LABEL: rev8_i32:59; RV64ZBKB: # %bb.0:60; RV64ZBKB-NEXT: rev8 a0, a061; RV64ZBKB-NEXT: srai a0, a0, 3262; RV64ZBKB-NEXT: ret63 %1 = call i32 @llvm.bswap.i32(i32 %a)64 ret i32 %165}66