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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64I4; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64ZBKB6 7define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {8; RV64I-LABEL: pack_i32:9; RV64I: # %bb.0:10; RV64I-NEXT: slli a0, a0, 4811; RV64I-NEXT: srli a0, a0, 4812; RV64I-NEXT: slliw a1, a1, 1613; RV64I-NEXT: or a0, a1, a014; RV64I-NEXT: ret15;16; RV64ZBKB-LABEL: pack_i32:17; RV64ZBKB: # %bb.0:18; RV64ZBKB-NEXT: packw a0, a0, a119; RV64ZBKB-NEXT: ret20 %shl = and i32 %a, 6553521 %shl1 = shl i32 %b, 1622 %or = or i32 %shl1, %shl23 ret i32 %or24}25 26define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {27; RV64I-LABEL: pack_i32_2:28; RV64I: # %bb.0:29; RV64I-NEXT: slliw a1, a1, 1630; RV64I-NEXT: or a0, a1, a031; RV64I-NEXT: ret32;33; RV64ZBKB-LABEL: pack_i32_2:34; RV64ZBKB: # %bb.0:35; RV64ZBKB-NEXT: packw a0, a0, a136; RV64ZBKB-NEXT: ret37 %zexta = zext i16 %a to i3238 %zextb = zext i16 %b to i3239 %shl1 = shl i32 %zextb, 1640 %or = or i32 %shl1, %zexta41 ret i32 %or42}43 44; Test case where we don't have a sign_extend_inreg after the or.45define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {46; RV64I-LABEL: pack_i32_3:47; RV64I: # %bb.0:48; RV64I-NEXT: slli a0, a0, 1649; RV64I-NEXT: or a0, a0, a150; RV64I-NEXT: addw a0, a0, a251; RV64I-NEXT: ret52;53; RV64ZBKB-LABEL: pack_i32_3:54; RV64ZBKB: # %bb.0:55; RV64ZBKB-NEXT: packw a0, a1, a056; RV64ZBKB-NEXT: addw a0, a0, a257; RV64ZBKB-NEXT: ret58 %4 = zext i16 %0 to i3259 %5 = shl nuw i32 %4, 1660 %6 = zext i16 %1 to i3261 %7 = or i32 %5, %662 %8 = add i32 %7, %263 ret i32 %864}65 66define i64 @pack_i64(i64 %a, i64 %b) nounwind {67; RV64I-LABEL: pack_i64:68; RV64I: # %bb.0:69; RV64I-NEXT: slli a0, a0, 3270; RV64I-NEXT: srli a0, a0, 3271; RV64I-NEXT: slli a1, a1, 3272; RV64I-NEXT: or a0, a1, a073; RV64I-NEXT: ret74;75; RV64ZBKB-LABEL: pack_i64:76; RV64ZBKB: # %bb.0:77; RV64ZBKB-NEXT: pack a0, a0, a178; RV64ZBKB-NEXT: ret79 %shl = and i64 %a, 429496729580 %shl1 = shl i64 %b, 3281 %or = or i64 %shl1, %shl82 ret i64 %or83}84 85define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {86; RV64I-LABEL: pack_i64_2:87; RV64I: # %bb.0:88; RV64I-NEXT: slli a0, a0, 3289; RV64I-NEXT: srli a0, a0, 3290; RV64I-NEXT: slli a1, a1, 3291; RV64I-NEXT: or a0, a1, a092; RV64I-NEXT: ret93;94; RV64ZBKB-LABEL: pack_i64_2:95; RV64ZBKB: # %bb.0:96; RV64ZBKB-NEXT: pack a0, a0, a197; RV64ZBKB-NEXT: ret98 %zexta = zext i32 %a to i6499 %zextb = zext i32 %b to i64100 %shl1 = shl i64 %zextb, 32101 %or = or i64 %shl1, %zexta102 ret i64 %or103}104 105define i64 @pack_i64_3(ptr %0, ptr %1) {106; RV64I-LABEL: pack_i64_3:107; RV64I: # %bb.0:108; RV64I-NEXT: lw a0, 0(a0)109; RV64I-NEXT: lwu a1, 0(a1)110; RV64I-NEXT: slli a0, a0, 32111; RV64I-NEXT: or a0, a0, a1112; RV64I-NEXT: ret113;114; RV64ZBKB-LABEL: pack_i64_3:115; RV64ZBKB: # %bb.0:116; RV64ZBKB-NEXT: lw a0, 0(a0)117; RV64ZBKB-NEXT: lw a1, 0(a1)118; RV64ZBKB-NEXT: pack a0, a1, a0119; RV64ZBKB-NEXT: ret120 %3 = load i32, ptr %0, align 4121 %4 = zext i32 %3 to i64122 %5 = shl i64 %4, 32123 %6 = load i32, ptr %1, align 4124 %7 = zext i32 %6 to i64125 %8 = or i64 %5, %7126 ret i64 %8127}128 129define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {130; RV64I-LABEL: packh_i32:131; RV64I: # %bb.0:132; RV64I-NEXT: zext.b a0, a0133; RV64I-NEXT: slli a1, a1, 56134; RV64I-NEXT: srli a1, a1, 48135; RV64I-NEXT: or a0, a1, a0136; RV64I-NEXT: ret137;138; RV64ZBKB-LABEL: packh_i32:139; RV64ZBKB: # %bb.0:140; RV64ZBKB-NEXT: packh a0, a0, a1141; RV64ZBKB-NEXT: ret142 %and = and i32 %a, 255143 %and1 = shl i32 %b, 8144 %shl = and i32 %and1, 65280145 %or = or i32 %shl, %and146 ret i32 %or147}148 149define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {150; RV64I-LABEL: packh_i32_2:151; RV64I: # %bb.0:152; RV64I-NEXT: zext.b a0, a0153; RV64I-NEXT: zext.b a1, a1154; RV64I-NEXT: slli a1, a1, 8155; RV64I-NEXT: or a0, a1, a0156; RV64I-NEXT: ret157;158; RV64ZBKB-LABEL: packh_i32_2:159; RV64ZBKB: # %bb.0:160; RV64ZBKB-NEXT: packh a0, a0, a1161; RV64ZBKB-NEXT: ret162 %and = and i32 %a, 255163 %and1 = and i32 %b, 255164 %shl = shl i32 %and1, 8165 %or = or i32 %shl, %and166 ret i32 %or167}168 169define i64 @packh_i64(i64 %a, i64 %b) nounwind {170; RV64I-LABEL: packh_i64:171; RV64I: # %bb.0:172; RV64I-NEXT: zext.b a0, a0173; RV64I-NEXT: slli a1, a1, 56174; RV64I-NEXT: srli a1, a1, 48175; RV64I-NEXT: or a0, a1, a0176; RV64I-NEXT: ret177;178; RV64ZBKB-LABEL: packh_i64:179; RV64ZBKB: # %bb.0:180; RV64ZBKB-NEXT: packh a0, a0, a1181; RV64ZBKB-NEXT: ret182 %and = and i64 %a, 255183 %and1 = shl i64 %b, 8184 %shl = and i64 %and1, 65280185 %or = or i64 %shl, %and186 ret i64 %or187}188 189define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {190; RV64I-LABEL: packh_i64_2:191; RV64I: # %bb.0:192; RV64I-NEXT: zext.b a0, a0193; RV64I-NEXT: zext.b a1, a1194; RV64I-NEXT: slli a1, a1, 8195; RV64I-NEXT: or a0, a1, a0196; RV64I-NEXT: ret197;198; RV64ZBKB-LABEL: packh_i64_2:199; RV64ZBKB: # %bb.0:200; RV64ZBKB-NEXT: packh a0, a0, a1201; RV64ZBKB-NEXT: ret202 %and = and i64 %a, 255203 %and1 = and i64 %b, 255204 %shl = shl i64 %and1, 8205 %or = or i64 %shl, %and206 ret i64 %or207}208 209define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {210; RV64I-LABEL: packh_i16:211; RV64I: # %bb.0:212; RV64I-NEXT: slli a1, a1, 8213; RV64I-NEXT: or a0, a1, a0214; RV64I-NEXT: ret215;216; RV64ZBKB-LABEL: packh_i16:217; RV64ZBKB: # %bb.0:218; RV64ZBKB-NEXT: packh a0, a0, a1219; RV64ZBKB-NEXT: ret220 %zext = zext i8 %a to i16221 %zext1 = zext i8 %b to i16222 %shl = shl i16 %zext1, 8223 %or = or i16 %shl, %zext224 ret i16 %or225}226 227define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {228; RV64I-LABEL: packh_i16_2:229; RV64I: # %bb.0:230; RV64I-NEXT: add a0, a1, a0231; RV64I-NEXT: slli a0, a0, 8232; RV64I-NEXT: or a0, a0, a2233; RV64I-NEXT: slli a0, a0, 48234; RV64I-NEXT: srli a0, a0, 48235; RV64I-NEXT: ret236;237; RV64ZBKB-LABEL: packh_i16_2:238; RV64ZBKB: # %bb.0:239; RV64ZBKB-NEXT: add a0, a1, a0240; RV64ZBKB-NEXT: packh a0, a2, a0241; RV64ZBKB-NEXT: ret242 %4 = add i8 %1, %0243 %5 = zext i8 %4 to i16244 %6 = shl i16 %5, 8245 %7 = zext i8 %2 to i16246 %8 = or i16 %6, %7247 ret i16 %8248}249 250define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {251; RV64I-LABEL: packh_i16_3:252; RV64I: # %bb.0:253; RV64I-NEXT: add a0, a1, a0254; RV64I-NEXT: slli a0, a0, 8255; RV64I-NEXT: or a0, a0, a2256; RV64I-NEXT: sh a0, 0(a3)257; RV64I-NEXT: ret258;259; RV64ZBKB-LABEL: packh_i16_3:260; RV64ZBKB: # %bb.0:261; RV64ZBKB-NEXT: add a0, a1, a0262; RV64ZBKB-NEXT: packh a0, a2, a0263; RV64ZBKB-NEXT: sh a0, 0(a3)264; RV64ZBKB-NEXT: ret265 %4 = add i8 %1, %0266 %5 = zext i8 %4 to i16267 %6 = shl i16 %5, 8268 %7 = zext i8 %2 to i16269 %8 = or i16 %6, %7270 store i16 %8, ptr %p271 ret void272}273 274define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {275; RV64I-LABEL: pack_i64_allWUsers:276; RV64I: # %bb.0:277; RV64I-NEXT: add a0, a1, a0278; RV64I-NEXT: slli a2, a2, 32279; RV64I-NEXT: slli a0, a0, 32280; RV64I-NEXT: srli a2, a2, 32281; RV64I-NEXT: or a0, a0, a2282; RV64I-NEXT: ret283;284; RV64ZBKB-LABEL: pack_i64_allWUsers:285; RV64ZBKB: # %bb.0:286; RV64ZBKB-NEXT: add a0, a1, a0287; RV64ZBKB-NEXT: pack a0, a2, a0288; RV64ZBKB-NEXT: ret289 %4 = add i32 %1, %0290 %5 = zext i32 %4 to i64291 %6 = shl i64 %5, 32292 %7 = zext i32 %2 to i64293 %8 = or i64 %6, %7294 ret i64 %8295}296 297define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2) {298; RV64I-LABEL: pack_i32_allWUsers:299; RV64I: # %bb.0:300; RV64I-NEXT: add a0, a1, a0301; RV64I-NEXT: slliw a0, a0, 16302; RV64I-NEXT: or a0, a0, a2303; RV64I-NEXT: ret304;305; RV64ZBKB-LABEL: pack_i32_allWUsers:306; RV64ZBKB: # %bb.0:307; RV64ZBKB-NEXT: add a0, a1, a0308; RV64ZBKB-NEXT: packw a0, a2, a0309; RV64ZBKB-NEXT: ret310 %4 = add i16 %1, %0311 %5 = zext i16 %4 to i32312 %6 = shl i32 %5, 16313 %7 = zext i16 %2 to i32314 %8 = or i32 %6, %7315 ret i32 %8316}317 318define i64 @pack_i64_imm() {319; RV64I-LABEL: pack_i64_imm:320; RV64I: # %bb.0:321; RV64I-NEXT: lui a0, 65793322; RV64I-NEXT: addi a0, a0, 16323; RV64I-NEXT: slli a1, a0, 32324; RV64I-NEXT: add a0, a0, a1325; RV64I-NEXT: ret326;327; RV64ZBKB-LABEL: pack_i64_imm:328; RV64ZBKB: # %bb.0:329; RV64ZBKB-NEXT: lui a0, 65793330; RV64ZBKB-NEXT: addi a0, a0, 16331; RV64ZBKB-NEXT: pack a0, a0, a0332; RV64ZBKB-NEXT: ret333 ret i64 1157442765409226768 ; 0x0101010101010101334}335 336define i32 @zexth_i32(i32 %a) nounwind {337; RV64I-LABEL: zexth_i32:338; RV64I: # %bb.0:339; RV64I-NEXT: slli a0, a0, 48340; RV64I-NEXT: srli a0, a0, 48341; RV64I-NEXT: ret342;343; RV64ZBKB-LABEL: zexth_i32:344; RV64ZBKB: # %bb.0:345; RV64ZBKB-NEXT: zext.h a0, a0346; RV64ZBKB-NEXT: ret347 %and = and i32 %a, 65535348 ret i32 %and349}350 351define i64 @zexth_i64(i64 %a) nounwind {352; RV64I-LABEL: zexth_i64:353; RV64I: # %bb.0:354; RV64I-NEXT: slli a0, a0, 48355; RV64I-NEXT: srli a0, a0, 48356; RV64I-NEXT: ret357;358; RV64ZBKB-LABEL: zexth_i64:359; RV64ZBKB: # %bb.0:360; RV64ZBKB-NEXT: zext.h a0, a0361; RV64ZBKB-NEXT: ret362 %and = and i64 %a, 65535363 ret i64 %and364}365 366define i32 @zext_i16_to_i32(i16 %a) nounwind {367; RV64I-LABEL: zext_i16_to_i32:368; RV64I: # %bb.0:369; RV64I-NEXT: slli a0, a0, 48370; RV64I-NEXT: srli a0, a0, 48371; RV64I-NEXT: ret372;373; RV64ZBKB-LABEL: zext_i16_to_i32:374; RV64ZBKB: # %bb.0:375; RV64ZBKB-NEXT: zext.h a0, a0376; RV64ZBKB-NEXT: ret377 %1 = zext i16 %a to i32378 ret i32 %1379}380 381define i64 @zext_i16_to_i64(i16 %a) nounwind {382; RV64I-LABEL: zext_i16_to_i64:383; RV64I: # %bb.0:384; RV64I-NEXT: slli a0, a0, 48385; RV64I-NEXT: srli a0, a0, 48386; RV64I-NEXT: ret387;388; RV64ZBKB-LABEL: zext_i16_to_i64:389; RV64ZBKB: # %bb.0:390; RV64ZBKB-NEXT: zext.h a0, a0391; RV64ZBKB-NEXT: ret392 %1 = zext i16 %a to i64393 ret i64 %1394}395 396define void @pack_lo_packh_hi_packh(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {397; RV64I-LABEL: pack_lo_packh_hi_packh:398; RV64I: # %bb.0:399; RV64I-NEXT: slli a1, a1, 8400; RV64I-NEXT: slli a2, a2, 16401; RV64I-NEXT: slli a3, a3, 24402; RV64I-NEXT: or a0, a0, a1403; RV64I-NEXT: or a2, a2, a3404; RV64I-NEXT: or a0, a0, a2405; RV64I-NEXT: sw a0, 0(a4)406; RV64I-NEXT: ret407;408; RV64ZBKB-LABEL: pack_lo_packh_hi_packh:409; RV64ZBKB: # %bb.0:410; RV64ZBKB-NEXT: packh a0, a0, a1411; RV64ZBKB-NEXT: packh a1, a2, a3412; RV64ZBKB-NEXT: packw a0, a0, a1413; RV64ZBKB-NEXT: sw a0, 0(a4)414; RV64ZBKB-NEXT: ret415 %a = zext i8 %0 to i32416 %b = zext i8 %1 to i32417 %c = zext i8 %2 to i32418 %d = zext i8 %3 to i32419 %e = shl i32 %b, 8420 %f = shl i32 %c, 16421 %g = shl i32 %d, 24422 %h = or i32 %a, %e423 %i = or i32 %h, %f424 %j = or i32 %i, %g425 store i32 %j, ptr %p426 ret void427}428 429define void @pack_lo_packh_hi_packh_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {430; RV64I-LABEL: pack_lo_packh_hi_packh_2:431; RV64I: # %bb.0:432; RV64I-NEXT: slli a1, a1, 8433; RV64I-NEXT: slli a2, a2, 16434; RV64I-NEXT: slli a3, a3, 24435; RV64I-NEXT: or a0, a0, a1436; RV64I-NEXT: or a2, a2, a3437; RV64I-NEXT: or a0, a2, a0438; RV64I-NEXT: sw a0, 0(a4)439; RV64I-NEXT: ret440;441; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_2:442; RV64ZBKB: # %bb.0:443; RV64ZBKB-NEXT: packh a0, a0, a1444; RV64ZBKB-NEXT: packh a1, a2, a3445; RV64ZBKB-NEXT: packw a0, a0, a1446; RV64ZBKB-NEXT: sw a0, 0(a4)447; RV64ZBKB-NEXT: ret448 %a = zext i8 %0 to i32449 %b = zext i8 %1 to i32450 %c = zext i8 %2 to i32451 %d = zext i8 %3 to i32452 %e = shl i32 %b, 8453 %f = shl i32 %c, 16454 %g = shl i32 %d, 24455 %h = or i32 %a, %e456 %i = or i32 %g, %h457 %j = or i32 %f, %i458 store i32 %j, ptr %p459 ret void460}461 462define void @pack_lo_packh_hi_packh_3(i8 %0, i8 %1, i8 %2, i8 %3, ptr %p) nounwind {463; RV64I-LABEL: pack_lo_packh_hi_packh_3:464; RV64I: # %bb.0:465; RV64I-NEXT: zext.b a0, a0466; RV64I-NEXT: zext.b a1, a1467; RV64I-NEXT: zext.b a2, a2468; RV64I-NEXT: slli a3, a3, 24469; RV64I-NEXT: slli a1, a1, 8470; RV64I-NEXT: slli a2, a2, 16471; RV64I-NEXT: or a0, a3, a0472; RV64I-NEXT: or a0, a0, a1473; RV64I-NEXT: or a0, a2, a0474; RV64I-NEXT: sw a0, 0(a4)475; RV64I-NEXT: ret476;477; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_3:478; RV64ZBKB: # %bb.0:479; RV64ZBKB-NEXT: packh a0, a0, a1480; RV64ZBKB-NEXT: packh a1, a2, a3481; RV64ZBKB-NEXT: packw a0, a0, a1482; RV64ZBKB-NEXT: sw a0, 0(a4)483; RV64ZBKB-NEXT: ret484 %a = zext i8 %0 to i32485 %b = zext i8 %1 to i32486 %c = zext i8 %2 to i32487 %d = zext i8 %3 to i32488 %e = shl i32 %b, 8489 %f = shl i32 %c, 16490 %g = shl i32 %d, 24491 %h = or i32 %a, %e492 %i = or i32 %g, %h493 %j = or i32 %f, %i494 store i32 %j, ptr %p495 ret void496}497 498define i32 @pack_lo_packh_hi_packh_4(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, ptr %p) nounwind {499; RV64I-LABEL: pack_lo_packh_hi_packh_4:500; RV64I: # %bb.0:501; RV64I-NEXT: slli a1, a1, 8502; RV64I-NEXT: slli a2, a2, 16503; RV64I-NEXT: slliw a3, a3, 24504; RV64I-NEXT: or a0, a0, a1505; RV64I-NEXT: or a2, a2, a3506; RV64I-NEXT: or a0, a0, a2507; RV64I-NEXT: ret508;509; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_4:510; RV64ZBKB: # %bb.0:511; RV64ZBKB-NEXT: packh a0, a0, a1512; RV64ZBKB-NEXT: packh a1, a2, a3513; RV64ZBKB-NEXT: packw a0, a0, a1514; RV64ZBKB-NEXT: ret515 %a = zext i8 %0 to i32516 %b = zext i8 %1 to i32517 %c = zext i8 %2 to i32518 %d = zext i8 %3 to i32519 %e = shl i32 %b, 8520 %f = shl i32 %c, 16521 %g = shl i32 %d, 24522 %h = or i32 %a, %e523 %i = or i32 %h, %f524 %j = or i32 %i, %g525 ret i32 %j526}527 528define void @pack_lo_zext_hi_packh(i16 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) nounwind {529; RV64I-LABEL: pack_lo_zext_hi_packh:530; RV64I: # %bb.0:531; RV64I-NEXT: slli a1, a1, 16532; RV64I-NEXT: slli a2, a2, 24533; RV64I-NEXT: or a1, a2, a1534; RV64I-NEXT: or a0, a1, a0535; RV64I-NEXT: sw a0, 0(a3)536; RV64I-NEXT: ret537;538; RV64ZBKB-LABEL: pack_lo_zext_hi_packh:539; RV64ZBKB: # %bb.0:540; RV64ZBKB-NEXT: packh a1, a1, a2541; RV64ZBKB-NEXT: packw a0, a0, a1542; RV64ZBKB-NEXT: sw a0, 0(a3)543; RV64ZBKB-NEXT: ret544 %a = zext i16 %0 to i32545 %b = zext i8 %1 to i32546 %c = zext i8 %2 to i32547 %d = shl i32 %c, 8548 %e = or i32 %b, %d549 %f = shl i32 %e, 16550 %g = or i32 %f, %a551 store i32 %g, ptr %p552 ret void553}554 555; Negative test, %a isn't extended so we can't use packw for the outer or, but556; we can use packh for the high half.557define void @pack_lo_noext_hi_packh(i32 %a, i8 zeroext %1, i8 zeroext %2, ptr %p) nounwind {558; RV64I-LABEL: pack_lo_noext_hi_packh:559; RV64I: # %bb.0:560; RV64I-NEXT: slli a1, a1, 16561; RV64I-NEXT: slli a2, a2, 24562; RV64I-NEXT: or a1, a2, a1563; RV64I-NEXT: or a0, a1, a0564; RV64I-NEXT: sw a0, 0(a3)565; RV64I-NEXT: ret566;567; RV64ZBKB-LABEL: pack_lo_noext_hi_packh:568; RV64ZBKB: # %bb.0:569; RV64ZBKB-NEXT: packh a1, a1, a2570; RV64ZBKB-NEXT: slli a1, a1, 16571; RV64ZBKB-NEXT: or a0, a1, a0572; RV64ZBKB-NEXT: sw a0, 0(a3)573; RV64ZBKB-NEXT: ret574 %b = zext i8 %1 to i32575 %c = zext i8 %2 to i32576 %d = shl i32 %c, 8577 %e = or i32 %b, %d578 %f = shl i32 %e, 16579 %g = or i32 %f, %a580 store i32 %g, ptr %p581 ret void582}583 584; Make sure we can match packh+slli without having the input bytes zero extended.585define void @pack_i32_lo_noext_hi_packh_nozeroext(i32 %a, i8 %1, i8 %2, ptr %p) nounwind {586; RV64I-LABEL: pack_i32_lo_noext_hi_packh_nozeroext:587; RV64I: # %bb.0:588; RV64I-NEXT: zext.b a1, a1589; RV64I-NEXT: slli a2, a2, 24590; RV64I-NEXT: slli a1, a1, 16591; RV64I-NEXT: or a0, a2, a0592; RV64I-NEXT: or a0, a0, a1593; RV64I-NEXT: sw a0, 0(a3)594; RV64I-NEXT: ret595;596; RV64ZBKB-LABEL: pack_i32_lo_noext_hi_packh_nozeroext:597; RV64ZBKB: # %bb.0:598; RV64ZBKB-NEXT: packh a1, a1, a2599; RV64ZBKB-NEXT: slli a1, a1, 16600; RV64ZBKB-NEXT: or a0, a1, a0601; RV64ZBKB-NEXT: sw a0, 0(a3)602; RV64ZBKB-NEXT: ret603 %b = zext i8 %1 to i32604 %c = zext i8 %2 to i32605 %d = shl i32 %c, 8606 %e = or i32 %b, %d607 %f = shl i32 %e, 16608 %g = or i32 %f, %a609 store i32 %g, ptr %p610 ret void611}612 613; Make sure we can match packh+slli without having the input bytes zero extended.614define i64 @pack_i64_lo_noext_hi_packh_nozeroext(i64 %a, i8 %1, i8 %2, ptr %p) nounwind {615; RV64I-LABEL: pack_i64_lo_noext_hi_packh_nozeroext:616; RV64I: # %bb.0:617; RV64I-NEXT: zext.b a1, a1618; RV64I-NEXT: zext.b a2, a2619; RV64I-NEXT: slli a1, a1, 16620; RV64I-NEXT: slli a2, a2, 24621; RV64I-NEXT: or a1, a2, a1622; RV64I-NEXT: or a0, a1, a0623; RV64I-NEXT: ret624;625; RV64ZBKB-LABEL: pack_i64_lo_noext_hi_packh_nozeroext:626; RV64ZBKB: # %bb.0:627; RV64ZBKB-NEXT: packh a1, a1, a2628; RV64ZBKB-NEXT: slli a1, a1, 16629; RV64ZBKB-NEXT: or a0, a1, a0630; RV64ZBKB-NEXT: ret631 %b = zext i8 %1 to i64632 %c = zext i8 %2 to i64633 %d = shl i64 %c, 8634 %e = or i64 %b, %d635 %f = shl i64 %e, 16636 %g = or i64 %f, %a637 ret i64 %g638}639