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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I4; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS6; RUN: llc -mtriple=riscv64 -mattr=+zbs,+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS8 9define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {10; RV64I-LABEL: bclr_i32:11; RV64I: # %bb.0:12; RV64I-NEXT: li a2, 113; RV64I-NEXT: sllw a1, a2, a114; RV64I-NEXT: not a1, a115; RV64I-NEXT: and a0, a1, a016; RV64I-NEXT: ret17;18; RV64ZBS-LABEL: bclr_i32:19; RV64ZBS: # %bb.0:20; RV64ZBS-NEXT: andi a1, a1, 3121; RV64ZBS-NEXT: bclr a0, a0, a122; RV64ZBS-NEXT: sext.w a0, a023; RV64ZBS-NEXT: ret24 %and = and i32 %b, 3125 %shl = shl nuw i32 1, %and26 %neg = xor i32 %shl, -127 %and1 = and i32 %neg, %a28 ret i32 %and129}30 31define signext i32 @bclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {32; RV64I-LABEL: bclr_i32_no_mask:33; RV64I: # %bb.0:34; RV64I-NEXT: li a2, 135; RV64I-NEXT: sllw a1, a2, a136; RV64I-NEXT: not a1, a137; RV64I-NEXT: and a0, a1, a038; RV64I-NEXT: ret39;40; RV64ZBS-LABEL: bclr_i32_no_mask:41; RV64ZBS: # %bb.0:42; RV64ZBS-NEXT: bclr a0, a0, a143; RV64ZBS-NEXT: sext.w a0, a044; RV64ZBS-NEXT: ret45 %shl = shl i32 1, %b46 %neg = xor i32 %shl, -147 %and1 = and i32 %neg, %a48 ret i32 %and149}50 51define signext i32 @bclr_i32_load(ptr %p, i32 signext %b) nounwind {52; RV64I-LABEL: bclr_i32_load:53; RV64I: # %bb.0:54; RV64I-NEXT: lw a0, 0(a0)55; RV64I-NEXT: li a2, 156; RV64I-NEXT: sllw a1, a2, a157; RV64I-NEXT: not a1, a158; RV64I-NEXT: and a0, a1, a059; RV64I-NEXT: ret60;61; RV64ZBS-LABEL: bclr_i32_load:62; RV64ZBS: # %bb.0:63; RV64ZBS-NEXT: lw a0, 0(a0)64; RV64ZBS-NEXT: bclr a0, a0, a165; RV64ZBS-NEXT: sext.w a0, a066; RV64ZBS-NEXT: ret67 %a = load i32, ptr %p68 %shl = shl i32 1, %b69 %neg = xor i32 %shl, -170 %and1 = and i32 %neg, %a71 ret i32 %and172}73 74define i64 @bclr_i64(i64 %a, i64 %b) nounwind {75; RV64I-LABEL: bclr_i64:76; RV64I: # %bb.0:77; RV64I-NEXT: li a2, 178; RV64I-NEXT: sll a1, a2, a179; RV64I-NEXT: not a1, a180; RV64I-NEXT: and a0, a1, a081; RV64I-NEXT: ret82;83; RV64ZBS-LABEL: bclr_i64:84; RV64ZBS: # %bb.0:85; RV64ZBS-NEXT: bclr a0, a0, a186; RV64ZBS-NEXT: ret87 %and = and i64 %b, 6388 %shl = shl nuw i64 1, %and89 %neg = xor i64 %shl, -190 %and1 = and i64 %neg, %a91 ret i64 %and192}93 94define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind {95; RV64I-LABEL: bclr_i64_no_mask:96; RV64I: # %bb.0:97; RV64I-NEXT: li a2, 198; RV64I-NEXT: sll a1, a2, a199; RV64I-NEXT: not a1, a1100; RV64I-NEXT: and a0, a1, a0101; RV64I-NEXT: ret102;103; RV64ZBS-LABEL: bclr_i64_no_mask:104; RV64ZBS: # %bb.0:105; RV64ZBS-NEXT: bclr a0, a0, a1106; RV64ZBS-NEXT: ret107 %shl = shl i64 1, %b108 %neg = xor i64 %shl, -1109 %and1 = and i64 %neg, %a110 ret i64 %and1111}112 113define i64 @bclr_i64_mask_multiple(i64 %a, i64 %b, i64 %shamt) nounwind {114; RV64I-LABEL: bclr_i64_mask_multiple:115; RV64I: # %bb.0:116; RV64I-NEXT: li a3, 1117; RV64I-NEXT: sll a2, a3, a2118; RV64I-NEXT: not a3, a2119; RV64I-NEXT: and a0, a3, a0120; RV64I-NEXT: or a1, a1, a2121; RV64I-NEXT: add a0, a0, a1122; RV64I-NEXT: ret123;124; RV64ZBS-LABEL: bclr_i64_mask_multiple:125; RV64ZBS: # %bb.0:126; RV64ZBS-NEXT: bclr a0, a0, a2127; RV64ZBS-NEXT: bset a1, a1, a2128; RV64ZBS-NEXT: add a0, a0, a1129; RV64ZBS-NEXT: ret130 %shamt_masked = and i64 %shamt, 63131 %shl = shl nuw i64 1, %shamt_masked132 %neg = xor i64 %shl, -1133 %and = and i64 %neg, %a134 %or = or i64 %b, %shl135 %c = add i64 %and, %or136 ret i64 %c137}138 139define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind {140; RV64I-LABEL: bset_i32:141; RV64I: # %bb.0:142; RV64I-NEXT: li a2, 1143; RV64I-NEXT: sllw a1, a2, a1144; RV64I-NEXT: or a0, a1, a0145; RV64I-NEXT: ret146;147; RV64ZBS-LABEL: bset_i32:148; RV64ZBS: # %bb.0:149; RV64ZBS-NEXT: andi a1, a1, 31150; RV64ZBS-NEXT: bset a0, a0, a1151; RV64ZBS-NEXT: sext.w a0, a0152; RV64ZBS-NEXT: ret153 %and = and i32 %b, 31154 %shl = shl nuw i32 1, %and155 %or = or i32 %shl, %a156 ret i32 %or157}158 159define signext i32 @bset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {160; RV64I-LABEL: bset_i32_no_mask:161; RV64I: # %bb.0:162; RV64I-NEXT: li a2, 1163; RV64I-NEXT: sllw a1, a2, a1164; RV64I-NEXT: or a0, a1, a0165; RV64I-NEXT: ret166;167; RV64ZBS-LABEL: bset_i32_no_mask:168; RV64ZBS: # %bb.0:169; RV64ZBS-NEXT: bset a0, a0, a1170; RV64ZBS-NEXT: sext.w a0, a0171; RV64ZBS-NEXT: ret172 %shl = shl i32 1, %b173 %or = or i32 %shl, %a174 ret i32 %or175}176 177define signext i32 @bset_i32_load(ptr %p, i32 signext %b) nounwind {178; RV64I-LABEL: bset_i32_load:179; RV64I: # %bb.0:180; RV64I-NEXT: lw a0, 0(a0)181; RV64I-NEXT: li a2, 1182; RV64I-NEXT: sllw a1, a2, a1183; RV64I-NEXT: or a0, a1, a0184; RV64I-NEXT: ret185;186; RV64ZBS-LABEL: bset_i32_load:187; RV64ZBS: # %bb.0:188; RV64ZBS-NEXT: lw a0, 0(a0)189; RV64ZBS-NEXT: bset a0, a0, a1190; RV64ZBS-NEXT: sext.w a0, a0191; RV64ZBS-NEXT: ret192 %a = load i32, ptr %p193 %shl = shl i32 1, %b194 %or = or i32 %shl, %a195 ret i32 %or196}197 198; We can use bsetw for 1 << x by setting the first source to zero.199define signext i32 @bset_i32_zero(i32 signext %a) nounwind {200; RV64I-LABEL: bset_i32_zero:201; RV64I: # %bb.0:202; RV64I-NEXT: li a1, 1203; RV64I-NEXT: sllw a0, a1, a0204; RV64I-NEXT: ret205;206; RV64ZBS-LABEL: bset_i32_zero:207; RV64ZBS: # %bb.0:208; RV64ZBS-NEXT: bset a0, zero, a0209; RV64ZBS-NEXT: sext.w a0, a0210; RV64ZBS-NEXT: ret211 %shl = shl i32 1, %a212 ret i32 %shl213}214 215define i64 @bset_i64(i64 %a, i64 %b) nounwind {216; RV64I-LABEL: bset_i64:217; RV64I: # %bb.0:218; RV64I-NEXT: li a2, 1219; RV64I-NEXT: sll a1, a2, a1220; RV64I-NEXT: or a0, a1, a0221; RV64I-NEXT: ret222;223; RV64ZBS-LABEL: bset_i64:224; RV64ZBS: # %bb.0:225; RV64ZBS-NEXT: bset a0, a0, a1226; RV64ZBS-NEXT: ret227 %conv = and i64 %b, 63228 %shl = shl nuw i64 1, %conv229 %or = or i64 %shl, %a230 ret i64 %or231}232 233define i64 @bset_i64_no_mask(i64 %a, i64 %b) nounwind {234; RV64I-LABEL: bset_i64_no_mask:235; RV64I: # %bb.0:236; RV64I-NEXT: li a2, 1237; RV64I-NEXT: sll a1, a2, a1238; RV64I-NEXT: or a0, a1, a0239; RV64I-NEXT: ret240;241; RV64ZBS-LABEL: bset_i64_no_mask:242; RV64ZBS: # %bb.0:243; RV64ZBS-NEXT: bset a0, a0, a1244; RV64ZBS-NEXT: ret245 %shl = shl i64 1, %b246 %or = or i64 %shl, %a247 ret i64 %or248}249 250; We can use bsetw for 1 << x by setting the first source to zero.251define signext i64 @bset_i64_zero(i64 signext %a) nounwind {252; RV64I-LABEL: bset_i64_zero:253; RV64I: # %bb.0:254; RV64I-NEXT: li a1, 1255; RV64I-NEXT: sll a0, a1, a0256; RV64I-NEXT: ret257;258; RV64ZBS-LABEL: bset_i64_zero:259; RV64ZBS: # %bb.0:260; RV64ZBS-NEXT: bset a0, zero, a0261; RV64ZBS-NEXT: ret262 %shl = shl i64 1, %a263 ret i64 %shl264}265 266define signext i32 @binv_i32(i32 signext %a, i32 signext %b) nounwind {267; RV64I-LABEL: binv_i32:268; RV64I: # %bb.0:269; RV64I-NEXT: li a2, 1270; RV64I-NEXT: sllw a1, a2, a1271; RV64I-NEXT: xor a0, a1, a0272; RV64I-NEXT: ret273;274; RV64ZBS-LABEL: binv_i32:275; RV64ZBS: # %bb.0:276; RV64ZBS-NEXT: andi a1, a1, 31277; RV64ZBS-NEXT: binv a0, a0, a1278; RV64ZBS-NEXT: sext.w a0, a0279; RV64ZBS-NEXT: ret280 %and = and i32 %b, 31281 %shl = shl nuw i32 1, %and282 %xor = xor i32 %shl, %a283 ret i32 %xor284}285 286define signext i32 @binv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {287; RV64I-LABEL: binv_i32_no_mask:288; RV64I: # %bb.0:289; RV64I-NEXT: li a2, 1290; RV64I-NEXT: sllw a1, a2, a1291; RV64I-NEXT: xor a0, a1, a0292; RV64I-NEXT: ret293;294; RV64ZBS-LABEL: binv_i32_no_mask:295; RV64ZBS: # %bb.0:296; RV64ZBS-NEXT: binv a0, a0, a1297; RV64ZBS-NEXT: sext.w a0, a0298; RV64ZBS-NEXT: ret299 %shl = shl i32 1, %b300 %xor = xor i32 %shl, %a301 ret i32 %xor302}303 304define signext i32 @binv_i32_load(ptr %p, i32 signext %b) nounwind {305; RV64I-LABEL: binv_i32_load:306; RV64I: # %bb.0:307; RV64I-NEXT: lw a0, 0(a0)308; RV64I-NEXT: li a2, 1309; RV64I-NEXT: sllw a1, a2, a1310; RV64I-NEXT: xor a0, a1, a0311; RV64I-NEXT: ret312;313; RV64ZBS-LABEL: binv_i32_load:314; RV64ZBS: # %bb.0:315; RV64ZBS-NEXT: lw a0, 0(a0)316; RV64ZBS-NEXT: binv a0, a0, a1317; RV64ZBS-NEXT: sext.w a0, a0318; RV64ZBS-NEXT: ret319 %a = load i32, ptr %p320 %shl = shl i32 1, %b321 %xor = xor i32 %shl, %a322 ret i32 %xor323}324 325define i64 @binv_i64(i64 %a, i64 %b) nounwind {326; RV64I-LABEL: binv_i64:327; RV64I: # %bb.0:328; RV64I-NEXT: li a2, 1329; RV64I-NEXT: sll a1, a2, a1330; RV64I-NEXT: xor a0, a1, a0331; RV64I-NEXT: ret332;333; RV64ZBS-LABEL: binv_i64:334; RV64ZBS: # %bb.0:335; RV64ZBS-NEXT: binv a0, a0, a1336; RV64ZBS-NEXT: ret337 %conv = and i64 %b, 63338 %shl = shl nuw i64 1, %conv339 %xor = xor i64 %shl, %a340 ret i64 %xor341}342 343define i64 @binv_i64_no_mask(i64 %a, i64 %b) nounwind {344; RV64I-LABEL: binv_i64_no_mask:345; RV64I: # %bb.0:346; RV64I-NEXT: li a2, 1347; RV64I-NEXT: sll a1, a2, a1348; RV64I-NEXT: xor a0, a1, a0349; RV64I-NEXT: ret350;351; RV64ZBS-LABEL: binv_i64_no_mask:352; RV64ZBS: # %bb.0:353; RV64ZBS-NEXT: binv a0, a0, a1354; RV64ZBS-NEXT: ret355 %shl = shl nuw i64 1, %b356 %xor = xor i64 %shl, %a357 ret i64 %xor358}359 360define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {361; RV64I-LABEL: bext_i32:362; RV64I: # %bb.0:363; RV64I-NEXT: srlw a0, a0, a1364; RV64I-NEXT: andi a0, a0, 1365; RV64I-NEXT: ret366;367; RV64ZBS-LABEL: bext_i32:368; RV64ZBS: # %bb.0:369; RV64ZBS-NEXT: andi a1, a1, 31370; RV64ZBS-NEXT: bext a0, a0, a1371; RV64ZBS-NEXT: ret372 %and = and i32 %b, 31373 %shr = lshr i32 %a, %and374 %and1 = and i32 %shr, 1375 ret i32 %and1376}377 378define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {379; RV64I-LABEL: bext_i32_no_mask:380; RV64I: # %bb.0:381; RV64I-NEXT: srlw a0, a0, a1382; RV64I-NEXT: andi a0, a0, 1383; RV64I-NEXT: ret384;385; RV64ZBS-LABEL: bext_i32_no_mask:386; RV64ZBS: # %bb.0:387; RV64ZBS-NEXT: bext a0, a0, a1388; RV64ZBS-NEXT: ret389 %shr = lshr i32 %a, %b390 %and1 = and i32 %shr, 1391 ret i32 %and1392}393 394; This gets previous converted to (i1 (truncate (srl X, Y)). Make sure we are395; able to use bext.396define void @bext_i32_trunc(i32 signext %0, i32 signext %1) {397; RV64I-LABEL: bext_i32_trunc:398; RV64I: # %bb.0:399; RV64I-NEXT: srlw a0, a0, a1400; RV64I-NEXT: andi a0, a0, 1401; RV64I-NEXT: beqz a0, .LBB20_2402; RV64I-NEXT: # %bb.1:403; RV64I-NEXT: ret404; RV64I-NEXT: .LBB20_2:405; RV64I-NEXT: tail bar406;407; RV64ZBS-LABEL: bext_i32_trunc:408; RV64ZBS: # %bb.0:409; RV64ZBS-NEXT: bext a0, a0, a1410; RV64ZBS-NEXT: beqz a0, .LBB20_2411; RV64ZBS-NEXT: # %bb.1:412; RV64ZBS-NEXT: ret413; RV64ZBS-NEXT: .LBB20_2:414; RV64ZBS-NEXT: tail bar415 %3 = shl i32 1, %1416 %4 = and i32 %3, %0417 %5 = icmp eq i32 %4, 0418 br i1 %5, label %6, label %7419 4206: ; preds = %2421 tail call void @bar()422 br label %7423 4247: ; preds = %6, %2425 ret void426}427 428declare void @bar()429 430define i64 @bext_i64(i64 %a, i64 %b) nounwind {431; RV64I-LABEL: bext_i64:432; RV64I: # %bb.0:433; RV64I-NEXT: srl a0, a0, a1434; RV64I-NEXT: andi a0, a0, 1435; RV64I-NEXT: ret436;437; RV64ZBS-LABEL: bext_i64:438; RV64ZBS: # %bb.0:439; RV64ZBS-NEXT: bext a0, a0, a1440; RV64ZBS-NEXT: ret441 %conv = and i64 %b, 63442 %shr = lshr i64 %a, %conv443 %and1 = and i64 %shr, 1444 ret i64 %and1445}446 447define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {448; RV64I-LABEL: bext_i64_no_mask:449; RV64I: # %bb.0:450; RV64I-NEXT: srl a0, a0, a1451; RV64I-NEXT: andi a0, a0, 1452; RV64I-NEXT: ret453;454; RV64ZBS-LABEL: bext_i64_no_mask:455; RV64ZBS: # %bb.0:456; RV64ZBS-NEXT: bext a0, a0, a1457; RV64ZBS-NEXT: ret458 %shr = lshr i64 %a, %b459 %and1 = and i64 %shr, 1460 ret i64 %and1461}462 463define signext i32 @bexti_i32(i32 signext %a) nounwind {464; RV64I-LABEL: bexti_i32:465; RV64I: # %bb.0:466; RV64I-NEXT: slli a0, a0, 58467; RV64I-NEXT: srli a0, a0, 63468; RV64I-NEXT: ret469;470; RV64ZBS-LABEL: bexti_i32:471; RV64ZBS: # %bb.0:472; RV64ZBS-NEXT: bexti a0, a0, 5473; RV64ZBS-NEXT: ret474 %shr = lshr i32 %a, 5475 %and = and i32 %shr, 1476 ret i32 %and477}478 479define i64 @bexti_i64(i64 %a) nounwind {480; RV64I-LABEL: bexti_i64:481; RV64I: # %bb.0:482; RV64I-NEXT: slli a0, a0, 58483; RV64I-NEXT: srli a0, a0, 63484; RV64I-NEXT: ret485;486; RV64ZBS-LABEL: bexti_i64:487; RV64ZBS: # %bb.0:488; RV64ZBS-NEXT: bexti a0, a0, 5489; RV64ZBS-NEXT: ret490 %shr = lshr i64 %a, 5491 %and = and i64 %shr, 1492 ret i64 %and493}494 495define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {496; RV64I-LABEL: bexti_i32_cmp:497; RV64I: # %bb.0:498; RV64I-NEXT: slli a0, a0, 58499; RV64I-NEXT: srli a0, a0, 63500; RV64I-NEXT: ret501;502; RV64ZBS-LABEL: bexti_i32_cmp:503; RV64ZBS: # %bb.0:504; RV64ZBS-NEXT: bexti a0, a0, 5505; RV64ZBS-NEXT: ret506 %and = and i32 %a, 32507 %cmp = icmp ne i32 %and, 0508 %zext = zext i1 %cmp to i32509 ret i32 %zext510}511 512define i64 @bexti_i64_cmp(i64 %a) nounwind {513; RV64I-LABEL: bexti_i64_cmp:514; RV64I: # %bb.0:515; RV64I-NEXT: slli a0, a0, 58516; RV64I-NEXT: srli a0, a0, 63517; RV64I-NEXT: ret518;519; RV64ZBS-LABEL: bexti_i64_cmp:520; RV64ZBS: # %bb.0:521; RV64ZBS-NEXT: bexti a0, a0, 5522; RV64ZBS-NEXT: ret523 %and = and i64 %a, 32524 %cmp = icmp ne i64 %and, 0525 %zext = zext i1 %cmp to i64526 ret i64 %zext527}528 529define signext i32 @bclri_i32_10(i32 signext %a) nounwind {530; CHECK-LABEL: bclri_i32_10:531; CHECK: # %bb.0:532; CHECK-NEXT: andi a0, a0, -1025533; CHECK-NEXT: ret534 %and = and i32 %a, -1025535 ret i32 %and536}537 538define signext i32 @bclri_i32_11(i32 signext %a) nounwind {539; RV64I-LABEL: bclri_i32_11:540; RV64I: # %bb.0:541; RV64I-NEXT: lui a1, 1048575542; RV64I-NEXT: addi a1, a1, 2047543; RV64I-NEXT: and a0, a0, a1544; RV64I-NEXT: ret545;546; RV64ZBS-LABEL: bclri_i32_11:547; RV64ZBS: # %bb.0:548; RV64ZBS-NEXT: bclri a0, a0, 11549; RV64ZBS-NEXT: ret550 %and = and i32 %a, -2049551 ret i32 %and552}553 554define signext i32 @bclri_i32_30(i32 signext %a) nounwind {555; RV64I-LABEL: bclri_i32_30:556; RV64I: # %bb.0:557; RV64I-NEXT: lui a1, 786432558; RV64I-NEXT: addi a1, a1, -1559; RV64I-NEXT: and a0, a0, a1560; RV64I-NEXT: ret561;562; RV64ZBS-LABEL: bclri_i32_30:563; RV64ZBS: # %bb.0:564; RV64ZBS-NEXT: bclri a0, a0, 30565; RV64ZBS-NEXT: ret566 %and = and i32 %a, -1073741825567 ret i32 %and568}569 570define signext i32 @bclri_i32_31(i32 signext %a) nounwind {571; CHECK-LABEL: bclri_i32_31:572; CHECK: # %bb.0:573; CHECK-NEXT: slli a0, a0, 33574; CHECK-NEXT: srli a0, a0, 33575; CHECK-NEXT: ret576 %and = and i32 %a, 2147483647577 ret i32 %and578}579 580define signext i32 @bclri_i32_31_allWUsers(i32 signext %a) nounwind {581; RV64I-LABEL: bclri_i32_31_allWUsers:582; RV64I: # %bb.0:583; RV64I-NEXT: slli a0, a0, 33584; RV64I-NEXT: srli a0, a0, 33585; RV64I-NEXT: addiw a0, a0, 1586; RV64I-NEXT: ret587;588; RV64ZBS-LABEL: bclri_i32_31_allWUsers:589; RV64ZBS: # %bb.0:590; RV64ZBS-NEXT: bclri a0, a0, 31591; RV64ZBS-NEXT: addiw a0, a0, 1592; RV64ZBS-NEXT: ret593 %and = and i32 %a, 2147483647594 %add = add i32 %and, 1595 ret i32 %add596}597 598define i64 @bclri_i64_10(i64 %a) nounwind {599; CHECK-LABEL: bclri_i64_10:600; CHECK: # %bb.0:601; CHECK-NEXT: andi a0, a0, -1025602; CHECK-NEXT: ret603 %and = and i64 %a, -1025604 ret i64 %and605}606 607define i64 @bclri_i64_11(i64 %a) nounwind {608; RV64I-LABEL: bclri_i64_11:609; RV64I: # %bb.0:610; RV64I-NEXT: lui a1, 1048575611; RV64I-NEXT: addi a1, a1, 2047612; RV64I-NEXT: and a0, a0, a1613; RV64I-NEXT: ret614;615; RV64ZBS-LABEL: bclri_i64_11:616; RV64ZBS: # %bb.0:617; RV64ZBS-NEXT: bclri a0, a0, 11618; RV64ZBS-NEXT: ret619 %and = and i64 %a, -2049620 ret i64 %and621}622 623define i64 @bclri_i64_30(i64 %a) nounwind {624; RV64I-LABEL: bclri_i64_30:625; RV64I: # %bb.0:626; RV64I-NEXT: lui a1, 786432627; RV64I-NEXT: addi a1, a1, -1628; RV64I-NEXT: and a0, a0, a1629; RV64I-NEXT: ret630;631; RV64ZBS-LABEL: bclri_i64_30:632; RV64ZBS: # %bb.0:633; RV64ZBS-NEXT: bclri a0, a0, 30634; RV64ZBS-NEXT: ret635 %and = and i64 %a, -1073741825636 ret i64 %and637}638 639define i64 @bclri_i64_31(i64 %a) nounwind {640; RV64I-LABEL: bclri_i64_31:641; RV64I: # %bb.0:642; RV64I-NEXT: lui a1, 524288643; RV64I-NEXT: addi a1, a1, -1644; RV64I-NEXT: and a0, a0, a1645; RV64I-NEXT: ret646;647; RV64ZBS-LABEL: bclri_i64_31:648; RV64ZBS: # %bb.0:649; RV64ZBS-NEXT: bclri a0, a0, 31650; RV64ZBS-NEXT: ret651 %and = and i64 %a, -2147483649652 ret i64 %and653}654 655define i64 @bclri_i64_62(i64 %a) nounwind {656; RV64I-LABEL: bclri_i64_62:657; RV64I: # %bb.0:658; RV64I-NEXT: li a1, -1659; RV64I-NEXT: slli a1, a1, 62660; RV64I-NEXT: addi a1, a1, -1661; RV64I-NEXT: and a0, a0, a1662; RV64I-NEXT: ret663;664; RV64ZBS-LABEL: bclri_i64_62:665; RV64ZBS: # %bb.0:666; RV64ZBS-NEXT: bclri a0, a0, 62667; RV64ZBS-NEXT: ret668 %and = and i64 %a, -4611686018427387905669 ret i64 %and670}671 672define i64 @bclri_i64_63(i64 %a) nounwind {673; RV64I-LABEL: bclri_i64_63:674; RV64I: # %bb.0:675; RV64I-NEXT: slli a0, a0, 1676; RV64I-NEXT: srli a0, a0, 1677; RV64I-NEXT: ret678;679; RV64ZBS-LABEL: bclri_i64_63:680; RV64ZBS: # %bb.0:681; RV64ZBS-NEXT: bclri a0, a0, 63682; RV64ZBS-NEXT: ret683 %and = and i64 %a, -9223372036854775809684 ret i64 %and685}686 687define i64 @bclri_i64_large0(i64 %a) nounwind {688; RV64I-LABEL: bclri_i64_large0:689; RV64I: # %bb.0:690; RV64I-NEXT: lui a1, 1044480691; RV64I-NEXT: addi a1, a1, -256692; RV64I-NEXT: and a0, a0, a1693; RV64I-NEXT: ret694;695; RV64ZBS-LABEL: bclri_i64_large0:696; RV64ZBS: # %bb.0:697; RV64ZBS-NEXT: andi a0, a0, -256698; RV64ZBS-NEXT: bclri a0, a0, 24699; RV64ZBS-NEXT: ret700 %and = and i64 %a, -16777472701 ret i64 %and702}703 704define i64 @bclri_i64_large1(i64 %a) nounwind {705; RV64I-LABEL: bclri_i64_large1:706; RV64I: # %bb.0:707; RV64I-NEXT: lui a1, 1044464708; RV64I-NEXT: addi a1, a1, -1709; RV64I-NEXT: and a0, a0, a1710; RV64I-NEXT: ret711;712; RV64ZBS-LABEL: bclri_i64_large1:713; RV64ZBS: # %bb.0:714; RV64ZBS-NEXT: bclri a0, a0, 16715; RV64ZBS-NEXT: bclri a0, a0, 24716; RV64ZBS-NEXT: ret717 %and = and i64 %a, -16842753718 ret i64 %and719}720 721define signext i32 @bseti_i32_10(i32 signext %a) nounwind {722; CHECK-LABEL: bseti_i32_10:723; CHECK: # %bb.0:724; CHECK-NEXT: ori a0, a0, 1024725; CHECK-NEXT: ret726 %or = or i32 %a, 1024727 ret i32 %or728}729 730define signext i32 @bseti_i32_11(i32 signext %a) nounwind {731; RV64I-LABEL: bseti_i32_11:732; RV64I: # %bb.0:733; RV64I-NEXT: li a1, 1734; RV64I-NEXT: slli a1, a1, 11735; RV64I-NEXT: or a0, a0, a1736; RV64I-NEXT: ret737;738; RV64ZBS-LABEL: bseti_i32_11:739; RV64ZBS: # %bb.0:740; RV64ZBS-NEXT: bseti a0, a0, 11741; RV64ZBS-NEXT: ret742 %or = or i32 %a, 2048743 ret i32 %or744}745 746define signext i32 @bseti_i32_30(i32 signext %a) nounwind {747; RV64I-LABEL: bseti_i32_30:748; RV64I: # %bb.0:749; RV64I-NEXT: lui a1, 262144750; RV64I-NEXT: or a0, a0, a1751; RV64I-NEXT: ret752;753; RV64ZBS-LABEL: bseti_i32_30:754; RV64ZBS: # %bb.0:755; RV64ZBS-NEXT: bseti a0, a0, 30756; RV64ZBS-NEXT: ret757 %or = or i32 %a, 1073741824758 ret i32 %or759}760 761define signext i32 @bseti_i32_31(i32 signext %a) nounwind {762; CHECK-LABEL: bseti_i32_31:763; CHECK: # %bb.0:764; CHECK-NEXT: lui a1, 524288765; CHECK-NEXT: or a0, a0, a1766; CHECK-NEXT: ret767 %or = or i32 %a, 2147483648768 ret i32 %or769}770 771define signext i32 @bseti_i32_31_allWUsers(i32 signext %a) nounwind {772; RV64I-LABEL: bseti_i32_31_allWUsers:773; RV64I: # %bb.0:774; RV64I-NEXT: lui a1, 524288775; RV64I-NEXT: or a0, a0, a1776; RV64I-NEXT: addiw a0, a0, 1777; RV64I-NEXT: ret778;779; RV64ZBS-LABEL: bseti_i32_31_allWUsers:780; RV64ZBS: # %bb.0:781; RV64ZBS-NEXT: bseti a0, a0, 31782; RV64ZBS-NEXT: addiw a0, a0, 1783; RV64ZBS-NEXT: ret784 %or = or i32 %a, 2147483648785 %add = add i32 %or, 1786 ret i32 %add787}788 789define i64 @bseti_i64_10(i64 %a) nounwind {790; CHECK-LABEL: bseti_i64_10:791; CHECK: # %bb.0:792; CHECK-NEXT: ori a0, a0, 1024793; CHECK-NEXT: ret794 %or = or i64 %a, 1024795 ret i64 %or796}797 798define i64 @bseti_i64_11(i64 %a) nounwind {799; RV64I-LABEL: bseti_i64_11:800; RV64I: # %bb.0:801; RV64I-NEXT: li a1, 1802; RV64I-NEXT: slli a1, a1, 11803; RV64I-NEXT: or a0, a0, a1804; RV64I-NEXT: ret805;806; RV64ZBS-LABEL: bseti_i64_11:807; RV64ZBS: # %bb.0:808; RV64ZBS-NEXT: bseti a0, a0, 11809; RV64ZBS-NEXT: ret810 %or = or i64 %a, 2048811 ret i64 %or812}813 814define i64 @bseti_i64_30(i64 %a) nounwind {815; RV64I-LABEL: bseti_i64_30:816; RV64I: # %bb.0:817; RV64I-NEXT: lui a1, 262144818; RV64I-NEXT: or a0, a0, a1819; RV64I-NEXT: ret820;821; RV64ZBS-LABEL: bseti_i64_30:822; RV64ZBS: # %bb.0:823; RV64ZBS-NEXT: bseti a0, a0, 30824; RV64ZBS-NEXT: ret825 %or = or i64 %a, 1073741824826 ret i64 %or827}828 829define i64 @bseti_i64_31(i64 %a) nounwind {830; RV64I-LABEL: bseti_i64_31:831; RV64I: # %bb.0:832; RV64I-NEXT: li a1, 1833; RV64I-NEXT: slli a1, a1, 31834; RV64I-NEXT: or a0, a0, a1835; RV64I-NEXT: ret836;837; RV64ZBS-LABEL: bseti_i64_31:838; RV64ZBS: # %bb.0:839; RV64ZBS-NEXT: bseti a0, a0, 31840; RV64ZBS-NEXT: ret841 %or = or i64 %a, 2147483648842 ret i64 %or843}844 845define i64 @bseti_i64_62(i64 %a) nounwind {846; RV64I-LABEL: bseti_i64_62:847; RV64I: # %bb.0:848; RV64I-NEXT: li a1, 1849; RV64I-NEXT: slli a1, a1, 62850; RV64I-NEXT: or a0, a0, a1851; RV64I-NEXT: ret852;853; RV64ZBS-LABEL: bseti_i64_62:854; RV64ZBS: # %bb.0:855; RV64ZBS-NEXT: bseti a0, a0, 62856; RV64ZBS-NEXT: ret857 %or = or i64 %a, 4611686018427387904858 ret i64 %or859}860 861define i64 @bseti_i64_63(i64 %a) nounwind {862; RV64I-LABEL: bseti_i64_63:863; RV64I: # %bb.0:864; RV64I-NEXT: li a1, -1865; RV64I-NEXT: slli a1, a1, 63866; RV64I-NEXT: or a0, a0, a1867; RV64I-NEXT: ret868;869; RV64ZBS-LABEL: bseti_i64_63:870; RV64ZBS: # %bb.0:871; RV64ZBS-NEXT: bseti a0, a0, 63872; RV64ZBS-NEXT: ret873 %or = or i64 %a, 9223372036854775808874 ret i64 %or875}876 877define signext i32 @binvi_i32_10(i32 signext %a) nounwind {878; CHECK-LABEL: binvi_i32_10:879; CHECK: # %bb.0:880; CHECK-NEXT: xori a0, a0, 1024881; CHECK-NEXT: ret882 %xor = xor i32 %a, 1024883 ret i32 %xor884}885 886define signext i32 @binvi_i32_11(i32 signext %a) nounwind {887; RV64I-LABEL: binvi_i32_11:888; RV64I: # %bb.0:889; RV64I-NEXT: li a1, 1890; RV64I-NEXT: slli a1, a1, 11891; RV64I-NEXT: xor a0, a0, a1892; RV64I-NEXT: ret893;894; RV64ZBS-LABEL: binvi_i32_11:895; RV64ZBS: # %bb.0:896; RV64ZBS-NEXT: binvi a0, a0, 11897; RV64ZBS-NEXT: ret898 %xor = xor i32 %a, 2048899 ret i32 %xor900}901 902define signext i32 @binvi_i32_30(i32 signext %a) nounwind {903; RV64I-LABEL: binvi_i32_30:904; RV64I: # %bb.0:905; RV64I-NEXT: lui a1, 262144906; RV64I-NEXT: xor a0, a0, a1907; RV64I-NEXT: ret908;909; RV64ZBS-LABEL: binvi_i32_30:910; RV64ZBS: # %bb.0:911; RV64ZBS-NEXT: binvi a0, a0, 30912; RV64ZBS-NEXT: ret913 %xor = xor i32 %a, 1073741824914 ret i32 %xor915}916 917define signext i32 @binvi_i32_31(i32 signext %a) nounwind {918; CHECK-LABEL: binvi_i32_31:919; CHECK: # %bb.0:920; CHECK-NEXT: lui a1, 524288921; CHECK-NEXT: xor a0, a0, a1922; CHECK-NEXT: ret923 %xor = xor i32 %a, 2147483648924 ret i32 %xor925}926 927define void @binvi_i32_31_allWUsers(i32 signext %a, ptr %p) nounwind {928; RV64I-LABEL: binvi_i32_31_allWUsers:929; RV64I: # %bb.0:930; RV64I-NEXT: lui a2, 524288931; RV64I-NEXT: xor a0, a0, a2932; RV64I-NEXT: sw a0, 0(a1)933; RV64I-NEXT: ret934;935; RV64ZBS-LABEL: binvi_i32_31_allWUsers:936; RV64ZBS: # %bb.0:937; RV64ZBS-NEXT: binvi a0, a0, 31938; RV64ZBS-NEXT: sw a0, 0(a1)939; RV64ZBS-NEXT: ret940 %xor = xor i32 %a, 2147483648941 store i32 %xor, ptr %p942 ret void943}944 945define i64 @binvi_i64_10(i64 %a) nounwind {946; CHECK-LABEL: binvi_i64_10:947; CHECK: # %bb.0:948; CHECK-NEXT: xori a0, a0, 1024949; CHECK-NEXT: ret950 %xor = xor i64 %a, 1024951 ret i64 %xor952}953 954define i64 @binvi_i64_11(i64 %a) nounwind {955; RV64I-LABEL: binvi_i64_11:956; RV64I: # %bb.0:957; RV64I-NEXT: li a1, 1958; RV64I-NEXT: slli a1, a1, 11959; RV64I-NEXT: xor a0, a0, a1960; RV64I-NEXT: ret961;962; RV64ZBS-LABEL: binvi_i64_11:963; RV64ZBS: # %bb.0:964; RV64ZBS-NEXT: binvi a0, a0, 11965; RV64ZBS-NEXT: ret966 %xor = xor i64 %a, 2048967 ret i64 %xor968}969 970define i64 @binvi_i64_30(i64 %a) nounwind {971; RV64I-LABEL: binvi_i64_30:972; RV64I: # %bb.0:973; RV64I-NEXT: lui a1, 262144974; RV64I-NEXT: xor a0, a0, a1975; RV64I-NEXT: ret976;977; RV64ZBS-LABEL: binvi_i64_30:978; RV64ZBS: # %bb.0:979; RV64ZBS-NEXT: binvi a0, a0, 30980; RV64ZBS-NEXT: ret981 %xor = xor i64 %a, 1073741824982 ret i64 %xor983}984 985define i64 @binvi_i64_31(i64 %a) nounwind {986; RV64I-LABEL: binvi_i64_31:987; RV64I: # %bb.0:988; RV64I-NEXT: li a1, 1989; RV64I-NEXT: slli a1, a1, 31990; RV64I-NEXT: xor a0, a0, a1991; RV64I-NEXT: ret992;993; RV64ZBS-LABEL: binvi_i64_31:994; RV64ZBS: # %bb.0:995; RV64ZBS-NEXT: binvi a0, a0, 31996; RV64ZBS-NEXT: ret997 %xor = xor i64 %a, 2147483648998 ret i64 %xor999}1000 1001define i64 @binvi_i64_62(i64 %a) nounwind {1002; RV64I-LABEL: binvi_i64_62:1003; RV64I: # %bb.0:1004; RV64I-NEXT: li a1, 11005; RV64I-NEXT: slli a1, a1, 621006; RV64I-NEXT: xor a0, a0, a11007; RV64I-NEXT: ret1008;1009; RV64ZBS-LABEL: binvi_i64_62:1010; RV64ZBS: # %bb.0:1011; RV64ZBS-NEXT: binvi a0, a0, 621012; RV64ZBS-NEXT: ret1013 %xor = xor i64 %a, 46116860184273879041014 ret i64 %xor1015}1016 1017define i64 @binvi_i64_63(i64 %a) nounwind {1018; RV64I-LABEL: binvi_i64_63:1019; RV64I: # %bb.0:1020; RV64I-NEXT: li a1, -11021; RV64I-NEXT: slli a1, a1, 631022; RV64I-NEXT: xor a0, a0, a11023; RV64I-NEXT: ret1024;1025; RV64ZBS-LABEL: binvi_i64_63:1026; RV64ZBS: # %bb.0:1027; RV64ZBS-NEXT: binvi a0, a0, 631028; RV64ZBS-NEXT: ret1029 %xor = xor i64 %a, 92233720368547758081030 ret i64 %xor1031}1032 1033define i64 @xor_i64_large(i64 %a) nounwind {1034; RV64I-LABEL: xor_i64_large:1035; RV64I: # %bb.0:1036; RV64I-NEXT: li a1, 11037; RV64I-NEXT: slli a1, a1, 321038; RV64I-NEXT: addi a1, a1, 11039; RV64I-NEXT: xor a0, a0, a11040; RV64I-NEXT: ret1041;1042; RV64ZBS-LABEL: xor_i64_large:1043; RV64ZBS: # %bb.0:1044; RV64ZBS-NEXT: binvi a0, a0, 01045; RV64ZBS-NEXT: binvi a0, a0, 321046; RV64ZBS-NEXT: ret1047 %xor = xor i64 %a, 42949672971048 ret i64 %xor1049}1050 1051define i64 @xor_i64_4099(i64 %a) nounwind {1052; RV64I-LABEL: xor_i64_4099:1053; RV64I: # %bb.0:1054; RV64I-NEXT: lui a1, 11055; RV64I-NEXT: addi a1, a1, 31056; RV64I-NEXT: xor a0, a0, a11057; RV64I-NEXT: ret1058;1059; RV64ZBS-LABEL: xor_i64_4099:1060; RV64ZBS: # %bb.0:1061; RV64ZBS-NEXT: xori a0, a0, 31062; RV64ZBS-NEXT: binvi a0, a0, 121063; RV64ZBS-NEXT: ret1064 %xor = xor i64 %a, 40991065 ret i64 %xor1066}1067 1068define i64 @xor_i64_96(i64 %a) nounwind {1069; CHECK-LABEL: xor_i64_96:1070; CHECK: # %bb.0:1071; CHECK-NEXT: xori a0, a0, 961072; CHECK-NEXT: ret1073 %xor = xor i64 %a, 961074 ret i64 %xor1075}1076 1077define i64 @or_i64_large(i64 %a) nounwind {1078; RV64I-LABEL: or_i64_large:1079; RV64I: # %bb.0:1080; RV64I-NEXT: li a1, 11081; RV64I-NEXT: slli a1, a1, 321082; RV64I-NEXT: addi a1, a1, 11083; RV64I-NEXT: or a0, a0, a11084; RV64I-NEXT: ret1085;1086; RV64ZBS-LABEL: or_i64_large:1087; RV64ZBS: # %bb.0:1088; RV64ZBS-NEXT: bseti a0, a0, 01089; RV64ZBS-NEXT: bseti a0, a0, 321090; RV64ZBS-NEXT: ret1091 %or = or i64 %a, 42949672971092 ret i64 %or1093}1094 1095define i64 @xor_i64_66901(i64 %a) nounwind {1096; RV64I-LABEL: xor_i64_66901:1097; RV64I: # %bb.0:1098; RV64I-NEXT: lui a1, 161099; RV64I-NEXT: addi a1, a1, 13651100; RV64I-NEXT: xor a0, a0, a11101; RV64I-NEXT: ret1102;1103; RV64ZBS-LABEL: xor_i64_66901:1104; RV64ZBS: # %bb.0:1105; RV64ZBS-NEXT: xori a0, a0, 13651106; RV64ZBS-NEXT: binvi a0, a0, 161107; RV64ZBS-NEXT: ret1108 %xor = xor i64 %a, 669011109 ret i64 %xor1110}1111 1112define i64 @or_i64_4099(i64 %a) nounwind {1113; RV64I-LABEL: or_i64_4099:1114; RV64I: # %bb.0:1115; RV64I-NEXT: lui a1, 11116; RV64I-NEXT: addi a1, a1, 31117; RV64I-NEXT: or a0, a0, a11118; RV64I-NEXT: ret1119;1120; RV64ZBS-LABEL: or_i64_4099:1121; RV64ZBS: # %bb.0:1122; RV64ZBS-NEXT: ori a0, a0, 31123; RV64ZBS-NEXT: bseti a0, a0, 121124; RV64ZBS-NEXT: ret1125 %or = or i64 %a, 40991126 ret i64 %or1127}1128 1129define i64 @or_i64_96(i64 %a) nounwind {1130; CHECK-LABEL: or_i64_96:1131; CHECK: # %bb.0:1132; CHECK-NEXT: ori a0, a0, 961133; CHECK-NEXT: ret1134 %or = or i64 %a, 961135 ret i64 %or1136}1137 1138define i64 @or_i64_66901(i64 %a) nounwind {1139; RV64I-LABEL: or_i64_66901:1140; RV64I: # %bb.0:1141; RV64I-NEXT: lui a1, 161142; RV64I-NEXT: addi a1, a1, 13651143; RV64I-NEXT: or a0, a0, a11144; RV64I-NEXT: ret1145;1146; RV64ZBS-LABEL: or_i64_66901:1147; RV64ZBS: # %bb.0:1148; RV64ZBS-NEXT: ori a0, a0, 13651149; RV64ZBS-NEXT: bseti a0, a0, 161150; RV64ZBS-NEXT: ret1151 %or = or i64 %a, 669011152 ret i64 %or1153}1154 1155define signext i32 @bset_trailing_ones_i32_mask(i32 signext %a) nounwind {1156; RV64I-LABEL: bset_trailing_ones_i32_mask:1157; RV64I: # %bb.0:1158; RV64I-NEXT: li a1, -11159; RV64I-NEXT: sllw a0, a1, a01160; RV64I-NEXT: not a0, a01161; RV64I-NEXT: ret1162;1163; RV64ZBS-LABEL: bset_trailing_ones_i32_mask:1164; RV64ZBS: # %bb.0:1165; RV64ZBS-NEXT: andi a0, a0, 311166; RV64ZBS-NEXT: bset a0, zero, a01167; RV64ZBS-NEXT: addi a0, a0, -11168; RV64ZBS-NEXT: ret1169 %and = and i32 %a, 311170 %shift = shl nsw i32 -1, %and1171 %not = xor i32 %shift, -11172 ret i32 %not1173}1174 1175define signext i32 @bset_trailing_ones_i32_no_mask(i32 signext %a) nounwind {1176; RV64I-LABEL: bset_trailing_ones_i32_no_mask:1177; RV64I: # %bb.0:1178; RV64I-NEXT: li a1, -11179; RV64I-NEXT: sllw a0, a1, a01180; RV64I-NEXT: not a0, a01181; RV64I-NEXT: ret1182;1183; RV64ZBS-LABEL: bset_trailing_ones_i32_no_mask:1184; RV64ZBS: # %bb.0:1185; RV64ZBS-NEXT: bset a0, zero, a01186; RV64ZBS-NEXT: addiw a0, a0, -11187; RV64ZBS-NEXT: ret1188 %shift = shl nsw i32 -1, %a1189 %not = xor i32 %shift, -11190 ret i32 %not1191}1192 1193define signext i64 @bset_trailing_ones_i64_mask(i64 signext %a) nounwind {1194; RV64I-LABEL: bset_trailing_ones_i64_mask:1195; RV64I: # %bb.0:1196; RV64I-NEXT: li a1, -11197; RV64I-NEXT: sll a0, a1, a01198; RV64I-NEXT: not a0, a01199; RV64I-NEXT: ret1200;1201; RV64ZBS-LABEL: bset_trailing_ones_i64_mask:1202; RV64ZBS: # %bb.0:1203; RV64ZBS-NEXT: bset a0, zero, a01204; RV64ZBS-NEXT: addi a0, a0, -11205; RV64ZBS-NEXT: ret1206 %and = and i64 %a, 631207 %shift = shl nsw i64 -1, %and1208 %not = xor i64 %shift, -11209 ret i64 %not1210}1211 1212define signext i64 @bset_trailing_ones_i64_no_mask(i64 signext %a) nounwind {1213; RV64I-LABEL: bset_trailing_ones_i64_no_mask:1214; RV64I: # %bb.0:1215; RV64I-NEXT: li a1, -11216; RV64I-NEXT: sll a0, a1, a01217; RV64I-NEXT: not a0, a01218; RV64I-NEXT: ret1219;1220; RV64ZBS-LABEL: bset_trailing_ones_i64_no_mask:1221; RV64ZBS: # %bb.0:1222; RV64ZBS-NEXT: bset a0, zero, a01223; RV64ZBS-NEXT: addi a0, a0, -11224; RV64ZBS-NEXT: ret1225 %shift = shl nsw i64 -1, %a1226 %not = xor i64 %shift, -11227 ret i64 %not1228}1229 1230define i1 @icmp_eq_pow2(i32 signext %x) nounwind {1231; RV64I-LABEL: icmp_eq_pow2:1232; RV64I: # %bb.0:1233; RV64I-NEXT: lui a1, 81234; RV64I-NEXT: xor a0, a0, a11235; RV64I-NEXT: seqz a0, a01236; RV64I-NEXT: ret1237;1238; RV64ZBS-LABEL: icmp_eq_pow2:1239; RV64ZBS: # %bb.0:1240; RV64ZBS-NEXT: binvi a0, a0, 151241; RV64ZBS-NEXT: seqz a0, a01242; RV64ZBS-NEXT: ret1243 %cmp = icmp eq i32 %x, 327681244 ret i1 %cmp1245}1246 1247define i1 @icmp_eq_pow2_64(i64 %x) nounwind {1248; RV64I-LABEL: icmp_eq_pow2_64:1249; RV64I: # %bb.0:1250; RV64I-NEXT: li a1, 11251; RV64I-NEXT: slli a1, a1, 401252; RV64I-NEXT: xor a0, a0, a11253; RV64I-NEXT: seqz a0, a01254; RV64I-NEXT: ret1255;1256; RV64ZBS-LABEL: icmp_eq_pow2_64:1257; RV64ZBS: # %bb.0:1258; RV64ZBS-NEXT: binvi a0, a0, 401259; RV64ZBS-NEXT: seqz a0, a01260; RV64ZBS-NEXT: ret1261 %cmp = icmp eq i64 %x, 10995116277761262 ret i1 %cmp1263}1264 1265define i1 @icmp_ne_pow2(i32 signext %x) nounwind {1266; RV64I-LABEL: icmp_ne_pow2:1267; RV64I: # %bb.0:1268; RV64I-NEXT: lui a1, 81269; RV64I-NEXT: xor a0, a0, a11270; RV64I-NEXT: seqz a0, a01271; RV64I-NEXT: ret1272;1273; RV64ZBS-LABEL: icmp_ne_pow2:1274; RV64ZBS: # %bb.0:1275; RV64ZBS-NEXT: binvi a0, a0, 151276; RV64ZBS-NEXT: seqz a0, a01277; RV64ZBS-NEXT: ret1278 %cmp = icmp eq i32 %x, 327681279 ret i1 %cmp1280}1281 1282define i1 @icmp_eq_nonpow2(i32 signext %x) nounwind {1283; CHECK-LABEL: icmp_eq_nonpow2:1284; CHECK: # %bb.0:1285; CHECK-NEXT: lui a1, 81286; CHECK-NEXT: addi a1, a1, -11287; CHECK-NEXT: xor a0, a0, a11288; CHECK-NEXT: seqz a0, a01289; CHECK-NEXT: ret1290 %cmp = icmp eq i32 %x, 327671291 ret i1 %cmp1292}1293 1294define signext i32 @fold_sextinreg_shl_to_sllw(i64 %x) nounwind {1295; CHECK-LABEL: fold_sextinreg_shl_to_sllw:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: li a1, 11298; CHECK-NEXT: sllw a0, a1, a01299; CHECK-NEXT: ret1300entry:1301 %mask = and i64 %x, 311302 %shl = shl i64 1, %mask1303 %trunc = trunc i64 %shl to i321304 ret i32 %trunc1305}1306 1307define signext i32 @fold_sextinreg_shl_to_sllw_large_shamt(i64 %x) nounwind {1308; RV64I-LABEL: fold_sextinreg_shl_to_sllw_large_shamt:1309; RV64I: # %bb.0: # %entry1310; RV64I-NEXT: li a1, 11311; RV64I-NEXT: sll a0, a1, a01312; RV64I-NEXT: sext.w a0, a01313; RV64I-NEXT: ret1314;1315; RV64ZBS-LABEL: fold_sextinreg_shl_to_sllw_large_shamt:1316; RV64ZBS: # %bb.0: # %entry1317; RV64ZBS-NEXT: bset a0, zero, a01318; RV64ZBS-NEXT: sext.w a0, a01319; RV64ZBS-NEXT: ret1320entry:1321 %mask = and i64 %x, 631322 %shl = shl i64 1, %mask1323 %trunc = trunc i64 %shl to i321324 ret i32 %trunc1325}1326