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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \3; RUN: -target-abi lp64f -disable-strictnode-mutation < %s | \4; RUN: FileCheck %s -check-prefix=RV64IZFH5; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \6; RUN: -target-abi lp64 -disable-strictnode-mutation < %s | \7; RUN: FileCheck %s -check-prefix=RV64IZHINX8 9; This file exhaustively checks half<->i32 conversions. In general,10; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is11; generated for an fpto[s|u]i conversion if the result doesn't fit in the12; target type.13 14define i32 @aext_fptosi(half %a) nounwind strictfp {15; RV64IZFH-LABEL: aext_fptosi:16; RV64IZFH: # %bb.0:17; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz18; RV64IZFH-NEXT: ret19;20; RV64IZHINX-LABEL: aext_fptosi:21; RV64IZHINX: # %bb.0:22; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz23; RV64IZHINX-NEXT: ret24 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")25 ret i32 %126}27 28define signext i32 @sext_fptosi(half %a) nounwind strictfp {29; RV64IZFH-LABEL: sext_fptosi:30; RV64IZFH: # %bb.0:31; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz32; RV64IZFH-NEXT: ret33;34; RV64IZHINX-LABEL: sext_fptosi:35; RV64IZHINX: # %bb.0:36; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz37; RV64IZHINX-NEXT: ret38 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")39 ret i32 %140}41 42define zeroext i32 @zext_fptosi(half %a) nounwind strictfp {43; RV64IZFH-LABEL: zext_fptosi:44; RV64IZFH: # %bb.0:45; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz46; RV64IZFH-NEXT: slli a0, a0, 3247; RV64IZFH-NEXT: srli a0, a0, 3248; RV64IZFH-NEXT: ret49;50; RV64IZHINX-LABEL: zext_fptosi:51; RV64IZHINX: # %bb.0:52; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz53; RV64IZHINX-NEXT: slli a0, a0, 3254; RV64IZHINX-NEXT: srli a0, a0, 3255; RV64IZHINX-NEXT: ret56 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")57 ret i32 %158}59 60define i32 @aext_fptoui(half %a) nounwind strictfp {61; RV64IZFH-LABEL: aext_fptoui:62; RV64IZFH: # %bb.0:63; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz64; RV64IZFH-NEXT: ret65;66; RV64IZHINX-LABEL: aext_fptoui:67; RV64IZHINX: # %bb.0:68; RV64IZHINX-NEXT: fcvt.wu.h a0, a0, rtz69; RV64IZHINX-NEXT: ret70 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")71 ret i32 %172}73 74define signext i32 @sext_fptoui(half %a) nounwind strictfp {75; RV64IZFH-LABEL: sext_fptoui:76; RV64IZFH: # %bb.0:77; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz78; RV64IZFH-NEXT: ret79;80; RV64IZHINX-LABEL: sext_fptoui:81; RV64IZHINX: # %bb.0:82; RV64IZHINX-NEXT: fcvt.wu.h a0, a0, rtz83; RV64IZHINX-NEXT: ret84 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")85 ret i32 %186}87 88define zeroext i32 @zext_fptoui(half %a) nounwind strictfp {89; RV64IZFH-LABEL: zext_fptoui:90; RV64IZFH: # %bb.0:91; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz92; RV64IZFH-NEXT: ret93;94; RV64IZHINX-LABEL: zext_fptoui:95; RV64IZHINX: # %bb.0:96; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz97; RV64IZHINX-NEXT: ret98 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")99 ret i32 %1100}101 102define half @uitofp_aext_i32_to_f16(i32 %a) nounwind strictfp {103; RV64IZFH-LABEL: uitofp_aext_i32_to_f16:104; RV64IZFH: # %bb.0:105; RV64IZFH-NEXT: fcvt.h.wu fa0, a0106; RV64IZFH-NEXT: ret107;108; RV64IZHINX-LABEL: uitofp_aext_i32_to_f16:109; RV64IZHINX: # %bb.0:110; RV64IZHINX-NEXT: fcvt.h.wu a0, a0111; RV64IZHINX-NEXT: ret112 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")113 ret half %1114}115 116define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind strictfp {117; RV64IZFH-LABEL: uitofp_sext_i32_to_f16:118; RV64IZFH: # %bb.0:119; RV64IZFH-NEXT: fcvt.h.wu fa0, a0120; RV64IZFH-NEXT: ret121;122; RV64IZHINX-LABEL: uitofp_sext_i32_to_f16:123; RV64IZHINX: # %bb.0:124; RV64IZHINX-NEXT: fcvt.h.wu a0, a0125; RV64IZHINX-NEXT: ret126 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")127 ret half %1128}129 130define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind strictfp {131; RV64IZFH-LABEL: uitofp_zext_i32_to_f16:132; RV64IZFH: # %bb.0:133; RV64IZFH-NEXT: fcvt.h.wu fa0, a0134; RV64IZFH-NEXT: ret135;136; RV64IZHINX-LABEL: uitofp_zext_i32_to_f16:137; RV64IZHINX: # %bb.0:138; RV64IZHINX-NEXT: fcvt.h.wu a0, a0139; RV64IZHINX-NEXT: ret140 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")141 ret half %1142}143 144define half @sitofp_aext_i32_to_f16(i32 %a) nounwind strictfp {145; RV64IZFH-LABEL: sitofp_aext_i32_to_f16:146; RV64IZFH: # %bb.0:147; RV64IZFH-NEXT: fcvt.h.w fa0, a0148; RV64IZFH-NEXT: ret149;150; RV64IZHINX-LABEL: sitofp_aext_i32_to_f16:151; RV64IZHINX: # %bb.0:152; RV64IZHINX-NEXT: fcvt.h.w a0, a0153; RV64IZHINX-NEXT: ret154 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")155 ret half %1156}157 158define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind strictfp {159; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:160; RV64IZFH: # %bb.0:161; RV64IZFH-NEXT: fcvt.h.w fa0, a0162; RV64IZFH-NEXT: ret163;164; RV64IZHINX-LABEL: sitofp_sext_i32_to_f16:165; RV64IZHINX: # %bb.0:166; RV64IZHINX-NEXT: fcvt.h.w a0, a0167; RV64IZHINX-NEXT: ret168 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")169 ret half %1170}171 172define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind strictfp {173; RV64IZFH-LABEL: sitofp_zext_i32_to_f16:174; RV64IZFH: # %bb.0:175; RV64IZFH-NEXT: fcvt.h.w fa0, a0176; RV64IZFH-NEXT: ret177;178; RV64IZHINX-LABEL: sitofp_zext_i32_to_f16:179; RV64IZHINX: # %bb.0:180; RV64IZHINX-NEXT: fcvt.h.w a0, a0181; RV64IZHINX-NEXT: ret182 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")183 ret half %1184}185