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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \3; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFH4; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \5; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINX6 7; This file exhaustively checks half<->i32 conversions. In general,8; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is9; generated for an fpto[s|u]i conversion if the result doesn't fit in the10; target type.11 12define i32 @aext_fptosi(half %a) nounwind {13; RV64IZFH-LABEL: aext_fptosi:14; RV64IZFH: # %bb.0:15; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz16; RV64IZFH-NEXT: ret17;18; RV64IZHINX-LABEL: aext_fptosi:19; RV64IZHINX: # %bb.0:20; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz21; RV64IZHINX-NEXT: ret22 %1 = fptosi half %a to i3223 ret i32 %124}25 26define signext i32 @sext_fptosi(half %a) nounwind {27; RV64IZFH-LABEL: sext_fptosi:28; RV64IZFH: # %bb.0:29; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz30; RV64IZFH-NEXT: ret31;32; RV64IZHINX-LABEL: sext_fptosi:33; RV64IZHINX: # %bb.0:34; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz35; RV64IZHINX-NEXT: ret36 %1 = fptosi half %a to i3237 ret i32 %138}39 40define zeroext i32 @zext_fptosi(half %a) nounwind {41; RV64IZFH-LABEL: zext_fptosi:42; RV64IZFH: # %bb.0:43; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz44; RV64IZFH-NEXT: slli a0, a0, 3245; RV64IZFH-NEXT: srli a0, a0, 3246; RV64IZFH-NEXT: ret47;48; RV64IZHINX-LABEL: zext_fptosi:49; RV64IZHINX: # %bb.0:50; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rtz51; RV64IZHINX-NEXT: slli a0, a0, 3252; RV64IZHINX-NEXT: srli a0, a0, 3253; RV64IZHINX-NEXT: ret54 %1 = fptosi half %a to i3255 ret i32 %156}57 58define i32 @aext_fptoui(half %a) nounwind {59; RV64IZFH-LABEL: aext_fptoui:60; RV64IZFH: # %bb.0:61; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz62; RV64IZFH-NEXT: ret63;64; RV64IZHINX-LABEL: aext_fptoui:65; RV64IZHINX: # %bb.0:66; RV64IZHINX-NEXT: fcvt.wu.h a0, a0, rtz67; RV64IZHINX-NEXT: ret68 %1 = fptoui half %a to i3269 ret i32 %170}71 72define signext i32 @sext_fptoui(half %a) nounwind {73; RV64IZFH-LABEL: sext_fptoui:74; RV64IZFH: # %bb.0:75; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz76; RV64IZFH-NEXT: ret77;78; RV64IZHINX-LABEL: sext_fptoui:79; RV64IZHINX: # %bb.0:80; RV64IZHINX-NEXT: fcvt.wu.h a0, a0, rtz81; RV64IZHINX-NEXT: ret82 %1 = fptoui half %a to i3283 ret i32 %184}85 86define zeroext i32 @zext_fptoui(half %a) nounwind {87; RV64IZFH-LABEL: zext_fptoui:88; RV64IZFH: # %bb.0:89; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz90; RV64IZFH-NEXT: ret91;92; RV64IZHINX-LABEL: zext_fptoui:93; RV64IZHINX: # %bb.0:94; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz95; RV64IZHINX-NEXT: ret96 %1 = fptoui half %a to i3297 ret i32 %198}99 100define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {101; RV64IZFH-LABEL: bcvt_f16_to_aext_i16:102; RV64IZFH: # %bb.0:103; RV64IZFH-NEXT: fadd.h fa5, fa0, fa1104; RV64IZFH-NEXT: fmv.x.h a0, fa5105; RV64IZFH-NEXT: ret106;107; RV64IZHINX-LABEL: bcvt_f16_to_aext_i16:108; RV64IZHINX: # %bb.0:109; RV64IZHINX-NEXT: fadd.h a0, a0, a1110; RV64IZHINX-NEXT: ret111 %1 = fadd half %a, %b112 %2 = bitcast half %1 to i16113 ret i16 %2114}115 116define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {117; RV64IZFH-LABEL: bcvt_f16_to_sext_i16:118; RV64IZFH: # %bb.0:119; RV64IZFH-NEXT: fadd.h fa5, fa0, fa1120; RV64IZFH-NEXT: fmv.x.h a0, fa5121; RV64IZFH-NEXT: ret122;123; RV64IZHINX-LABEL: bcvt_f16_to_sext_i16:124; RV64IZHINX: # %bb.0:125; RV64IZHINX-NEXT: fadd.h a0, a0, a1126; RV64IZHINX-NEXT: slli a0, a0, 48127; RV64IZHINX-NEXT: srai a0, a0, 48128; RV64IZHINX-NEXT: ret129 %1 = fadd half %a, %b130 %2 = bitcast half %1 to i16131 ret i16 %2132}133 134define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {135; RV64IZFH-LABEL: bcvt_f16_to_zext_i16:136; RV64IZFH: # %bb.0:137; RV64IZFH-NEXT: fadd.h fa5, fa0, fa1138; RV64IZFH-NEXT: fmv.x.h a0, fa5139; RV64IZFH-NEXT: slli a0, a0, 48140; RV64IZFH-NEXT: srli a0, a0, 48141; RV64IZFH-NEXT: ret142;143; RV64IZHINX-LABEL: bcvt_f16_to_zext_i16:144; RV64IZHINX: # %bb.0:145; RV64IZHINX-NEXT: fadd.h a0, a0, a1146; RV64IZHINX-NEXT: slli a0, a0, 48147; RV64IZHINX-NEXT: srli a0, a0, 48148; RV64IZHINX-NEXT: ret149 %1 = fadd half %a, %b150 %2 = bitcast half %1 to i16151 ret i16 %2152}153 154define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {155; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16:156; RV64IZFH: # %bb.0:157; RV64IZFH-NEXT: fmv.h.x fa5, a0158; RV64IZFH-NEXT: fmv.h.x fa4, a1159; RV64IZFH-NEXT: fadd.h fa0, fa5, fa4160; RV64IZFH-NEXT: ret161;162; RV64IZHINX-LABEL: bcvt_i64_to_f16_via_i16:163; RV64IZHINX: # %bb.0:164; RV64IZHINX-NEXT: fadd.h a0, a0, a1165; RV64IZHINX-NEXT: ret166 %1 = trunc i64 %a to i16167 %2 = trunc i64 %b to i16168 %3 = bitcast i16 %1 to half169 %4 = bitcast i16 %2 to half170 %5 = fadd half %3, %4171 ret half %5172}173 174define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {175; RV64IZFH-LABEL: uitofp_aext_i32_to_f16:176; RV64IZFH: # %bb.0:177; RV64IZFH-NEXT: fcvt.h.wu fa0, a0178; RV64IZFH-NEXT: ret179;180; RV64IZHINX-LABEL: uitofp_aext_i32_to_f16:181; RV64IZHINX: # %bb.0:182; RV64IZHINX-NEXT: fcvt.h.wu a0, a0183; RV64IZHINX-NEXT: ret184 %1 = uitofp i32 %a to half185 ret half %1186}187 188define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {189; RV64IZFH-LABEL: uitofp_sext_i32_to_f16:190; RV64IZFH: # %bb.0:191; RV64IZFH-NEXT: fcvt.h.wu fa0, a0192; RV64IZFH-NEXT: ret193;194; RV64IZHINX-LABEL: uitofp_sext_i32_to_f16:195; RV64IZHINX: # %bb.0:196; RV64IZHINX-NEXT: fcvt.h.wu a0, a0197; RV64IZHINX-NEXT: ret198 %1 = uitofp i32 %a to half199 ret half %1200}201 202define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {203; RV64IZFH-LABEL: uitofp_zext_i32_to_f16:204; RV64IZFH: # %bb.0:205; RV64IZFH-NEXT: fcvt.h.wu fa0, a0206; RV64IZFH-NEXT: ret207;208; RV64IZHINX-LABEL: uitofp_zext_i32_to_f16:209; RV64IZHINX: # %bb.0:210; RV64IZHINX-NEXT: fcvt.h.wu a0, a0211; RV64IZHINX-NEXT: ret212 %1 = uitofp i32 %a to half213 ret half %1214}215 216define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {217; RV64IZFH-LABEL: sitofp_aext_i32_to_f16:218; RV64IZFH: # %bb.0:219; RV64IZFH-NEXT: fcvt.h.w fa0, a0220; RV64IZFH-NEXT: ret221;222; RV64IZHINX-LABEL: sitofp_aext_i32_to_f16:223; RV64IZHINX: # %bb.0:224; RV64IZHINX-NEXT: fcvt.h.w a0, a0225; RV64IZHINX-NEXT: ret226 %1 = sitofp i32 %a to half227 ret half %1228}229 230define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {231; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:232; RV64IZFH: # %bb.0:233; RV64IZFH-NEXT: fcvt.h.w fa0, a0234; RV64IZFH-NEXT: ret235;236; RV64IZHINX-LABEL: sitofp_sext_i32_to_f16:237; RV64IZHINX: # %bb.0:238; RV64IZHINX-NEXT: fcvt.h.w a0, a0239; RV64IZHINX-NEXT: ret240 %1 = sitofp i32 %a to half241 ret half %1242}243 244define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {245; RV64IZFH-LABEL: sitofp_zext_i32_to_f16:246; RV64IZFH: # %bb.0:247; RV64IZFH-NEXT: fcvt.h.w fa0, a0248; RV64IZFH-NEXT: ret249;250; RV64IZHINX-LABEL: sitofp_zext_i32_to_f16:251; RV64IZHINX: # %bb.0:252; RV64IZHINX-NEXT: fcvt.h.w a0, a0253; RV64IZHINX-NEXT: ret254 %1 = sitofp i32 %a to half255 ret half %1256}257