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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+zfh \3; RUN: -verify-machineinstrs -target-abi lp64f | \4; RUN: FileCheck -check-prefix=RV64IZFH %s5; RUN: llc < %s -mtriple=riscv64 -mattr=+d \6; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \7; RUN: FileCheck -check-prefix=RV64IDZFH %s8; RUN: llc < %s -mtriple=riscv64 -mattr=+zhinx \9; RUN: -verify-machineinstrs -target-abi lp64 | \10; RUN: FileCheck -check-prefix=RV64IZHINX %s11; RUN: llc < %s -mtriple=riscv64 -mattr=+zdinx \12; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \13; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s14 15; These intrinsics require half and i64 to be legal types.16 17define i64 @llrint_f16(half %a) nounwind {18; RV64IZFH-LABEL: llrint_f16:19; RV64IZFH: # %bb.0:20; RV64IZFH-NEXT: fcvt.l.h a0, fa021; RV64IZFH-NEXT: ret22;23; RV64IDZFH-LABEL: llrint_f16:24; RV64IDZFH: # %bb.0:25; RV64IDZFH-NEXT: fcvt.l.h a0, fa026; RV64IDZFH-NEXT: ret27;28; RV64IZHINX-LABEL: llrint_f16:29; RV64IZHINX: # %bb.0:30; RV64IZHINX-NEXT: fcvt.l.h a0, a031; RV64IZHINX-NEXT: ret32;33; RV64IZDINXZHINX-LABEL: llrint_f16:34; RV64IZDINXZHINX: # %bb.0:35; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a036; RV64IZDINXZHINX-NEXT: ret37 %1 = call i64 @llvm.llrint.i64.f16(half %a)38 ret i64 %139}40 41define i64 @llround_f16(half %a) nounwind {42; RV64IZFH-LABEL: llround_f16:43; RV64IZFH: # %bb.0:44; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm45; RV64IZFH-NEXT: ret46;47; RV64IDZFH-LABEL: llround_f16:48; RV64IDZFH: # %bb.0:49; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm50; RV64IDZFH-NEXT: ret51;52; RV64IZHINX-LABEL: llround_f16:53; RV64IZHINX: # %bb.0:54; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm55; RV64IZHINX-NEXT: ret56;57; RV64IZDINXZHINX-LABEL: llround_f16:58; RV64IZDINXZHINX: # %bb.0:59; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm60; RV64IZDINXZHINX-NEXT: ret61 %1 = call i64 @llvm.llround.i64.f16(half %a)62 ret i64 %163}64