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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \3; RUN: -target-abi lp64f -disable-strictnode-mutation < %s | \4; RUN: FileCheck %s -check-prefix=RV64IZFHMIN5; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \6; RUN: -target-abi lp64 -disable-strictnode-mutation < %s | \7; RUN: FileCheck %s -check-prefix=RV64IZHINXMIN8 9; This file exhaustively checks half<->i32 conversions.10 11define i32 @aext_fptosi(half %a) nounwind strictfp {12; RV64IZFHMIN-LABEL: aext_fptosi:13; RV64IZFHMIN: # %bb.0:14; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa015; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz16; RV64IZFHMIN-NEXT: ret17;18; RV64IZHINXMIN-LABEL: aext_fptosi:19; RV64IZHINXMIN: # %bb.0:20; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a021; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz22; RV64IZHINXMIN-NEXT: ret23 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")24 ret i32 %125}26 27define signext i32 @sext_fptosi(half %a) nounwind strictfp {28; RV64IZFHMIN-LABEL: sext_fptosi:29; RV64IZFHMIN: # %bb.0:30; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa031; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz32; RV64IZFHMIN-NEXT: ret33;34; RV64IZHINXMIN-LABEL: sext_fptosi:35; RV64IZHINXMIN: # %bb.0:36; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a037; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz38; RV64IZHINXMIN-NEXT: ret39 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")40 ret i32 %141}42 43define zeroext i32 @zext_fptosi(half %a) nounwind strictfp {44; RV64IZFHMIN-LABEL: zext_fptosi:45; RV64IZFHMIN: # %bb.0:46; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa047; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz48; RV64IZFHMIN-NEXT: slli a0, a0, 3249; RV64IZFHMIN-NEXT: srli a0, a0, 3250; RV64IZFHMIN-NEXT: ret51;52; RV64IZHINXMIN-LABEL: zext_fptosi:53; RV64IZHINXMIN: # %bb.0:54; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a055; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz56; RV64IZHINXMIN-NEXT: slli a0, a0, 3257; RV64IZHINXMIN-NEXT: srli a0, a0, 3258; RV64IZHINXMIN-NEXT: ret59 %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict")60 ret i32 %161}62 63define i32 @aext_fptoui(half %a) nounwind strictfp {64; RV64IZFHMIN-LABEL: aext_fptoui:65; RV64IZFHMIN: # %bb.0:66; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa067; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz68; RV64IZFHMIN-NEXT: ret69;70; RV64IZHINXMIN-LABEL: aext_fptoui:71; RV64IZHINXMIN: # %bb.0:72; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a073; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz74; RV64IZHINXMIN-NEXT: ret75 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")76 ret i32 %177}78 79define signext i32 @sext_fptoui(half %a) nounwind strictfp {80; RV64IZFHMIN-LABEL: sext_fptoui:81; RV64IZFHMIN: # %bb.0:82; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa083; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz84; RV64IZFHMIN-NEXT: ret85;86; RV64IZHINXMIN-LABEL: sext_fptoui:87; RV64IZHINXMIN: # %bb.0:88; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a089; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz90; RV64IZHINXMIN-NEXT: ret91 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")92 ret i32 %193}94 95define zeroext i32 @zext_fptoui(half %a) nounwind strictfp {96; RV64IZFHMIN-LABEL: zext_fptoui:97; RV64IZFHMIN: # %bb.0:98; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa099; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz100; RV64IZFHMIN-NEXT: ret101;102; RV64IZHINXMIN-LABEL: zext_fptoui:103; RV64IZHINXMIN: # %bb.0:104; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0105; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz106; RV64IZHINXMIN-NEXT: ret107 %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict")108 ret i32 %1109}110 111define half @uitofp_aext_i32_to_f16(i32 %a) nounwind strictfp {112; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:113; RV64IZFHMIN: # %bb.0:114; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0115; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5116; RV64IZFHMIN-NEXT: ret117;118; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16:119; RV64IZHINXMIN: # %bb.0:120; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0121; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0122; RV64IZHINXMIN-NEXT: ret123 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")124 ret half %1125}126 127define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind strictfp {128; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:129; RV64IZFHMIN: # %bb.0:130; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0131; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5132; RV64IZFHMIN-NEXT: ret133;134; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16:135; RV64IZHINXMIN: # %bb.0:136; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0137; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0138; RV64IZHINXMIN-NEXT: ret139 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")140 ret half %1141}142 143define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind strictfp {144; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:145; RV64IZFHMIN: # %bb.0:146; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0147; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5148; RV64IZFHMIN-NEXT: ret149;150; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16:151; RV64IZHINXMIN: # %bb.0:152; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0153; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0154; RV64IZHINXMIN-NEXT: ret155 %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")156 ret half %1157}158 159define half @sitofp_aext_i32_to_f16(i32 %a) nounwind strictfp {160; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:161; RV64IZFHMIN: # %bb.0:162; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0163; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5164; RV64IZFHMIN-NEXT: ret165;166; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16:167; RV64IZHINXMIN: # %bb.0:168; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0169; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0170; RV64IZHINXMIN-NEXT: ret171 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")172 ret half %1173}174 175define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind strictfp {176; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:177; RV64IZFHMIN: # %bb.0:178; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0179; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5180; RV64IZFHMIN-NEXT: ret181;182; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16:183; RV64IZHINXMIN: # %bb.0:184; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0185; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0186; RV64IZHINXMIN-NEXT: ret187 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")188 ret half %1189}190 191define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind strictfp {192; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:193; RV64IZFHMIN: # %bb.0:194; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0195; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5196; RV64IZFHMIN-NEXT: ret197;198; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16:199; RV64IZHINXMIN: # %bb.0:200; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0201; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0202; RV64IZHINXMIN-NEXT: ret203 %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")204 ret half %1205}206