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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \3; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFHMIN4; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \5; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINXMIN6 7; This file exhaustively checks half<->i32 conversions.8 9define i32 @aext_fptosi(half %a) nounwind {10; RV64IZFHMIN-LABEL: aext_fptosi:11; RV64IZFHMIN: # %bb.0:12; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa013; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz14; RV64IZFHMIN-NEXT: ret15;16; RV64IZHINXMIN-LABEL: aext_fptosi:17; RV64IZHINXMIN: # %bb.0:18; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a019; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz20; RV64IZHINXMIN-NEXT: ret21 %1 = fptosi half %a to i3222 ret i32 %123}24 25define signext i32 @sext_fptosi(half %a) nounwind {26; RV64IZFHMIN-LABEL: sext_fptosi:27; RV64IZFHMIN: # %bb.0:28; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa029; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz30; RV64IZFHMIN-NEXT: ret31;32; RV64IZHINXMIN-LABEL: sext_fptosi:33; RV64IZHINXMIN: # %bb.0:34; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a035; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz36; RV64IZHINXMIN-NEXT: ret37 %1 = fptosi half %a to i3238 ret i32 %139}40 41define zeroext i32 @zext_fptosi(half %a) nounwind {42; RV64IZFHMIN-LABEL: zext_fptosi:43; RV64IZFHMIN: # %bb.0:44; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa045; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz46; RV64IZFHMIN-NEXT: slli a0, a0, 3247; RV64IZFHMIN-NEXT: srli a0, a0, 3248; RV64IZFHMIN-NEXT: ret49;50; RV64IZHINXMIN-LABEL: zext_fptosi:51; RV64IZHINXMIN: # %bb.0:52; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a053; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz54; RV64IZHINXMIN-NEXT: slli a0, a0, 3255; RV64IZHINXMIN-NEXT: srli a0, a0, 3256; RV64IZHINXMIN-NEXT: ret57 %1 = fptosi half %a to i3258 ret i32 %159}60 61define i32 @aext_fptoui(half %a) nounwind {62; RV64IZFHMIN-LABEL: aext_fptoui:63; RV64IZFHMIN: # %bb.0:64; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa065; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz66; RV64IZFHMIN-NEXT: ret67;68; RV64IZHINXMIN-LABEL: aext_fptoui:69; RV64IZHINXMIN: # %bb.0:70; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a071; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz72; RV64IZHINXMIN-NEXT: ret73 %1 = fptoui half %a to i3274 ret i32 %175}76 77define signext i32 @sext_fptoui(half %a) nounwind {78; RV64IZFHMIN-LABEL: sext_fptoui:79; RV64IZFHMIN: # %bb.0:80; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa081; RV64IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz82; RV64IZFHMIN-NEXT: ret83;84; RV64IZHINXMIN-LABEL: sext_fptoui:85; RV64IZHINXMIN: # %bb.0:86; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a087; RV64IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz88; RV64IZHINXMIN-NEXT: ret89 %1 = fptoui half %a to i3290 ret i32 %191}92 93define zeroext i32 @zext_fptoui(half %a) nounwind {94; RV64IZFHMIN-LABEL: zext_fptoui:95; RV64IZFHMIN: # %bb.0:96; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa097; RV64IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz98; RV64IZFHMIN-NEXT: ret99;100; RV64IZHINXMIN-LABEL: zext_fptoui:101; RV64IZHINXMIN: # %bb.0:102; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0103; RV64IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz104; RV64IZHINXMIN-NEXT: ret105 %1 = fptoui half %a to i32106 ret i32 %1107}108 109define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {110; RV64IZFHMIN-LABEL: bcvt_f16_to_aext_i16:111; RV64IZFHMIN: # %bb.0:112; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1113; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0114; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5115; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5116; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5117; RV64IZFHMIN-NEXT: ret118;119; RV64IZHINXMIN-LABEL: bcvt_f16_to_aext_i16:120; RV64IZHINXMIN: # %bb.0:121; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1122; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0123; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1124; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0125; RV64IZHINXMIN-NEXT: ret126 %1 = fadd half %a, %b127 %2 = bitcast half %1 to i16128 ret i16 %2129}130 131define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {132; RV64IZFHMIN-LABEL: bcvt_f16_to_sext_i16:133; RV64IZFHMIN: # %bb.0:134; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1135; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0136; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5137; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5138; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5139; RV64IZFHMIN-NEXT: ret140;141; RV64IZHINXMIN-LABEL: bcvt_f16_to_sext_i16:142; RV64IZHINXMIN: # %bb.0:143; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1144; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0145; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1146; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0147; RV64IZHINXMIN-NEXT: slli a0, a0, 48148; RV64IZHINXMIN-NEXT: srai a0, a0, 48149; RV64IZHINXMIN-NEXT: ret150 %1 = fadd half %a, %b151 %2 = bitcast half %1 to i16152 ret i16 %2153}154 155define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {156; RV64IZFHMIN-LABEL: bcvt_f16_to_zext_i16:157; RV64IZFHMIN: # %bb.0:158; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1159; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0160; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5161; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5162; RV64IZFHMIN-NEXT: fmv.x.h a0, fa5163; RV64IZFHMIN-NEXT: slli a0, a0, 48164; RV64IZFHMIN-NEXT: srli a0, a0, 48165; RV64IZFHMIN-NEXT: ret166;167; RV64IZHINXMIN-LABEL: bcvt_f16_to_zext_i16:168; RV64IZHINXMIN: # %bb.0:169; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1170; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0171; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1172; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0173; RV64IZHINXMIN-NEXT: slli a0, a0, 48174; RV64IZHINXMIN-NEXT: srli a0, a0, 48175; RV64IZHINXMIN-NEXT: ret176 %1 = fadd half %a, %b177 %2 = bitcast half %1 to i16178 ret i16 %2179}180 181define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {182; RV64IZFHMIN-LABEL: bcvt_i64_to_f16_via_i16:183; RV64IZFHMIN: # %bb.0:184; RV64IZFHMIN-NEXT: fmv.h.x fa5, a0185; RV64IZFHMIN-NEXT: fmv.h.x fa4, a1186; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4187; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5188; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4189; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5190; RV64IZFHMIN-NEXT: ret191;192; RV64IZHINXMIN-LABEL: bcvt_i64_to_f16_via_i16:193; RV64IZHINXMIN: # %bb.0:194; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1195; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0196; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1197; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0198; RV64IZHINXMIN-NEXT: ret199 %1 = trunc i64 %a to i16200 %2 = trunc i64 %b to i16201 %3 = bitcast i16 %1 to half202 %4 = bitcast i16 %2 to half203 %5 = fadd half %3, %4204 ret half %5205}206 207define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {208; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:209; RV64IZFHMIN: # %bb.0:210; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0211; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5212; RV64IZFHMIN-NEXT: ret213;214; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16:215; RV64IZHINXMIN: # %bb.0:216; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0217; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0218; RV64IZHINXMIN-NEXT: ret219 %1 = uitofp i32 %a to half220 ret half %1221}222 223define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {224; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:225; RV64IZFHMIN: # %bb.0:226; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0227; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5228; RV64IZFHMIN-NEXT: ret229;230; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16:231; RV64IZHINXMIN: # %bb.0:232; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0233; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0234; RV64IZHINXMIN-NEXT: ret235 %1 = uitofp i32 %a to half236 ret half %1237}238 239define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {240; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:241; RV64IZFHMIN: # %bb.0:242; RV64IZFHMIN-NEXT: fcvt.s.wu fa5, a0243; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5244; RV64IZFHMIN-NEXT: ret245;246; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16:247; RV64IZHINXMIN: # %bb.0:248; RV64IZHINXMIN-NEXT: fcvt.s.wu a0, a0249; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0250; RV64IZHINXMIN-NEXT: ret251 %1 = uitofp i32 %a to half252 ret half %1253}254 255define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {256; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:257; RV64IZFHMIN: # %bb.0:258; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0259; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5260; RV64IZFHMIN-NEXT: ret261;262; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16:263; RV64IZHINXMIN: # %bb.0:264; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0265; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0266; RV64IZHINXMIN-NEXT: ret267 %1 = sitofp i32 %a to half268 ret half %1269}270 271define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {272; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:273; RV64IZFHMIN: # %bb.0:274; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0275; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5276; RV64IZFHMIN-NEXT: ret277;278; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16:279; RV64IZHINXMIN: # %bb.0:280; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0281; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0282; RV64IZHINXMIN-NEXT: ret283 %1 = sitofp i32 %a to half284 ret half %1285}286 287define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {288; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:289; RV64IZFHMIN: # %bb.0:290; RV64IZFHMIN-NEXT: fcvt.s.w fa5, a0291; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5292; RV64IZFHMIN-NEXT: ret293;294; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16:295; RV64IZHINXMIN: # %bb.0:296; RV64IZHINXMIN-NEXT: fcvt.s.w a0, a0297; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0298; RV64IZHINXMIN-NEXT: ret299 %1 = sitofp i32 %a to half300 ret half %1301}302