81 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zimop -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64ZIMOP4 5define i64 @mopr0_64(i64 %a) nounwind {6; RV64ZIMOP-LABEL: mopr0_64:7; RV64ZIMOP: # %bb.0:8; RV64ZIMOP-NEXT: mop.r.0 a0, a09; RV64ZIMOP-NEXT: ret10 %tmp = call i64 @llvm.riscv.mopr.i64(i64 %a, i64 0)11 ret i64 %tmp12}13 14define i64 @mopr31_64(i64 %a) nounwind {15; RV64ZIMOP-LABEL: mopr31_64:16; RV64ZIMOP: # %bb.0:17; RV64ZIMOP-NEXT: mop.r.31 a0, a018; RV64ZIMOP-NEXT: ret19 %tmp = call i64 @llvm.riscv.mopr.i64(i64 %a, i64 31)20 ret i64 %tmp21}22 23define i64 @moprr0_64(i64 %a, i64 %b) nounwind {24; RV64ZIMOP-LABEL: moprr0_64:25; RV64ZIMOP: # %bb.0:26; RV64ZIMOP-NEXT: mop.rr.0 a0, a0, a127; RV64ZIMOP-NEXT: ret28 %tmp = call i64 @llvm.riscv.moprr.i64(i64 %a, i64 %b, i64 0)29 ret i64 %tmp30}31 32define i64 @moprr7_64(i64 %a, i64 %b) nounwind {33; RV64ZIMOP-LABEL: moprr7_64:34; RV64ZIMOP: # %bb.0:35; RV64ZIMOP-NEXT: mop.rr.7 a0, a0, a136; RV64ZIMOP-NEXT: ret37 %tmp = call i64 @llvm.riscv.moprr.i64(i64 %a, i64 %b, i64 7)38 ret i64 %tmp39}40 41define signext i32 @mopr0_32(i32 signext %a) nounwind {42; RV64ZIMOP-LABEL: mopr0_32:43; RV64ZIMOP: # %bb.0:44; RV64ZIMOP-NEXT: mop.r.0 a0, a045; RV64ZIMOP-NEXT: sext.w a0, a046; RV64ZIMOP-NEXT: ret47 %tmp = call i32 @llvm.riscv.mopr.i32(i32 %a, i32 0)48 ret i32 %tmp49}50 51define signext i32 @mopr31_32(i32 signext %a) nounwind {52; RV64ZIMOP-LABEL: mopr31_32:53; RV64ZIMOP: # %bb.0:54; RV64ZIMOP-NEXT: mop.r.31 a0, a055; RV64ZIMOP-NEXT: sext.w a0, a056; RV64ZIMOP-NEXT: ret57 %tmp = call i32 @llvm.riscv.mopr.i32(i32 %a, i32 31)58 ret i32 %tmp59}60 61define signext i32 @moprr0_32(i32 signext %a, i32 signext %b) nounwind {62; RV64ZIMOP-LABEL: moprr0_32:63; RV64ZIMOP: # %bb.0:64; RV64ZIMOP-NEXT: mop.rr.0 a0, a0, a165; RV64ZIMOP-NEXT: sext.w a0, a066; RV64ZIMOP-NEXT: ret67 %tmp = call i32 @llvm.riscv.moprr.i32(i32 %a, i32 %b, i32 0)68 ret i32 %tmp69}70 71define signext i32 @moprr7_32(i32 signext %a, i32 signext %b) nounwind {72; RV64ZIMOP-LABEL: moprr7_32:73; RV64ZIMOP: # %bb.0:74; RV64ZIMOP-NEXT: mop.rr.7 a0, a0, a175; RV64ZIMOP-NEXT: sext.w a0, a076; RV64ZIMOP-NEXT: ret77 %tmp = call i32 @llvm.riscv.moprr.i32(i32 %a, i32 %b, i32 7)78 ret i32 %tmp79}80 81