334 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5;6; SABD7;8 9define <vscale x 16 x i8> @sabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {10; CHECK-LABEL: sabd_b:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma13; CHECK-NEXT: vmin.vv v12, v8, v1014; CHECK-NEXT: vmax.vv v8, v8, v1015; CHECK-NEXT: vsub.vv v8, v8, v1216; CHECK-NEXT: ret17 %a.sext = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>18 %b.sext = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>19 %sub = sub <vscale x 16 x i16> %a.sext, %b.sext20 %abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)21 %trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>22 ret <vscale x 16 x i8> %trunc23}24 25define <vscale x 16 x i8> @sabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {26; CHECK-LABEL: sabd_b_promoted_ops:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma29; CHECK-NEXT: vmxor.mm v0, v0, v830; CHECK-NEXT: vmv.v.i v8, 031; CHECK-NEXT: vmerge.vim v8, v8, 1, v032; CHECK-NEXT: ret33 %a.sext = sext <vscale x 16 x i1> %a to <vscale x 16 x i8>34 %b.sext = sext <vscale x 16 x i1> %b to <vscale x 16 x i8>35 %sub = sub <vscale x 16 x i8> %a.sext, %b.sext36 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)37 ret <vscale x 16 x i8> %abs38}39 40define <vscale x 8 x i16> @sabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {41; CHECK-LABEL: sabd_h:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma44; CHECK-NEXT: vmin.vv v12, v8, v1045; CHECK-NEXT: vmax.vv v8, v8, v1046; CHECK-NEXT: vsub.vv v8, v8, v1247; CHECK-NEXT: ret48 %a.sext = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>49 %b.sext = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>50 %sub = sub <vscale x 8 x i32> %a.sext, %b.sext51 %abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)52 %trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>53 ret <vscale x 8 x i16> %trunc54}55 56define <vscale x 8 x i16> @sabd_h_promoted_ops(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {57; CHECK-LABEL: sabd_h_promoted_ops:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma60; CHECK-NEXT: vmin.vv v10, v8, v961; CHECK-NEXT: vmax.vv v8, v8, v962; CHECK-NEXT: vsub.vv v10, v8, v1063; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma64; CHECK-NEXT: vzext.vf2 v8, v1065; CHECK-NEXT: ret66 %a.sext = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>67 %b.sext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>68 %sub = sub <vscale x 8 x i16> %a.sext, %b.sext69 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)70 ret <vscale x 8 x i16> %abs71}72 73define <vscale x 4 x i32> @sabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {74; CHECK-LABEL: sabd_s:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma77; CHECK-NEXT: vmin.vv v12, v8, v1078; CHECK-NEXT: vmax.vv v8, v8, v1079; CHECK-NEXT: vsub.vv v8, v8, v1280; CHECK-NEXT: ret81 %a.sext = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>82 %b.sext = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>83 %sub = sub <vscale x 4 x i64> %a.sext, %b.sext84 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)85 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>86 ret <vscale x 4 x i32> %trunc87}88 89define <vscale x 4 x i32> @sabd_s_promoted_ops(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {90; CHECK-LABEL: sabd_s_promoted_ops:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma93; CHECK-NEXT: vmin.vv v10, v8, v994; CHECK-NEXT: vmax.vv v8, v8, v995; CHECK-NEXT: vsub.vv v10, v8, v1096; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma97; CHECK-NEXT: vzext.vf2 v8, v1098; CHECK-NEXT: ret99 %a.sext = sext <vscale x 4 x i16> %a to <vscale x 4 x i32>100 %b.sext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>101 %sub = sub <vscale x 4 x i32> %a.sext, %b.sext102 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)103 ret <vscale x 4 x i32> %abs104}105 106define <vscale x 2 x i64> @sabd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {107; CHECK-LABEL: sabd_d:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma110; CHECK-NEXT: vmin.vv v12, v8, v10111; CHECK-NEXT: vmax.vv v8, v8, v10112; CHECK-NEXT: vsub.vv v8, v8, v12113; CHECK-NEXT: ret114 %a.sext = sext <vscale x 2 x i64> %a to <vscale x 2 x i128>115 %b.sext = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>116 %sub = sub <vscale x 2 x i128> %a.sext, %b.sext117 %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)118 %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>119 ret <vscale x 2 x i64> %trunc120}121 122define <vscale x 2 x i64> @sabd_d_promoted_ops(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {123; CHECK-LABEL: sabd_d_promoted_ops:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma126; CHECK-NEXT: vmin.vv v10, v8, v9127; CHECK-NEXT: vmax.vv v8, v8, v9128; CHECK-NEXT: vsub.vv v10, v8, v10129; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma130; CHECK-NEXT: vzext.vf2 v8, v10131; CHECK-NEXT: ret132 %a.sext = sext <vscale x 2 x i32> %a to <vscale x 2 x i64>133 %b.sext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>134 %sub = sub <vscale x 2 x i64> %a.sext, %b.sext135 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)136 ret <vscale x 2 x i64> %abs137}138 139;140; UABD141;142 143define <vscale x 16 x i8> @uabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {144; CHECK-LABEL: uabd_b:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma147; CHECK-NEXT: vminu.vv v12, v8, v10148; CHECK-NEXT: vmaxu.vv v8, v8, v10149; CHECK-NEXT: vsub.vv v8, v8, v12150; CHECK-NEXT: ret151 %a.zext = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>152 %b.zext = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>153 %sub = sub <vscale x 16 x i16> %a.zext, %b.zext154 %abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)155 %trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>156 ret <vscale x 16 x i8> %trunc157}158 159define <vscale x 16 x i8> @uabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {160; CHECK-LABEL: uabd_b_promoted_ops:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma163; CHECK-NEXT: vmxor.mm v0, v0, v8164; CHECK-NEXT: vmv.v.i v8, 0165; CHECK-NEXT: vmerge.vim v8, v8, 1, v0166; CHECK-NEXT: ret167 %a.zext = zext <vscale x 16 x i1> %a to <vscale x 16 x i8>168 %b.zext = zext <vscale x 16 x i1> %b to <vscale x 16 x i8>169 %sub = sub <vscale x 16 x i8> %a.zext, %b.zext170 %abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)171 ret <vscale x 16 x i8> %abs172}173 174define <vscale x 8 x i16> @uabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {175; CHECK-LABEL: uabd_h:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma178; CHECK-NEXT: vminu.vv v12, v8, v10179; CHECK-NEXT: vmaxu.vv v8, v8, v10180; CHECK-NEXT: vsub.vv v8, v8, v12181; CHECK-NEXT: ret182 %a.zext = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>183 %b.zext = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>184 %sub = sub <vscale x 8 x i32> %a.zext, %b.zext185 %abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)186 %trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>187 ret <vscale x 8 x i16> %trunc188}189 190define <vscale x 8 x i16> @uabd_h_promoted_ops(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {191; CHECK-LABEL: uabd_h_promoted_ops:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma194; CHECK-NEXT: vminu.vv v10, v8, v9195; CHECK-NEXT: vmaxu.vv v8, v8, v9196; CHECK-NEXT: vsub.vv v10, v8, v10197; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma198; CHECK-NEXT: vzext.vf2 v8, v10199; CHECK-NEXT: ret200 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>201 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>202 %sub = sub <vscale x 8 x i16> %a.zext, %b.zext203 %abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)204 ret <vscale x 8 x i16> %abs205}206 207define <vscale x 4 x i32> @uabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {208; CHECK-LABEL: uabd_s:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma211; CHECK-NEXT: vminu.vv v12, v8, v10212; CHECK-NEXT: vmaxu.vv v8, v8, v10213; CHECK-NEXT: vsub.vv v8, v8, v12214; CHECK-NEXT: ret215 %a.zext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>216 %b.zext = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>217 %sub = sub <vscale x 4 x i64> %a.zext, %b.zext218 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)219 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>220 ret <vscale x 4 x i32> %trunc221}222 223define <vscale x 4 x i32> @uabd_s_promoted_ops(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {224; CHECK-LABEL: uabd_s_promoted_ops:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma227; CHECK-NEXT: vminu.vv v10, v8, v9228; CHECK-NEXT: vmaxu.vv v8, v8, v9229; CHECK-NEXT: vsub.vv v10, v8, v10230; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma231; CHECK-NEXT: vzext.vf2 v8, v10232; CHECK-NEXT: ret233 %a.zext = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>234 %b.zext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>235 %sub = sub <vscale x 4 x i32> %a.zext, %b.zext236 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)237 ret <vscale x 4 x i32> %abs238}239 240define <vscale x 2 x i64> @uabd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {241; CHECK-LABEL: uabd_d:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma244; CHECK-NEXT: vminu.vv v12, v8, v10245; CHECK-NEXT: vmaxu.vv v8, v8, v10246; CHECK-NEXT: vsub.vv v8, v8, v12247; CHECK-NEXT: ret248 %a.zext = zext <vscale x 2 x i64> %a to <vscale x 2 x i128>249 %b.zext = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>250 %sub = sub <vscale x 2 x i128> %a.zext, %b.zext251 %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)252 %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>253 ret <vscale x 2 x i64> %trunc254}255 256define <vscale x 2 x i64> @uabd_d_promoted_ops(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {257; CHECK-LABEL: uabd_d_promoted_ops:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma260; CHECK-NEXT: vminu.vv v10, v8, v9261; CHECK-NEXT: vmaxu.vv v8, v8, v9262; CHECK-NEXT: vsub.vv v10, v8, v10263; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma264; CHECK-NEXT: vzext.vf2 v8, v10265; CHECK-NEXT: ret266 %a.zext = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>267 %b.zext = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>268 %sub = sub <vscale x 2 x i64> %a.zext, %b.zext269 %abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)270 ret <vscale x 2 x i64> %abs271}272 273; Test the situation where isLegal(ISD::ABD, typeof(%a)) returns true but %a and274; %b have differing types.275define <vscale x 4 x i32> @uabd_non_matching_extension(<vscale x 4 x i32> %a, <vscale x 4 x i8> %b) {276; CHECK-LABEL: uabd_non_matching_extension:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma279; CHECK-NEXT: vzext.vf4 v12, v10280; CHECK-NEXT: vminu.vv v10, v8, v12281; CHECK-NEXT: vmaxu.vv v8, v8, v12282; CHECK-NEXT: vsub.vv v8, v8, v10283; CHECK-NEXT: ret284 %a.zext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>285 %b.zext = zext <vscale x 4 x i8> %b to <vscale x 4 x i64>286 %sub = sub <vscale x 4 x i64> %a.zext, %b.zext287 %abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)288 %trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>289 ret <vscale x 4 x i32> %trunc290}291 292; Test the situation where isLegal(ISD::ABD, typeof(%a.zext)) returns true but293; %a and %b have differing types.294define <vscale x 4 x i32> @uabd_non_matching_promoted_ops(<vscale x 4 x i8> %a, <vscale x 4 x i16> %b) {295; CHECK-LABEL: uabd_non_matching_promoted_ops:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma298; CHECK-NEXT: vzext.vf2 v10, v8299; CHECK-NEXT: vminu.vv v8, v10, v9300; CHECK-NEXT: vmaxu.vv v9, v10, v9301; CHECK-NEXT: vsub.vv v10, v9, v8302; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma303; CHECK-NEXT: vzext.vf2 v8, v10304; CHECK-NEXT: ret305 %a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>306 %b.zext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>307 %sub = sub <vscale x 4 x i32> %a.zext, %b.zext308 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)309 ret <vscale x 4 x i32> %abs310}311 312; Test the situation where isLegal(ISD::ABD, typeof(%a)) returns true but %a and313; %b are promoted differently.314define <vscale x 4 x i32> @uabd_non_matching_promotion(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {315; CHECK-LABEL: uabd_non_matching_promotion:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma318; CHECK-NEXT: vzext.vf4 v10, v8319; CHECK-NEXT: vsext.vf4 v12, v9320; CHECK-NEXT: vmin.vv v8, v10, v12321; CHECK-NEXT: vmax.vv v10, v10, v12322; CHECK-NEXT: vsub.vv v8, v10, v8323; CHECK-NEXT: ret324 %a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>325 %b.zext = sext <vscale x 4 x i8> %b to <vscale x 4 x i32>326 %sub = sub <vscale x 4 x i32> %a.zext, %b.zext327 %abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)328 ret <vscale x 4 x i32> %abs329}330 331;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:332; RV32: {{.*}}333; RV64: {{.*}}334