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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i16> @vabs_nxv1i16(<vscale x 1 x i16> %v) {6; CHECK-LABEL: vabs_nxv1i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma9; CHECK-NEXT: vrsub.vi v9, v8, 010; CHECK-NEXT: vmax.vv v8, v8, v911; CHECK-NEXT: ret12 %r = call <vscale x 1 x i16> @llvm.abs.nxv1i16(<vscale x 1 x i16> %v, i1 false)13 ret <vscale x 1 x i16> %r14}15 16define <vscale x 2 x i16> @vabs_nxv2i16(<vscale x 2 x i16> %v) {17; CHECK-LABEL: vabs_nxv2i16:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma20; CHECK-NEXT: vrsub.vi v9, v8, 021; CHECK-NEXT: vmax.vv v8, v8, v922; CHECK-NEXT: ret23 %r = call <vscale x 2 x i16> @llvm.abs.nxv2i16(<vscale x 2 x i16> %v, i1 false)24 ret <vscale x 2 x i16> %r25}26 27define <vscale x 4 x i16> @vabs_nxv4i16(<vscale x 4 x i16> %v) {28; CHECK-LABEL: vabs_nxv4i16:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma31; CHECK-NEXT: vrsub.vi v9, v8, 032; CHECK-NEXT: vmax.vv v8, v8, v933; CHECK-NEXT: ret34 %r = call <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16> %v, i1 false)35 ret <vscale x 4 x i16> %r36}37 38define <vscale x 8 x i16> @vabs_nxv8i16(<vscale x 8 x i16> %v) {39; CHECK-LABEL: vabs_nxv8i16:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma42; CHECK-NEXT: vrsub.vi v10, v8, 043; CHECK-NEXT: vmax.vv v8, v8, v1044; CHECK-NEXT: ret45 %r = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %v, i1 false)46 ret <vscale x 8 x i16> %r47}48 49define <vscale x 16 x i16> @vabs_nxv16i16(<vscale x 16 x i16> %v) {50; CHECK-LABEL: vabs_nxv16i16:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma53; CHECK-NEXT: vrsub.vi v12, v8, 054; CHECK-NEXT: vmax.vv v8, v8, v1255; CHECK-NEXT: ret56 %r = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %v, i1 false)57 ret <vscale x 16 x i16> %r58}59 60define <vscale x 32 x i16> @vabs_nxv32i16(<vscale x 32 x i16> %v) {61; CHECK-LABEL: vabs_nxv32i16:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma64; CHECK-NEXT: vrsub.vi v16, v8, 065; CHECK-NEXT: vmax.vv v8, v8, v1666; CHECK-NEXT: ret67 %r = call <vscale x 32 x i16> @llvm.abs.nxv32i16(<vscale x 32 x i16> %v, i1 false)68 ret <vscale x 32 x i16> %r69}70 71define <vscale x 1 x i32> @vabs_nxv1i32(<vscale x 1 x i32> %v) {72; CHECK-LABEL: vabs_nxv1i32:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma75; CHECK-NEXT: vrsub.vi v9, v8, 076; CHECK-NEXT: vmax.vv v8, v8, v977; CHECK-NEXT: ret78 %r = call <vscale x 1 x i32> @llvm.abs.nxv1i32(<vscale x 1 x i32> %v, i1 false)79 ret <vscale x 1 x i32> %r80}81 82define <vscale x 2 x i32> @vabs_nxv2i32(<vscale x 2 x i32> %v) {83; CHECK-LABEL: vabs_nxv2i32:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma86; CHECK-NEXT: vrsub.vi v9, v8, 087; CHECK-NEXT: vmax.vv v8, v8, v988; CHECK-NEXT: ret89 %r = call <vscale x 2 x i32> @llvm.abs.nxv2i32(<vscale x 2 x i32> %v, i1 false)90 ret <vscale x 2 x i32> %r91}92 93define <vscale x 4 x i32> @vabs_nxv4i32(<vscale x 4 x i32> %v) {94; CHECK-LABEL: vabs_nxv4i32:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma97; CHECK-NEXT: vrsub.vi v10, v8, 098; CHECK-NEXT: vmax.vv v8, v8, v1099; CHECK-NEXT: ret100 %r = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %v, i1 false)101 ret <vscale x 4 x i32> %r102}103 104define <vscale x 8 x i32> @vabs_nxv8i32(<vscale x 8 x i32> %v) {105; CHECK-LABEL: vabs_nxv8i32:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma108; CHECK-NEXT: vrsub.vi v12, v8, 0109; CHECK-NEXT: vmax.vv v8, v8, v12110; CHECK-NEXT: ret111 %r = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %v, i1 false)112 ret <vscale x 8 x i32> %r113}114 115define <vscale x 16 x i32> @vabs_nxv16i32(<vscale x 16 x i32> %v) {116; CHECK-LABEL: vabs_nxv16i32:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma119; CHECK-NEXT: vrsub.vi v16, v8, 0120; CHECK-NEXT: vmax.vv v8, v8, v16121; CHECK-NEXT: ret122 %r = call <vscale x 16 x i32> @llvm.abs.nxv16i32(<vscale x 16 x i32> %v, i1 false)123 ret <vscale x 16 x i32> %r124}125 126define <vscale x 1 x i64> @vabs_nxv1i64(<vscale x 1 x i64> %v) {127; CHECK-LABEL: vabs_nxv1i64:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma130; CHECK-NEXT: vrsub.vi v9, v8, 0131; CHECK-NEXT: vmax.vv v8, v8, v9132; CHECK-NEXT: ret133 %r = call <vscale x 1 x i64> @llvm.abs.nxv1i64(<vscale x 1 x i64> %v, i1 false)134 ret <vscale x 1 x i64> %r135}136 137define <vscale x 2 x i64> @vabs_nxv2i64(<vscale x 2 x i64> %v) {138; CHECK-LABEL: vabs_nxv2i64:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma141; CHECK-NEXT: vrsub.vi v10, v8, 0142; CHECK-NEXT: vmax.vv v8, v8, v10143; CHECK-NEXT: ret144 %r = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %v, i1 false)145 ret <vscale x 2 x i64> %r146}147 148define <vscale x 4 x i64> @vabs_nxv4i64(<vscale x 4 x i64> %v) {149; CHECK-LABEL: vabs_nxv4i64:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma152; CHECK-NEXT: vrsub.vi v12, v8, 0153; CHECK-NEXT: vmax.vv v8, v8, v12154; CHECK-NEXT: ret155 %r = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %v, i1 false)156 ret <vscale x 4 x i64> %r157}158 159define <vscale x 8 x i64> @vabs_nxv8i64(<vscale x 8 x i64> %v) {160; CHECK-LABEL: vabs_nxv8i64:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma163; CHECK-NEXT: vrsub.vi v16, v8, 0164; CHECK-NEXT: vmax.vv v8, v8, v16165; CHECK-NEXT: ret166 %r = call <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64> %v, i1 false)167 ret <vscale x 8 x i64> %r168}169