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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK4; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i8> @vp_abs_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vp_abs_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t12; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t13; CHECK-NEXT: ret14 %v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)15 ret <vscale x 1 x i8> %v16}17 18define <vscale x 1 x i8> @vp_abs_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {19; CHECK-LABEL: vp_abs_nxv1i8_unmasked:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma22; CHECK-NEXT: vrsub.vi v9, v8, 023; CHECK-NEXT: vmax.vv v8, v8, v924; CHECK-NEXT: ret25 %v = call <vscale x 1 x i8> @llvm.vp.abs.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)26 ret <vscale x 1 x i8> %v27}28 29define <vscale x 2 x i8> @vp_abs_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {30; CHECK-LABEL: vp_abs_nxv2i8:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma33; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t34; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t35; CHECK-NEXT: ret36 %v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)37 ret <vscale x 2 x i8> %v38}39 40define <vscale x 2 x i8> @vp_abs_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {41; CHECK-LABEL: vp_abs_nxv2i8_unmasked:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT: vrsub.vi v9, v8, 045; CHECK-NEXT: vmax.vv v8, v8, v946; CHECK-NEXT: ret47 %v = call <vscale x 2 x i8> @llvm.vp.abs.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)48 ret <vscale x 2 x i8> %v49}50 51define <vscale x 4 x i8> @vp_abs_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vp_abs_nxv4i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma55; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t56; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t57; CHECK-NEXT: ret58 %v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)59 ret <vscale x 4 x i8> %v60}61 62define <vscale x 4 x i8> @vp_abs_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {63; CHECK-LABEL: vp_abs_nxv4i8_unmasked:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma66; CHECK-NEXT: vrsub.vi v9, v8, 067; CHECK-NEXT: vmax.vv v8, v8, v968; CHECK-NEXT: ret69 %v = call <vscale x 4 x i8> @llvm.vp.abs.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)70 ret <vscale x 4 x i8> %v71}72 73define <vscale x 8 x i8> @vp_abs_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {74; CHECK-LABEL: vp_abs_nxv8i8:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma77; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t78; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t79; CHECK-NEXT: ret80 %v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)81 ret <vscale x 8 x i8> %v82}83 84define <vscale x 8 x i8> @vp_abs_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {85; CHECK-LABEL: vp_abs_nxv8i8_unmasked:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma88; CHECK-NEXT: vrsub.vi v9, v8, 089; CHECK-NEXT: vmax.vv v8, v8, v990; CHECK-NEXT: ret91 %v = call <vscale x 8 x i8> @llvm.vp.abs.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)92 ret <vscale x 8 x i8> %v93}94 95define <vscale x 16 x i8> @vp_abs_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {96; CHECK-LABEL: vp_abs_nxv16i8:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma99; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t100; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t101; CHECK-NEXT: ret102 %v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)103 ret <vscale x 16 x i8> %v104}105 106define <vscale x 16 x i8> @vp_abs_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {107; CHECK-LABEL: vp_abs_nxv16i8_unmasked:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma110; CHECK-NEXT: vrsub.vi v10, v8, 0111; CHECK-NEXT: vmax.vv v8, v8, v10112; CHECK-NEXT: ret113 %v = call <vscale x 16 x i8> @llvm.vp.abs.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)114 ret <vscale x 16 x i8> %v115}116 117define <vscale x 32 x i8> @vp_abs_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: vp_abs_nxv32i8:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma121; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t122; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t123; CHECK-NEXT: ret124 %v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)125 ret <vscale x 32 x i8> %v126}127 128define <vscale x 32 x i8> @vp_abs_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {129; CHECK-LABEL: vp_abs_nxv32i8_unmasked:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma132; CHECK-NEXT: vrsub.vi v12, v8, 0133; CHECK-NEXT: vmax.vv v8, v8, v12134; CHECK-NEXT: ret135 %v = call <vscale x 32 x i8> @llvm.vp.abs.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)136 ret <vscale x 32 x i8> %v137}138 139define <vscale x 64 x i8> @vp_abs_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vp_abs_nxv64i8:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma143; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t144; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t145; CHECK-NEXT: ret146 %v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)147 ret <vscale x 64 x i8> %v148}149 150define <vscale x 64 x i8> @vp_abs_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {151; CHECK-LABEL: vp_abs_nxv64i8_unmasked:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma154; CHECK-NEXT: vrsub.vi v16, v8, 0155; CHECK-NEXT: vmax.vv v8, v8, v16156; CHECK-NEXT: ret157 %v = call <vscale x 64 x i8> @llvm.vp.abs.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> splat (i1 true), i32 %evl)158 ret <vscale x 64 x i8> %v159}160 161define <vscale x 1 x i16> @vp_abs_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: vp_abs_nxv1i16:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma165; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t166; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t167; CHECK-NEXT: ret168 %v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)169 ret <vscale x 1 x i16> %v170}171 172define <vscale x 1 x i16> @vp_abs_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {173; CHECK-LABEL: vp_abs_nxv1i16_unmasked:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma176; CHECK-NEXT: vrsub.vi v9, v8, 0177; CHECK-NEXT: vmax.vv v8, v8, v9178; CHECK-NEXT: ret179 %v = call <vscale x 1 x i16> @llvm.vp.abs.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)180 ret <vscale x 1 x i16> %v181}182 183define <vscale x 2 x i16> @vp_abs_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {184; CHECK-LABEL: vp_abs_nxv2i16:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma187; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t188; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t189; CHECK-NEXT: ret190 %v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)191 ret <vscale x 2 x i16> %v192}193 194define <vscale x 2 x i16> @vp_abs_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {195; CHECK-LABEL: vp_abs_nxv2i16_unmasked:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma198; CHECK-NEXT: vrsub.vi v9, v8, 0199; CHECK-NEXT: vmax.vv v8, v8, v9200; CHECK-NEXT: ret201 %v = call <vscale x 2 x i16> @llvm.vp.abs.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)202 ret <vscale x 2 x i16> %v203}204 205define <vscale x 4 x i16> @vp_abs_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {206; CHECK-LABEL: vp_abs_nxv4i16:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma209; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t210; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t211; CHECK-NEXT: ret212 %v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)213 ret <vscale x 4 x i16> %v214}215 216define <vscale x 4 x i16> @vp_abs_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {217; CHECK-LABEL: vp_abs_nxv4i16_unmasked:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma220; CHECK-NEXT: vrsub.vi v9, v8, 0221; CHECK-NEXT: vmax.vv v8, v8, v9222; CHECK-NEXT: ret223 %v = call <vscale x 4 x i16> @llvm.vp.abs.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)224 ret <vscale x 4 x i16> %v225}226 227define <vscale x 8 x i16> @vp_abs_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vp_abs_nxv8i16:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma231; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t232; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t233; CHECK-NEXT: ret234 %v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)235 ret <vscale x 8 x i16> %v236}237 238define <vscale x 8 x i16> @vp_abs_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {239; CHECK-LABEL: vp_abs_nxv8i16_unmasked:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma242; CHECK-NEXT: vrsub.vi v10, v8, 0243; CHECK-NEXT: vmax.vv v8, v8, v10244; CHECK-NEXT: ret245 %v = call <vscale x 8 x i16> @llvm.vp.abs.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)246 ret <vscale x 8 x i16> %v247}248 249define <vscale x 16 x i16> @vp_abs_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {250; CHECK-LABEL: vp_abs_nxv16i16:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma253; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t254; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t255; CHECK-NEXT: ret256 %v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)257 ret <vscale x 16 x i16> %v258}259 260define <vscale x 16 x i16> @vp_abs_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {261; CHECK-LABEL: vp_abs_nxv16i16_unmasked:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma264; CHECK-NEXT: vrsub.vi v12, v8, 0265; CHECK-NEXT: vmax.vv v8, v8, v12266; CHECK-NEXT: ret267 %v = call <vscale x 16 x i16> @llvm.vp.abs.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)268 ret <vscale x 16 x i16> %v269}270 271define <vscale x 32 x i16> @vp_abs_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vp_abs_nxv32i16:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma275; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t276; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t277; CHECK-NEXT: ret278 %v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)279 ret <vscale x 32 x i16> %v280}281 282define <vscale x 32 x i16> @vp_abs_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {283; CHECK-LABEL: vp_abs_nxv32i16_unmasked:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma286; CHECK-NEXT: vrsub.vi v16, v8, 0287; CHECK-NEXT: vmax.vv v8, v8, v16288; CHECK-NEXT: ret289 %v = call <vscale x 32 x i16> @llvm.vp.abs.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)290 ret <vscale x 32 x i16> %v291}292 293define <vscale x 1 x i32> @vp_abs_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: vp_abs_nxv1i32:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma297; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t298; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t299; CHECK-NEXT: ret300 %v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)301 ret <vscale x 1 x i32> %v302}303 304define <vscale x 1 x i32> @vp_abs_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {305; CHECK-LABEL: vp_abs_nxv1i32_unmasked:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma308; CHECK-NEXT: vrsub.vi v9, v8, 0309; CHECK-NEXT: vmax.vv v8, v8, v9310; CHECK-NEXT: ret311 %v = call <vscale x 1 x i32> @llvm.vp.abs.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)312 ret <vscale x 1 x i32> %v313}314 315define <vscale x 2 x i32> @vp_abs_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {316; CHECK-LABEL: vp_abs_nxv2i32:317; CHECK: # %bb.0:318; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma319; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t320; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t321; CHECK-NEXT: ret322 %v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)323 ret <vscale x 2 x i32> %v324}325 326define <vscale x 2 x i32> @vp_abs_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {327; CHECK-LABEL: vp_abs_nxv2i32_unmasked:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma330; CHECK-NEXT: vrsub.vi v9, v8, 0331; CHECK-NEXT: vmax.vv v8, v8, v9332; CHECK-NEXT: ret333 %v = call <vscale x 2 x i32> @llvm.vp.abs.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)334 ret <vscale x 2 x i32> %v335}336 337define <vscale x 4 x i32> @vp_abs_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {338; CHECK-LABEL: vp_abs_nxv4i32:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma341; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t342; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t343; CHECK-NEXT: ret344 %v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)345 ret <vscale x 4 x i32> %v346}347 348define <vscale x 4 x i32> @vp_abs_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {349; CHECK-LABEL: vp_abs_nxv4i32_unmasked:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma352; CHECK-NEXT: vrsub.vi v10, v8, 0353; CHECK-NEXT: vmax.vv v8, v8, v10354; CHECK-NEXT: ret355 %v = call <vscale x 4 x i32> @llvm.vp.abs.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)356 ret <vscale x 4 x i32> %v357}358 359define <vscale x 8 x i32> @vp_abs_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: vp_abs_nxv8i32:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma363; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t364; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t365; CHECK-NEXT: ret366 %v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)367 ret <vscale x 8 x i32> %v368}369 370define <vscale x 8 x i32> @vp_abs_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {371; CHECK-LABEL: vp_abs_nxv8i32_unmasked:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma374; CHECK-NEXT: vrsub.vi v12, v8, 0375; CHECK-NEXT: vmax.vv v8, v8, v12376; CHECK-NEXT: ret377 %v = call <vscale x 8 x i32> @llvm.vp.abs.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)378 ret <vscale x 8 x i32> %v379}380 381define <vscale x 16 x i32> @vp_abs_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {382; CHECK-LABEL: vp_abs_nxv16i32:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma385; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t386; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t387; CHECK-NEXT: ret388 %v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)389 ret <vscale x 16 x i32> %v390}391 392define <vscale x 16 x i32> @vp_abs_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {393; CHECK-LABEL: vp_abs_nxv16i32_unmasked:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma396; CHECK-NEXT: vrsub.vi v16, v8, 0397; CHECK-NEXT: vmax.vv v8, v8, v16398; CHECK-NEXT: ret399 %v = call <vscale x 16 x i32> @llvm.vp.abs.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)400 ret <vscale x 16 x i32> %v401}402 403define <vscale x 1 x i64> @vp_abs_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {404; CHECK-LABEL: vp_abs_nxv1i64:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma407; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t408; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t409; CHECK-NEXT: ret410 %v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)411 ret <vscale x 1 x i64> %v412}413 414define <vscale x 1 x i64> @vp_abs_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {415; CHECK-LABEL: vp_abs_nxv1i64_unmasked:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma418; CHECK-NEXT: vrsub.vi v9, v8, 0419; CHECK-NEXT: vmax.vv v8, v8, v9420; CHECK-NEXT: ret421 %v = call <vscale x 1 x i64> @llvm.vp.abs.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)422 ret <vscale x 1 x i64> %v423}424 425define <vscale x 2 x i64> @vp_abs_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {426; CHECK-LABEL: vp_abs_nxv2i64:427; CHECK: # %bb.0:428; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma429; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t430; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t431; CHECK-NEXT: ret432 %v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)433 ret <vscale x 2 x i64> %v434}435 436define <vscale x 2 x i64> @vp_abs_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {437; CHECK-LABEL: vp_abs_nxv2i64_unmasked:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma440; CHECK-NEXT: vrsub.vi v10, v8, 0441; CHECK-NEXT: vmax.vv v8, v8, v10442; CHECK-NEXT: ret443 %v = call <vscale x 2 x i64> @llvm.vp.abs.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)444 ret <vscale x 2 x i64> %v445}446 447define <vscale x 4 x i64> @vp_abs_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {448; CHECK-LABEL: vp_abs_nxv4i64:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma451; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t452; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t453; CHECK-NEXT: ret454 %v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)455 ret <vscale x 4 x i64> %v456}457 458define <vscale x 4 x i64> @vp_abs_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {459; CHECK-LABEL: vp_abs_nxv4i64_unmasked:460; CHECK: # %bb.0:461; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma462; CHECK-NEXT: vrsub.vi v12, v8, 0463; CHECK-NEXT: vmax.vv v8, v8, v12464; CHECK-NEXT: ret465 %v = call <vscale x 4 x i64> @llvm.vp.abs.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)466 ret <vscale x 4 x i64> %v467}468 469define <vscale x 7 x i64> @vp_abs_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {470; CHECK-LABEL: vp_abs_nxv7i64:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma473; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t474; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t475; CHECK-NEXT: ret476 %v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)477 ret <vscale x 7 x i64> %v478}479 480define <vscale x 7 x i64> @vp_abs_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {481; CHECK-LABEL: vp_abs_nxv7i64_unmasked:482; CHECK: # %bb.0:483; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma484; CHECK-NEXT: vrsub.vi v16, v8, 0485; CHECK-NEXT: vmax.vv v8, v8, v16486; CHECK-NEXT: ret487 %v = call <vscale x 7 x i64> @llvm.vp.abs.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> splat (i1 true), i32 %evl)488 ret <vscale x 7 x i64> %v489}490 491define <vscale x 8 x i64> @vp_abs_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {492; CHECK-LABEL: vp_abs_nxv8i64:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma495; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t496; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t497; CHECK-NEXT: ret498 %v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)499 ret <vscale x 8 x i64> %v500}501 502define <vscale x 8 x i64> @vp_abs_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {503; CHECK-LABEL: vp_abs_nxv8i64_unmasked:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma506; CHECK-NEXT: vrsub.vi v16, v8, 0507; CHECK-NEXT: vmax.vv v8, v8, v16508; CHECK-NEXT: ret509 %v = call <vscale x 8 x i64> @llvm.vp.abs.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)510 ret <vscale x 8 x i64> %v511}512 513define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {514; CHECK-LABEL: vp_abs_nxv16i64:515; CHECK: # %bb.0:516; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma517; CHECK-NEXT: vmv1r.v v7, v0518; CHECK-NEXT: csrr a1, vlenb519; CHECK-NEXT: srli a2, a1, 3520; CHECK-NEXT: sub a3, a0, a1521; CHECK-NEXT: vslidedown.vx v0, v0, a2522; CHECK-NEXT: sltu a2, a0, a3523; CHECK-NEXT: addi a2, a2, -1524; CHECK-NEXT: and a2, a2, a3525; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma526; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t527; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t528; CHECK-NEXT: bltu a0, a1, .LBB46_2529; CHECK-NEXT: # %bb.1:530; CHECK-NEXT: mv a0, a1531; CHECK-NEXT: .LBB46_2:532; CHECK-NEXT: vmv1r.v v0, v7533; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma534; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t535; CHECK-NEXT: vmax.vv v8, v8, v24, v0.t536; CHECK-NEXT: ret537 %v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)538 ret <vscale x 16 x i64> %v539}540 541define <vscale x 16 x i64> @vp_abs_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {542; CHECK-LABEL: vp_abs_nxv16i64_unmasked:543; CHECK: # %bb.0:544; CHECK-NEXT: csrr a1, vlenb545; CHECK-NEXT: sub a2, a0, a1546; CHECK-NEXT: sltu a3, a0, a2547; CHECK-NEXT: addi a3, a3, -1548; CHECK-NEXT: and a2, a3, a2549; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma550; CHECK-NEXT: vrsub.vi v24, v16, 0551; CHECK-NEXT: vmax.vv v16, v16, v24552; CHECK-NEXT: bltu a0, a1, .LBB47_2553; CHECK-NEXT: # %bb.1:554; CHECK-NEXT: mv a0, a1555; CHECK-NEXT: .LBB47_2:556; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma557; CHECK-NEXT: vrsub.vi v24, v8, 0558; CHECK-NEXT: vmax.vv v8, v8, v24559; CHECK-NEXT: ret560 %v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)561 ret <vscale x 16 x i64> %v562}563