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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \3; RUN: | FileCheck %s -check-prefix=RV64IV4 5define <vscale x 1 x i64> @access_fixed_object(ptr %val) {6; RV64IV-LABEL: access_fixed_object:7; RV64IV: # %bb.0:8; RV64IV-NEXT: addi sp, sp, -5289; RV64IV-NEXT: .cfi_def_cfa_offset 52810; RV64IV-NEXT: addi a1, sp, 811; RV64IV-NEXT: vl1re64.v v8, (a1)12; RV64IV-NEXT: ld a1, 520(sp)13; RV64IV-NEXT: sd a1, 0(a0)14; RV64IV-NEXT: addi sp, sp, 52815; RV64IV-NEXT: .cfi_def_cfa_offset 016; RV64IV-NEXT: ret17 %local = alloca i6418 %array = alloca [64 x i64]19 %v = load <vscale x 1 x i64>, ptr %array20 %len = load i64, ptr %local21 store i64 %len, ptr %val22 ret <vscale x 1 x i64> %v23}24 25define <vscale x 1 x i64> @access_fixed_and_vector_objects(ptr %val) {26; RV64IV-LABEL: access_fixed_and_vector_objects:27; RV64IV: # %bb.0:28; RV64IV-NEXT: addi sp, sp, -52829; RV64IV-NEXT: .cfi_def_cfa_offset 52830; RV64IV-NEXT: csrr a0, vlenb31; RV64IV-NEXT: sub sp, sp, a032; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 1 * vlenb33; RV64IV-NEXT: addi a0, sp, 834; RV64IV-NEXT: vl1re64.v v8, (a0)35; RV64IV-NEXT: addi a0, sp, 52836; RV64IV-NEXT: vl1re64.v v9, (a0)37; RV64IV-NEXT: ld a0, 520(sp)38; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, ma39; RV64IV-NEXT: vadd.vv v8, v8, v940; RV64IV-NEXT: csrr a0, vlenb41; RV64IV-NEXT: add sp, sp, a042; RV64IV-NEXT: .cfi_def_cfa sp, 52843; RV64IV-NEXT: addi sp, sp, 52844; RV64IV-NEXT: .cfi_def_cfa_offset 045; RV64IV-NEXT: ret46 %local = alloca i6447 %vector = alloca <vscale x 1 x i64>48 %array = alloca [64 x i64]49 %v1 = load <vscale x 1 x i64>, ptr %array50 %v2 = load <vscale x 1 x i64>, ptr %vector51 %len = load i64, ptr %local52 53 %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(54 <vscale x 1 x i64> poison,55 <vscale x 1 x i64> %v1,56 <vscale x 1 x i64> %v2,57 i64 %len)58 59 ret <vscale x 1 x i64> %a60}61 62define <vscale x 1 x i64> @probe_fixed_and_vector_objects(ptr %val, <vscale x 1 x i64> %dummy) "probe-stack"="inline-asm" {63; RV64IV-LABEL: probe_fixed_and_vector_objects:64; RV64IV: # %bb.0:65; RV64IV-NEXT: addi sp, sp, -52866; RV64IV-NEXT: .cfi_def_cfa_offset 52867; RV64IV-NEXT: csrr t1, vlenb68; RV64IV-NEXT: .cfi_def_cfa t1, -869; RV64IV-NEXT: lui t2, 170; RV64IV-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=171; RV64IV-NEXT: sub sp, sp, t272; RV64IV-NEXT: sd zero, 0(sp)73; RV64IV-NEXT: sub t1, t1, t274; RV64IV-NEXT: bge t1, t2, .LBB2_175; RV64IV-NEXT: # %bb.2:76; RV64IV-NEXT: .cfi_def_cfa_register sp77; RV64IV-NEXT: sub sp, sp, t178; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 1 * vlenb79; RV64IV-NEXT: addi a0, sp, 880; RV64IV-NEXT: vl1re64.v v9, (a0)81; RV64IV-NEXT: addi a0, sp, 52882; RV64IV-NEXT: vl1re64.v v10, (a0)83; RV64IV-NEXT: ld a0, 520(sp)84; RV64IV-NEXT: vsetvli zero, a0, e64, m1, tu, ma85; RV64IV-NEXT: vadd.vv v8, v9, v1086; RV64IV-NEXT: csrr a0, vlenb87; RV64IV-NEXT: add sp, sp, a088; RV64IV-NEXT: .cfi_def_cfa sp, 52889; RV64IV-NEXT: addi sp, sp, 52890; RV64IV-NEXT: .cfi_def_cfa_offset 091; RV64IV-NEXT: ret92 %local = alloca i6493 %vector = alloca <vscale x 1 x i64>94 %array = alloca [64 x i64]95 %v1 = load <vscale x 1 x i64>, ptr %array96 %v2 = load <vscale x 1 x i64>, ptr %vector97 %len = load i64, ptr %local98 99 %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(100 <vscale x 1 x i64> %dummy,101 <vscale x 1 x i64> %v1,102 <vscale x 1 x i64> %v2,103 i64 %len)104 105 ret <vscale x 1 x i64> %a106}107