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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK3 4define <vscale x 1 x i1> @get_lane_mask(ptr %p, i64 %index, i64 %tc) {5; CHECK-LABEL: get_lane_mask:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma8; CHECK-NEXT: vid.v v89; CHECK-NEXT: vsaddu.vx v8, v8, a110; CHECK-NEXT: vmsltu.vx v0, v8, a211; CHECK-NEXT: ret12 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 %index, i64 %tc)13 ret <vscale x 1 x i1> %mask14}15 16define <vscale x 1 x i1> @constant_zero_index(ptr %p, i64 %tc) {17; CHECK-LABEL: constant_zero_index:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma20; CHECK-NEXT: vid.v v821; CHECK-NEXT: vmsltu.vx v0, v8, a122; CHECK-NEXT: ret23 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 %tc)24 ret <vscale x 1 x i1> %mask25}26 27define <vscale x 1 x i1> @constant_nonzero_index(ptr %p, i64 %tc) {28; CHECK-LABEL: constant_nonzero_index:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma31; CHECK-NEXT: vid.v v832; CHECK-NEXT: li a0, 2433; CHECK-NEXT: vsaddu.vx v8, v8, a034; CHECK-NEXT: vmsltu.vx v0, v8, a135; CHECK-NEXT: ret36 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 24, i64 %tc)37 ret <vscale x 1 x i1> %mask38}39 40define <vscale x 1 x i1> @constant_tripcount(ptr %p, i64 %index) {41; CHECK-LABEL: constant_tripcount:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma44; CHECK-NEXT: vid.v v845; CHECK-NEXT: vsaddu.vx v8, v8, a146; CHECK-NEXT: li a0, 102447; CHECK-NEXT: vmsltu.vx v0, v8, a048; CHECK-NEXT: ret49 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 %index, i64 1024)50 ret <vscale x 1 x i1> %mask51}52 53define <vscale x 1 x i1> @constant_both(ptr %p) {54; CHECK-LABEL: constant_both:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma57; CHECK-NEXT: vid.v v858; CHECK-NEXT: li a0, 102459; CHECK-NEXT: vmsltu.vx v0, v8, a060; CHECK-NEXT: ret61 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 1024)62 ret <vscale x 1 x i1> %mask63}64 65; Architectural max VLEN=64k, so result is "as-if" TC=102466define <vscale x 1 x i1> @above_maxvl(ptr %p) {67; CHECK-LABEL: above_maxvl:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma70; CHECK-NEXT: vid.v v871; CHECK-NEXT: li a0, 172; CHECK-NEXT: slli a0, a0, 1173; CHECK-NEXT: vmsltu.vx v0, v8, a074; CHECK-NEXT: ret75 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 2048)76 ret <vscale x 1 x i1> %mask77}78 79define <2 x i1> @fv2(ptr %p, i64 %index, i64 %tc) {80; CHECK-LABEL: fv2:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma83; CHECK-NEXT: vid.v v884; CHECK-NEXT: vsaddu.vx v8, v8, a185; CHECK-NEXT: vmsltu.vx v0, v8, a286; CHECK-NEXT: ret87 %mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %tc)88 ret <2 x i1> %mask89}90 91define <8 x i1> @fv8(ptr %p, i64 %index, i64 %tc) {92; CHECK-LABEL: fv8:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma95; CHECK-NEXT: vid.v v896; CHECK-NEXT: vsaddu.vx v8, v8, a197; CHECK-NEXT: vmsltu.vx v0, v8, a298; CHECK-NEXT: ret99 %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc)100 ret <8 x i1> %mask101}102 103define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {104; CHECK-LABEL: fv32:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma107; CHECK-NEXT: vid.v v8108; CHECK-NEXT: li a0, 16109; CHECK-NEXT: vadd.vx v16, v8, a0110; CHECK-NEXT: vsaddu.vx v8, v8, a1111; CHECK-NEXT: vsaddu.vx v16, v16, a1112; CHECK-NEXT: vmsltu.vx v24, v16, a2113; CHECK-NEXT: vmsltu.vx v0, v8, a2114; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma115; CHECK-NEXT: vslideup.vi v0, v24, 2116; CHECK-NEXT: ret117 %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)118 ret <32 x i1> %mask119}120 121define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {122; CHECK-LABEL: fv64:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma125; CHECK-NEXT: vid.v v8126; CHECK-NEXT: li a0, 16127; CHECK-NEXT: vsaddu.vx v16, v8, a1128; CHECK-NEXT: vmsltu.vx v0, v16, a2129; CHECK-NEXT: vadd.vx v16, v8, a0130; CHECK-NEXT: li a0, 32131; CHECK-NEXT: vsaddu.vx v16, v16, a1132; CHECK-NEXT: vmsltu.vx v24, v16, a2133; CHECK-NEXT: vadd.vx v16, v8, a0134; CHECK-NEXT: vsaddu.vx v16, v16, a1135; CHECK-NEXT: vmsltu.vx v25, v16, a2136; CHECK-NEXT: li a0, 48137; CHECK-NEXT: vadd.vx v8, v8, a0138; CHECK-NEXT: vsaddu.vx v8, v8, a1139; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma140; CHECK-NEXT: vslideup.vi v0, v24, 2141; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma142; CHECK-NEXT: vslideup.vi v0, v25, 4143; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma144; CHECK-NEXT: vmsltu.vx v16, v8, a2145; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma146; CHECK-NEXT: vslideup.vi v0, v16, 6147; CHECK-NEXT: ret148 %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc)149 ret <64 x i1> %mask150}151 152define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) {153; CHECK-LABEL: fv128:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma156; CHECK-NEXT: vid.v v8157; CHECK-NEXT: li a0, 80158; CHECK-NEXT: vsaddu.vx v16, v8, a1159; CHECK-NEXT: vmsltu.vx v0, v16, a2160; CHECK-NEXT: vadd.vx v16, v8, a0161; CHECK-NEXT: li a0, 64162; CHECK-NEXT: vsaddu.vx v16, v16, a1163; CHECK-NEXT: vmsltu.vx v24, v16, a2164; CHECK-NEXT: vadd.vx v16, v8, a0165; CHECK-NEXT: li a0, 96166; CHECK-NEXT: vsaddu.vx v16, v16, a1167; CHECK-NEXT: vmsltu.vx v25, v16, a2168; CHECK-NEXT: vadd.vx v16, v8, a0169; CHECK-NEXT: li a0, 112170; CHECK-NEXT: vsaddu.vx v16, v16, a1171; CHECK-NEXT: vmsltu.vx v26, v16, a2172; CHECK-NEXT: vadd.vx v16, v8, a0173; CHECK-NEXT: li a0, 16174; CHECK-NEXT: vsaddu.vx v16, v16, a1175; CHECK-NEXT: vmsltu.vx v27, v16, a2176; CHECK-NEXT: vadd.vx v16, v8, a0177; CHECK-NEXT: li a0, 32178; CHECK-NEXT: vsaddu.vx v16, v16, a1179; CHECK-NEXT: vmsltu.vx v28, v16, a2180; CHECK-NEXT: vadd.vx v16, v8, a0181; CHECK-NEXT: vsaddu.vx v16, v16, a1182; CHECK-NEXT: vmsltu.vx v29, v16, a2183; CHECK-NEXT: li a0, 48184; CHECK-NEXT: vadd.vx v8, v8, a0185; CHECK-NEXT: vsaddu.vx v8, v8, a1186; CHECK-NEXT: vmsltu.vx v16, v8, a2187; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma188; CHECK-NEXT: vslideup.vi v25, v24, 2189; CHECK-NEXT: vslideup.vi v0, v28, 2190; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma191; CHECK-NEXT: vslideup.vi v25, v26, 4192; CHECK-NEXT: vslideup.vi v0, v29, 4193; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma194; CHECK-NEXT: vslideup.vi v25, v27, 6195; CHECK-NEXT: vslideup.vi v0, v16, 6196; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma197; CHECK-NEXT: vslideup.vi v0, v25, 8198; CHECK-NEXT: ret199 %mask = call <128 x i1> @llvm.get.active.lane.mask.v128i1.i64(i64 %index, i64 %tc)200 ret <128 x i1> %mask201}202 203