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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v -verify-machineinstrs \3; RUN: -M no-aliases < %s | FileCheck %s4 5target triple = "riscv64-unknown-unknown-elf"6 7define target("riscv.vector.tuple", <vscale x 8 x i8>, 5) @load_store_m1x5(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %tuple) {8; CHECK-LABEL: load_store_m1x5:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: addi sp, sp, -1611; CHECK-NEXT: .cfi_def_cfa_offset 1612; CHECK-NEXT: csrrs a0, vlenb, zero13; CHECK-NEXT: slli a0, a0, 314; CHECK-NEXT: sub sp, sp, a015; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb16; CHECK-NEXT: addi a0, sp, 1617; CHECK-NEXT: csrrs a1, vlenb, zero18; CHECK-NEXT: vs1r.v v8, (a0)19; CHECK-NEXT: add a2, a0, a120; CHECK-NEXT: vs1r.v v9, (a2)21; CHECK-NEXT: add a3, a2, a122; CHECK-NEXT: vs1r.v v10, (a3)23; CHECK-NEXT: add a4, a3, a124; CHECK-NEXT: vs1r.v v11, (a4)25; CHECK-NEXT: add a1, a4, a126; CHECK-NEXT: vs1r.v v12, (a1)27; CHECK-NEXT: #APP28; CHECK-NEXT: #NO_APP29; CHECK-NEXT: vl1re8.v v8, (a0)30; CHECK-NEXT: vl1re8.v v9, (a2)31; CHECK-NEXT: vl1re8.v v10, (a3)32; CHECK-NEXT: vl1re8.v v11, (a4)33; CHECK-NEXT: vl1re8.v v12, (a1)34; CHECK-NEXT: csrrs a0, vlenb, zero35; CHECK-NEXT: slli a0, a0, 336; CHECK-NEXT: add sp, sp, a037; CHECK-NEXT: .cfi_def_cfa sp, 1638; CHECK-NEXT: addi sp, sp, 1639; CHECK-NEXT: .cfi_def_cfa_offset 040; CHECK-NEXT: jalr zero, 0(ra)41entry:42 %tuple.addr = alloca target("riscv.vector.tuple", <vscale x 8 x i8>, 5), align 143 store target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %tuple, ptr %tuple.addr, align 144 call void asm sideeffect "",45 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()46 %0 = load target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr %tuple.addr, align 147 ret target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %048}49 50define target("riscv.vector.tuple", <vscale x 16 x i8>, 2) @load_store_m2x2(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %tuple) {51; CHECK-LABEL: load_store_m2x2:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: addi sp, sp, -1654; CHECK-NEXT: .cfi_def_cfa_offset 1655; CHECK-NEXT: csrrs a0, vlenb, zero56; CHECK-NEXT: slli a0, a0, 257; CHECK-NEXT: sub sp, sp, a058; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb59; CHECK-NEXT: addi a0, sp, 1660; CHECK-NEXT: csrrs a1, vlenb, zero61; CHECK-NEXT: vs2r.v v8, (a0)62; CHECK-NEXT: slli a1, a1, 163; CHECK-NEXT: add a1, a0, a164; CHECK-NEXT: vs2r.v v10, (a1)65; CHECK-NEXT: #APP66; CHECK-NEXT: #NO_APP67; CHECK-NEXT: vl2re8.v v8, (a0)68; CHECK-NEXT: vl2re8.v v10, (a1)69; CHECK-NEXT: csrrs a0, vlenb, zero70; CHECK-NEXT: slli a0, a0, 271; CHECK-NEXT: add sp, sp, a072; CHECK-NEXT: .cfi_def_cfa sp, 1673; CHECK-NEXT: addi sp, sp, 1674; CHECK-NEXT: .cfi_def_cfa_offset 075; CHECK-NEXT: jalr zero, 0(ra)76entry:77 %tuple.addr = alloca target("riscv.vector.tuple", <vscale x 16 x i8>, 2), align 178 store target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %tuple, ptr %tuple.addr, align 179 call void asm sideeffect "",80 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()81 %0 = load target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr %tuple.addr, align 182 ret target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %083}84 85define target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @load_store_m4x2(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %tuple) {86; CHECK-LABEL: load_store_m4x2:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: addi sp, sp, -1689; CHECK-NEXT: .cfi_def_cfa_offset 1690; CHECK-NEXT: csrrs a0, vlenb, zero91; CHECK-NEXT: slli a0, a0, 392; CHECK-NEXT: sub sp, sp, a093; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb94; CHECK-NEXT: addi a0, sp, 1695; CHECK-NEXT: csrrs a1, vlenb, zero96; CHECK-NEXT: vs4r.v v8, (a0)97; CHECK-NEXT: slli a1, a1, 298; CHECK-NEXT: add a1, a0, a199; CHECK-NEXT: vs4r.v v12, (a1)100; CHECK-NEXT: #APP101; CHECK-NEXT: #NO_APP102; CHECK-NEXT: vl4re8.v v8, (a0)103; CHECK-NEXT: vl4re8.v v12, (a1)104; CHECK-NEXT: csrrs a0, vlenb, zero105; CHECK-NEXT: slli a0, a0, 3106; CHECK-NEXT: add sp, sp, a0107; CHECK-NEXT: .cfi_def_cfa sp, 16108; CHECK-NEXT: addi sp, sp, 16109; CHECK-NEXT: .cfi_def_cfa_offset 0110; CHECK-NEXT: jalr zero, 0(ra)111entry:112 %tuple.addr = alloca target("riscv.vector.tuple", <vscale x 32 x i8>, 2), align 1113 store target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %tuple, ptr %tuple.addr, align 1114 call void asm sideeffect "",115 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()116 %0 = load target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr %tuple.addr, align 1117 ret target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0118}119