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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s3; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s4 5; Use unmasked instruction because the mask operand is allone mask6define <vscale x 1 x i8> @test0(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {7; CHECK-LABEL: test0:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma10; CHECK-NEXT: vadd.vv v8, v8, v911; CHECK-NEXT: ret12entry:13 %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(14 iXLen %2);15 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(16 <vscale x 1 x i8> poison,17 <vscale x 1 x i8> %0,18 <vscale x 1 x i8> %1,19 <vscale x 1 x i1> %allone,20 iXLen %2, iXLen 1)21 22 ret <vscale x 1 x i8> %a23}24 25; Use an unmasked TAIL_AGNOSTIC instruction if the tie operand is IMPLICIT_DEF26define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {27; CHECK-LABEL: test1:28; CHECK: # %bb.0: # %entry29; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma30; CHECK-NEXT: vadd.vv v8, v8, v931; CHECK-NEXT: ret32entry:33 %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(34 iXLen %2);35 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(36 <vscale x 1 x i8> poison,37 <vscale x 1 x i8> %0,38 <vscale x 1 x i8> %1,39 <vscale x 1 x i1> %allone,40 iXLen %2, iXLen 0)41 42 ret <vscale x 1 x i8> %a43}44 45; Use an unmasked TU instruction because of the policy operand46define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {47; CHECK-LABEL: test2:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma50; CHECK-NEXT: vadd.vv v8, v9, v1051; CHECK-NEXT: ret52entry:53 %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(54 iXLen %3);55 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(56 <vscale x 1 x i8> %0,57 <vscale x 1 x i8> %1,58 <vscale x 1 x i8> %2,59 <vscale x 1 x i1> %allone,60 iXLen %3, iXLen 0)61 62 ret <vscale x 1 x i8> %a63}64 65; Merge operand is dropped because of the policy operand66define <vscale x 1 x i8> @test3(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {67; CHECK-LABEL: test3:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma70; CHECK-NEXT: vadd.vv v8, v9, v1071; CHECK-NEXT: ret72entry:73 %allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(74 iXLen %3);75 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(76 <vscale x 1 x i8> %0,77 <vscale x 1 x i8> %1,78 <vscale x 1 x i8> %2,79 <vscale x 1 x i1> %allone,80 iXLen %3, iXLen 1)81 82 ret <vscale x 1 x i8> %a83}84