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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5; Check that we perform binary arithmetic in a narrower type where possible, via6; combineBinOpOfZExt or otherwise.7 8define <vscale x 8 x i32> @add(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {9; CHECK-LABEL: add:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma12; CHECK-NEXT: vwaddu.vv v12, v8, v913; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma14; CHECK-NEXT: vzext.vf2 v8, v1215; CHECK-NEXT: ret16 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>17 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>18 %add = add <vscale x 8 x i32> %a.zext, %b.zext19 ret <vscale x 8 x i32> %add20}21 22define <vscale x 8 x i32> @sub(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {23; CHECK-LABEL: sub:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma26; CHECK-NEXT: vwsubu.vv v12, v8, v927; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma28; CHECK-NEXT: vsext.vf2 v8, v1229; CHECK-NEXT: ret30 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>31 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>32 %sub = sub <vscale x 8 x i32> %a.zext, %b.zext33 ret <vscale x 8 x i32> %sub34}35 36define <vscale x 8 x i32> @mul(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {37; CHECK-LABEL: mul:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma40; CHECK-NEXT: vwmulu.vv v12, v8, v941; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma42; CHECK-NEXT: vzext.vf2 v8, v1243; CHECK-NEXT: ret44 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>45 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>46 %mul = mul <vscale x 8 x i32> %a.zext, %b.zext47 ret <vscale x 8 x i32> %mul48}49 50define <vscale x 8 x i32> @sdiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {51; CHECK-LABEL: sdiv:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma54; CHECK-NEXT: vzext.vf2 v10, v955; CHECK-NEXT: vzext.vf2 v12, v856; CHECK-NEXT: vdivu.vv v12, v12, v1057; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma58; CHECK-NEXT: vzext.vf2 v8, v1259; CHECK-NEXT: ret60 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>61 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>62 %sdiv = sdiv <vscale x 8 x i32> %a.zext, %b.zext63 ret <vscale x 8 x i32> %sdiv64}65 66define <vscale x 8 x i32> @udiv(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {67; CHECK-LABEL: udiv:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma70; CHECK-NEXT: vzext.vf2 v10, v971; CHECK-NEXT: vzext.vf2 v12, v872; CHECK-NEXT: vdivu.vv v12, v12, v1073; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma74; CHECK-NEXT: vzext.vf2 v8, v1275; CHECK-NEXT: ret76 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>77 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>78 %udiv = udiv <vscale x 8 x i32> %a.zext, %b.zext79 ret <vscale x 8 x i32> %udiv80}81 82define <vscale x 8 x i32> @srem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {83; CHECK-LABEL: srem:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma86; CHECK-NEXT: vzext.vf2 v10, v987; CHECK-NEXT: vzext.vf2 v12, v888; CHECK-NEXT: vremu.vv v12, v12, v1089; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma90; CHECK-NEXT: vzext.vf2 v8, v1291; CHECK-NEXT: ret92 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>93 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>94 %srem = srem <vscale x 8 x i32> %a.zext, %b.zext95 ret <vscale x 8 x i32> %srem96}97 98define <vscale x 8 x i32> @urem(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {99; CHECK-LABEL: urem:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma102; CHECK-NEXT: vzext.vf2 v10, v9103; CHECK-NEXT: vzext.vf2 v12, v8104; CHECK-NEXT: vremu.vv v12, v12, v10105; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma106; CHECK-NEXT: vzext.vf2 v8, v12107; CHECK-NEXT: ret108 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>109 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>110 %urem = urem <vscale x 8 x i32> %a.zext, %b.zext111 ret <vscale x 8 x i32> %urem112}113 114define <vscale x 8 x i32> @and(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {115; CHECK-LABEL: and:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma118; CHECK-NEXT: vand.vv v12, v8, v9119; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma120; CHECK-NEXT: vzext.vf4 v8, v12121; CHECK-NEXT: ret122 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>123 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>124 %shl = and <vscale x 8 x i32> %a.zext, %b.zext125 ret <vscale x 8 x i32> %shl126}127 128define <vscale x 8 x i32> @or(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {129; CHECK-LABEL: or:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma132; CHECK-NEXT: vor.vv v12, v8, v9133; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma134; CHECK-NEXT: vzext.vf4 v8, v12135; CHECK-NEXT: ret136 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>137 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>138 %or = or <vscale x 8 x i32> %a.zext, %b.zext139 ret <vscale x 8 x i32> %or140}141 142define <vscale x 8 x i32> @xor(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {143; CHECK-LABEL: xor:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma146; CHECK-NEXT: vxor.vv v12, v8, v9147; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma148; CHECK-NEXT: vzext.vf4 v8, v12149; CHECK-NEXT: ret150 %a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i32>151 %b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i32>152 %xor = xor <vscale x 8 x i32> %a.zext, %b.zext153 ret <vscale x 8 x i32> %xor154}155