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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB6 7define <vscale x 1 x i8> @bitreverse_nxv1i8(<vscale x 1 x i8> %va) {8; CHECK-LABEL: bitreverse_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vsll.vi v9, v8, 412; CHECK-NEXT: vsrl.vi v8, v8, 413; CHECK-NEXT: li a0, 5114; CHECK-NEXT: vor.vv v8, v8, v915; CHECK-NEXT: vsrl.vi v9, v8, 216; CHECK-NEXT: vand.vx v8, v8, a017; CHECK-NEXT: vand.vx v9, v9, a018; CHECK-NEXT: li a0, 8519; CHECK-NEXT: vsll.vi v8, v8, 220; CHECK-NEXT: vor.vv v8, v9, v821; CHECK-NEXT: vsrl.vi v9, v8, 122; CHECK-NEXT: vand.vx v8, v8, a023; CHECK-NEXT: vand.vx v9, v9, a024; CHECK-NEXT: vadd.vv v8, v8, v825; CHECK-NEXT: vor.vv v8, v9, v826; CHECK-NEXT: ret27;28; CHECK-ZVBB-LABEL: bitreverse_nxv1i8:29; CHECK-ZVBB: # %bb.0:30; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-ZVBB-NEXT: vbrev.v v8, v832; CHECK-ZVBB-NEXT: ret33 %a = call <vscale x 1 x i8> @llvm.bitreverse.nxv1i8(<vscale x 1 x i8> %va)34 ret <vscale x 1 x i8> %a35}36 37define <vscale x 2 x i8> @bitreverse_nxv2i8(<vscale x 2 x i8> %va) {38; CHECK-LABEL: bitreverse_nxv2i8:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma41; CHECK-NEXT: vsll.vi v9, v8, 442; CHECK-NEXT: vsrl.vi v8, v8, 443; CHECK-NEXT: li a0, 5144; CHECK-NEXT: vor.vv v8, v8, v945; CHECK-NEXT: vsrl.vi v9, v8, 246; CHECK-NEXT: vand.vx v8, v8, a047; CHECK-NEXT: vand.vx v9, v9, a048; CHECK-NEXT: li a0, 8549; CHECK-NEXT: vsll.vi v8, v8, 250; CHECK-NEXT: vor.vv v8, v9, v851; CHECK-NEXT: vsrl.vi v9, v8, 152; CHECK-NEXT: vand.vx v8, v8, a053; CHECK-NEXT: vand.vx v9, v9, a054; CHECK-NEXT: vadd.vv v8, v8, v855; CHECK-NEXT: vor.vv v8, v9, v856; CHECK-NEXT: ret57;58; CHECK-ZVBB-LABEL: bitreverse_nxv2i8:59; CHECK-ZVBB: # %bb.0:60; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma61; CHECK-ZVBB-NEXT: vbrev.v v8, v862; CHECK-ZVBB-NEXT: ret63 %a = call <vscale x 2 x i8> @llvm.bitreverse.nxv2i8(<vscale x 2 x i8> %va)64 ret <vscale x 2 x i8> %a65}66 67define <vscale x 4 x i8> @bitreverse_nxv4i8(<vscale x 4 x i8> %va) {68; CHECK-LABEL: bitreverse_nxv4i8:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma71; CHECK-NEXT: vsll.vi v9, v8, 472; CHECK-NEXT: vsrl.vi v8, v8, 473; CHECK-NEXT: li a0, 5174; CHECK-NEXT: vor.vv v8, v8, v975; CHECK-NEXT: vsrl.vi v9, v8, 276; CHECK-NEXT: vand.vx v8, v8, a077; CHECK-NEXT: vand.vx v9, v9, a078; CHECK-NEXT: li a0, 8579; CHECK-NEXT: vsll.vi v8, v8, 280; CHECK-NEXT: vor.vv v8, v9, v881; CHECK-NEXT: vsrl.vi v9, v8, 182; CHECK-NEXT: vand.vx v8, v8, a083; CHECK-NEXT: vand.vx v9, v9, a084; CHECK-NEXT: vadd.vv v8, v8, v885; CHECK-NEXT: vor.vv v8, v9, v886; CHECK-NEXT: ret87;88; CHECK-ZVBB-LABEL: bitreverse_nxv4i8:89; CHECK-ZVBB: # %bb.0:90; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma91; CHECK-ZVBB-NEXT: vbrev.v v8, v892; CHECK-ZVBB-NEXT: ret93 %a = call <vscale x 4 x i8> @llvm.bitreverse.nxv4i8(<vscale x 4 x i8> %va)94 ret <vscale x 4 x i8> %a95}96 97define <vscale x 8 x i8> @bitreverse_nxv8i8(<vscale x 8 x i8> %va) {98; CHECK-LABEL: bitreverse_nxv8i8:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma101; CHECK-NEXT: vsll.vi v9, v8, 4102; CHECK-NEXT: vsrl.vi v8, v8, 4103; CHECK-NEXT: li a0, 51104; CHECK-NEXT: vor.vv v8, v8, v9105; CHECK-NEXT: vsrl.vi v9, v8, 2106; CHECK-NEXT: vand.vx v8, v8, a0107; CHECK-NEXT: vand.vx v9, v9, a0108; CHECK-NEXT: li a0, 85109; CHECK-NEXT: vsll.vi v8, v8, 2110; CHECK-NEXT: vor.vv v8, v9, v8111; CHECK-NEXT: vsrl.vi v9, v8, 1112; CHECK-NEXT: vand.vx v8, v8, a0113; CHECK-NEXT: vand.vx v9, v9, a0114; CHECK-NEXT: vadd.vv v8, v8, v8115; CHECK-NEXT: vor.vv v8, v9, v8116; CHECK-NEXT: ret117;118; CHECK-ZVBB-LABEL: bitreverse_nxv8i8:119; CHECK-ZVBB: # %bb.0:120; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma121; CHECK-ZVBB-NEXT: vbrev.v v8, v8122; CHECK-ZVBB-NEXT: ret123 %a = call <vscale x 8 x i8> @llvm.bitreverse.nxv8i8(<vscale x 8 x i8> %va)124 ret <vscale x 8 x i8> %a125}126 127define <vscale x 16 x i8> @bitreverse_nxv16i8(<vscale x 16 x i8> %va) {128; CHECK-LABEL: bitreverse_nxv16i8:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma131; CHECK-NEXT: vsll.vi v10, v8, 4132; CHECK-NEXT: vsrl.vi v8, v8, 4133; CHECK-NEXT: li a0, 51134; CHECK-NEXT: vor.vv v8, v8, v10135; CHECK-NEXT: vsrl.vi v10, v8, 2136; CHECK-NEXT: vand.vx v8, v8, a0137; CHECK-NEXT: vand.vx v10, v10, a0138; CHECK-NEXT: li a0, 85139; CHECK-NEXT: vsll.vi v8, v8, 2140; CHECK-NEXT: vor.vv v8, v10, v8141; CHECK-NEXT: vsrl.vi v10, v8, 1142; CHECK-NEXT: vand.vx v8, v8, a0143; CHECK-NEXT: vand.vx v10, v10, a0144; CHECK-NEXT: vadd.vv v8, v8, v8145; CHECK-NEXT: vor.vv v8, v10, v8146; CHECK-NEXT: ret147;148; CHECK-ZVBB-LABEL: bitreverse_nxv16i8:149; CHECK-ZVBB: # %bb.0:150; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma151; CHECK-ZVBB-NEXT: vbrev.v v8, v8152; CHECK-ZVBB-NEXT: ret153 %a = call <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8> %va)154 ret <vscale x 16 x i8> %a155}156 157define <vscale x 32 x i8> @bitreverse_nxv32i8(<vscale x 32 x i8> %va) {158; CHECK-LABEL: bitreverse_nxv32i8:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma161; CHECK-NEXT: vsll.vi v12, v8, 4162; CHECK-NEXT: vsrl.vi v8, v8, 4163; CHECK-NEXT: li a0, 51164; CHECK-NEXT: vor.vv v8, v8, v12165; CHECK-NEXT: vsrl.vi v12, v8, 2166; CHECK-NEXT: vand.vx v8, v8, a0167; CHECK-NEXT: vand.vx v12, v12, a0168; CHECK-NEXT: li a0, 85169; CHECK-NEXT: vsll.vi v8, v8, 2170; CHECK-NEXT: vor.vv v8, v12, v8171; CHECK-NEXT: vsrl.vi v12, v8, 1172; CHECK-NEXT: vand.vx v8, v8, a0173; CHECK-NEXT: vand.vx v12, v12, a0174; CHECK-NEXT: vadd.vv v8, v8, v8175; CHECK-NEXT: vor.vv v8, v12, v8176; CHECK-NEXT: ret177;178; CHECK-ZVBB-LABEL: bitreverse_nxv32i8:179; CHECK-ZVBB: # %bb.0:180; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma181; CHECK-ZVBB-NEXT: vbrev.v v8, v8182; CHECK-ZVBB-NEXT: ret183 %a = call <vscale x 32 x i8> @llvm.bitreverse.nxv32i8(<vscale x 32 x i8> %va)184 ret <vscale x 32 x i8> %a185}186 187define <vscale x 64 x i8> @bitreverse_nxv64i8(<vscale x 64 x i8> %va) {188; CHECK-LABEL: bitreverse_nxv64i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma191; CHECK-NEXT: vsll.vi v16, v8, 4192; CHECK-NEXT: vsrl.vi v8, v8, 4193; CHECK-NEXT: li a0, 51194; CHECK-NEXT: vor.vv v8, v8, v16195; CHECK-NEXT: vsrl.vi v16, v8, 2196; CHECK-NEXT: vand.vx v8, v8, a0197; CHECK-NEXT: vand.vx v16, v16, a0198; CHECK-NEXT: li a0, 85199; CHECK-NEXT: vsll.vi v8, v8, 2200; CHECK-NEXT: vor.vv v8, v16, v8201; CHECK-NEXT: vsrl.vi v16, v8, 1202; CHECK-NEXT: vand.vx v8, v8, a0203; CHECK-NEXT: vand.vx v16, v16, a0204; CHECK-NEXT: vadd.vv v8, v8, v8205; CHECK-NEXT: vor.vv v8, v16, v8206; CHECK-NEXT: ret207;208; CHECK-ZVBB-LABEL: bitreverse_nxv64i8:209; CHECK-ZVBB: # %bb.0:210; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma211; CHECK-ZVBB-NEXT: vbrev.v v8, v8212; CHECK-ZVBB-NEXT: ret213 %a = call <vscale x 64 x i8> @llvm.bitreverse.nxv64i8(<vscale x 64 x i8> %va)214 ret <vscale x 64 x i8> %a215}216 217define <vscale x 1 x i16> @bitreverse_nxv1i16(<vscale x 1 x i16> %va) {218; CHECK-LABEL: bitreverse_nxv1i16:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma221; CHECK-NEXT: vsrl.vi v9, v8, 8222; CHECK-NEXT: vsll.vi v8, v8, 8223; CHECK-NEXT: lui a0, 1224; CHECK-NEXT: vor.vv v8, v8, v9225; CHECK-NEXT: addi a0, a0, -241226; CHECK-NEXT: vsrl.vi v9, v8, 4227; CHECK-NEXT: vand.vx v8, v8, a0228; CHECK-NEXT: vand.vx v9, v9, a0229; CHECK-NEXT: lui a0, 3230; CHECK-NEXT: addi a0, a0, 819231; CHECK-NEXT: vsll.vi v8, v8, 4232; CHECK-NEXT: vor.vv v8, v9, v8233; CHECK-NEXT: vsrl.vi v9, v8, 2234; CHECK-NEXT: vand.vx v8, v8, a0235; CHECK-NEXT: vand.vx v9, v9, a0236; CHECK-NEXT: lui a0, 5237; CHECK-NEXT: addi a0, a0, 1365238; CHECK-NEXT: vsll.vi v8, v8, 2239; CHECK-NEXT: vor.vv v8, v9, v8240; CHECK-NEXT: vsrl.vi v9, v8, 1241; CHECK-NEXT: vand.vx v8, v8, a0242; CHECK-NEXT: vand.vx v9, v9, a0243; CHECK-NEXT: vadd.vv v8, v8, v8244; CHECK-NEXT: vor.vv v8, v9, v8245; CHECK-NEXT: ret246;247; CHECK-ZVBB-LABEL: bitreverse_nxv1i16:248; CHECK-ZVBB: # %bb.0:249; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma250; CHECK-ZVBB-NEXT: vbrev.v v8, v8251; CHECK-ZVBB-NEXT: ret252 %a = call <vscale x 1 x i16> @llvm.bitreverse.nxv1i16(<vscale x 1 x i16> %va)253 ret <vscale x 1 x i16> %a254}255 256define <vscale x 2 x i16> @bitreverse_nxv2i16(<vscale x 2 x i16> %va) {257; CHECK-LABEL: bitreverse_nxv2i16:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma260; CHECK-NEXT: vsrl.vi v9, v8, 8261; CHECK-NEXT: vsll.vi v8, v8, 8262; CHECK-NEXT: lui a0, 1263; CHECK-NEXT: vor.vv v8, v8, v9264; CHECK-NEXT: addi a0, a0, -241265; CHECK-NEXT: vsrl.vi v9, v8, 4266; CHECK-NEXT: vand.vx v8, v8, a0267; CHECK-NEXT: vand.vx v9, v9, a0268; CHECK-NEXT: lui a0, 3269; CHECK-NEXT: addi a0, a0, 819270; CHECK-NEXT: vsll.vi v8, v8, 4271; CHECK-NEXT: vor.vv v8, v9, v8272; CHECK-NEXT: vsrl.vi v9, v8, 2273; CHECK-NEXT: vand.vx v8, v8, a0274; CHECK-NEXT: vand.vx v9, v9, a0275; CHECK-NEXT: lui a0, 5276; CHECK-NEXT: addi a0, a0, 1365277; CHECK-NEXT: vsll.vi v8, v8, 2278; CHECK-NEXT: vor.vv v8, v9, v8279; CHECK-NEXT: vsrl.vi v9, v8, 1280; CHECK-NEXT: vand.vx v8, v8, a0281; CHECK-NEXT: vand.vx v9, v9, a0282; CHECK-NEXT: vadd.vv v8, v8, v8283; CHECK-NEXT: vor.vv v8, v9, v8284; CHECK-NEXT: ret285;286; CHECK-ZVBB-LABEL: bitreverse_nxv2i16:287; CHECK-ZVBB: # %bb.0:288; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma289; CHECK-ZVBB-NEXT: vbrev.v v8, v8290; CHECK-ZVBB-NEXT: ret291 %a = call <vscale x 2 x i16> @llvm.bitreverse.nxv2i16(<vscale x 2 x i16> %va)292 ret <vscale x 2 x i16> %a293}294 295define <vscale x 4 x i16> @bitreverse_nxv4i16(<vscale x 4 x i16> %va) {296; CHECK-LABEL: bitreverse_nxv4i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma299; CHECK-NEXT: vsrl.vi v9, v8, 8300; CHECK-NEXT: vsll.vi v8, v8, 8301; CHECK-NEXT: lui a0, 1302; CHECK-NEXT: vor.vv v8, v8, v9303; CHECK-NEXT: addi a0, a0, -241304; CHECK-NEXT: vsrl.vi v9, v8, 4305; CHECK-NEXT: vand.vx v8, v8, a0306; CHECK-NEXT: vand.vx v9, v9, a0307; CHECK-NEXT: lui a0, 3308; CHECK-NEXT: addi a0, a0, 819309; CHECK-NEXT: vsll.vi v8, v8, 4310; CHECK-NEXT: vor.vv v8, v9, v8311; CHECK-NEXT: vsrl.vi v9, v8, 2312; CHECK-NEXT: vand.vx v8, v8, a0313; CHECK-NEXT: vand.vx v9, v9, a0314; CHECK-NEXT: lui a0, 5315; CHECK-NEXT: addi a0, a0, 1365316; CHECK-NEXT: vsll.vi v8, v8, 2317; CHECK-NEXT: vor.vv v8, v9, v8318; CHECK-NEXT: vsrl.vi v9, v8, 1319; CHECK-NEXT: vand.vx v8, v8, a0320; CHECK-NEXT: vand.vx v9, v9, a0321; CHECK-NEXT: vadd.vv v8, v8, v8322; CHECK-NEXT: vor.vv v8, v9, v8323; CHECK-NEXT: ret324;325; CHECK-ZVBB-LABEL: bitreverse_nxv4i16:326; CHECK-ZVBB: # %bb.0:327; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma328; CHECK-ZVBB-NEXT: vbrev.v v8, v8329; CHECK-ZVBB-NEXT: ret330 %a = call <vscale x 4 x i16> @llvm.bitreverse.nxv4i16(<vscale x 4 x i16> %va)331 ret <vscale x 4 x i16> %a332}333 334define <vscale x 8 x i16> @bitreverse_nxv8i16(<vscale x 8 x i16> %va) {335; CHECK-LABEL: bitreverse_nxv8i16:336; CHECK: # %bb.0:337; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma338; CHECK-NEXT: vsrl.vi v10, v8, 8339; CHECK-NEXT: vsll.vi v8, v8, 8340; CHECK-NEXT: lui a0, 1341; CHECK-NEXT: vor.vv v8, v8, v10342; CHECK-NEXT: addi a0, a0, -241343; CHECK-NEXT: vsrl.vi v10, v8, 4344; CHECK-NEXT: vand.vx v8, v8, a0345; CHECK-NEXT: vand.vx v10, v10, a0346; CHECK-NEXT: lui a0, 3347; CHECK-NEXT: addi a0, a0, 819348; CHECK-NEXT: vsll.vi v8, v8, 4349; CHECK-NEXT: vor.vv v8, v10, v8350; CHECK-NEXT: vsrl.vi v10, v8, 2351; CHECK-NEXT: vand.vx v8, v8, a0352; CHECK-NEXT: vand.vx v10, v10, a0353; CHECK-NEXT: lui a0, 5354; CHECK-NEXT: addi a0, a0, 1365355; CHECK-NEXT: vsll.vi v8, v8, 2356; CHECK-NEXT: vor.vv v8, v10, v8357; CHECK-NEXT: vsrl.vi v10, v8, 1358; CHECK-NEXT: vand.vx v8, v8, a0359; CHECK-NEXT: vand.vx v10, v10, a0360; CHECK-NEXT: vadd.vv v8, v8, v8361; CHECK-NEXT: vor.vv v8, v10, v8362; CHECK-NEXT: ret363;364; CHECK-ZVBB-LABEL: bitreverse_nxv8i16:365; CHECK-ZVBB: # %bb.0:366; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma367; CHECK-ZVBB-NEXT: vbrev.v v8, v8368; CHECK-ZVBB-NEXT: ret369 %a = call <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16> %va)370 ret <vscale x 8 x i16> %a371}372 373define <vscale x 16 x i16> @bitreverse_nxv16i16(<vscale x 16 x i16> %va) {374; CHECK-LABEL: bitreverse_nxv16i16:375; CHECK: # %bb.0:376; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma377; CHECK-NEXT: vsrl.vi v12, v8, 8378; CHECK-NEXT: vsll.vi v8, v8, 8379; CHECK-NEXT: lui a0, 1380; CHECK-NEXT: vor.vv v8, v8, v12381; CHECK-NEXT: addi a0, a0, -241382; CHECK-NEXT: vsrl.vi v12, v8, 4383; CHECK-NEXT: vand.vx v8, v8, a0384; CHECK-NEXT: vand.vx v12, v12, a0385; CHECK-NEXT: lui a0, 3386; CHECK-NEXT: addi a0, a0, 819387; CHECK-NEXT: vsll.vi v8, v8, 4388; CHECK-NEXT: vor.vv v8, v12, v8389; CHECK-NEXT: vsrl.vi v12, v8, 2390; CHECK-NEXT: vand.vx v8, v8, a0391; CHECK-NEXT: vand.vx v12, v12, a0392; CHECK-NEXT: lui a0, 5393; CHECK-NEXT: addi a0, a0, 1365394; CHECK-NEXT: vsll.vi v8, v8, 2395; CHECK-NEXT: vor.vv v8, v12, v8396; CHECK-NEXT: vsrl.vi v12, v8, 1397; CHECK-NEXT: vand.vx v8, v8, a0398; CHECK-NEXT: vand.vx v12, v12, a0399; CHECK-NEXT: vadd.vv v8, v8, v8400; CHECK-NEXT: vor.vv v8, v12, v8401; CHECK-NEXT: ret402;403; CHECK-ZVBB-LABEL: bitreverse_nxv16i16:404; CHECK-ZVBB: # %bb.0:405; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma406; CHECK-ZVBB-NEXT: vbrev.v v8, v8407; CHECK-ZVBB-NEXT: ret408 %a = call <vscale x 16 x i16> @llvm.bitreverse.nxv16i16(<vscale x 16 x i16> %va)409 ret <vscale x 16 x i16> %a410}411 412define <vscale x 32 x i16> @bitreverse_nxv32i16(<vscale x 32 x i16> %va) {413; CHECK-LABEL: bitreverse_nxv32i16:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma416; CHECK-NEXT: vsrl.vi v16, v8, 8417; CHECK-NEXT: vsll.vi v8, v8, 8418; CHECK-NEXT: lui a0, 1419; CHECK-NEXT: vor.vv v8, v8, v16420; CHECK-NEXT: addi a0, a0, -241421; CHECK-NEXT: vsrl.vi v16, v8, 4422; CHECK-NEXT: vand.vx v8, v8, a0423; CHECK-NEXT: vand.vx v16, v16, a0424; CHECK-NEXT: lui a0, 3425; CHECK-NEXT: addi a0, a0, 819426; CHECK-NEXT: vsll.vi v8, v8, 4427; CHECK-NEXT: vor.vv v8, v16, v8428; CHECK-NEXT: vsrl.vi v16, v8, 2429; CHECK-NEXT: vand.vx v8, v8, a0430; CHECK-NEXT: vand.vx v16, v16, a0431; CHECK-NEXT: lui a0, 5432; CHECK-NEXT: addi a0, a0, 1365433; CHECK-NEXT: vsll.vi v8, v8, 2434; CHECK-NEXT: vor.vv v8, v16, v8435; CHECK-NEXT: vsrl.vi v16, v8, 1436; CHECK-NEXT: vand.vx v8, v8, a0437; CHECK-NEXT: vand.vx v16, v16, a0438; CHECK-NEXT: vadd.vv v8, v8, v8439; CHECK-NEXT: vor.vv v8, v16, v8440; CHECK-NEXT: ret441;442; CHECK-ZVBB-LABEL: bitreverse_nxv32i16:443; CHECK-ZVBB: # %bb.0:444; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma445; CHECK-ZVBB-NEXT: vbrev.v v8, v8446; CHECK-ZVBB-NEXT: ret447 %a = call <vscale x 32 x i16> @llvm.bitreverse.nxv32i16(<vscale x 32 x i16> %va)448 ret <vscale x 32 x i16> %a449}450 451define <vscale x 1 x i32> @bitreverse_nxv1i32(<vscale x 1 x i32> %va) {452; CHECK-LABEL: bitreverse_nxv1i32:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma455; CHECK-NEXT: vsrl.vi v9, v8, 8456; CHECK-NEXT: lui a0, 16457; CHECK-NEXT: vsrl.vi v10, v8, 24458; CHECK-NEXT: addi a0, a0, -256459; CHECK-NEXT: vand.vx v9, v9, a0460; CHECK-NEXT: vor.vv v9, v9, v10461; CHECK-NEXT: vsll.vi v10, v8, 24462; CHECK-NEXT: vand.vx v8, v8, a0463; CHECK-NEXT: lui a0, 61681464; CHECK-NEXT: addi a0, a0, -241465; CHECK-NEXT: vsll.vi v8, v8, 8466; CHECK-NEXT: vor.vv v8, v10, v8467; CHECK-NEXT: vor.vv v8, v8, v9468; CHECK-NEXT: vsrl.vi v9, v8, 4469; CHECK-NEXT: vand.vx v8, v8, a0470; CHECK-NEXT: vand.vx v9, v9, a0471; CHECK-NEXT: lui a0, 209715472; CHECK-NEXT: addi a0, a0, 819473; CHECK-NEXT: vsll.vi v8, v8, 4474; CHECK-NEXT: vor.vv v8, v9, v8475; CHECK-NEXT: vsrl.vi v9, v8, 2476; CHECK-NEXT: vand.vx v8, v8, a0477; CHECK-NEXT: vand.vx v9, v9, a0478; CHECK-NEXT: lui a0, 349525479; CHECK-NEXT: addi a0, a0, 1365480; CHECK-NEXT: vsll.vi v8, v8, 2481; CHECK-NEXT: vor.vv v8, v9, v8482; CHECK-NEXT: vsrl.vi v9, v8, 1483; CHECK-NEXT: vand.vx v8, v8, a0484; CHECK-NEXT: vand.vx v9, v9, a0485; CHECK-NEXT: vadd.vv v8, v8, v8486; CHECK-NEXT: vor.vv v8, v9, v8487; CHECK-NEXT: ret488;489; CHECK-ZVBB-LABEL: bitreverse_nxv1i32:490; CHECK-ZVBB: # %bb.0:491; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma492; CHECK-ZVBB-NEXT: vbrev.v v8, v8493; CHECK-ZVBB-NEXT: ret494 %a = call <vscale x 1 x i32> @llvm.bitreverse.nxv1i32(<vscale x 1 x i32> %va)495 ret <vscale x 1 x i32> %a496}497 498define <vscale x 2 x i32> @bitreverse_nxv2i32(<vscale x 2 x i32> %va) {499; CHECK-LABEL: bitreverse_nxv2i32:500; CHECK: # %bb.0:501; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma502; CHECK-NEXT: vsrl.vi v9, v8, 8503; CHECK-NEXT: lui a0, 16504; CHECK-NEXT: vsrl.vi v10, v8, 24505; CHECK-NEXT: addi a0, a0, -256506; CHECK-NEXT: vand.vx v9, v9, a0507; CHECK-NEXT: vor.vv v9, v9, v10508; CHECK-NEXT: vsll.vi v10, v8, 24509; CHECK-NEXT: vand.vx v8, v8, a0510; CHECK-NEXT: lui a0, 61681511; CHECK-NEXT: addi a0, a0, -241512; CHECK-NEXT: vsll.vi v8, v8, 8513; CHECK-NEXT: vor.vv v8, v10, v8514; CHECK-NEXT: vor.vv v8, v8, v9515; CHECK-NEXT: vsrl.vi v9, v8, 4516; CHECK-NEXT: vand.vx v8, v8, a0517; CHECK-NEXT: vand.vx v9, v9, a0518; CHECK-NEXT: lui a0, 209715519; CHECK-NEXT: addi a0, a0, 819520; CHECK-NEXT: vsll.vi v8, v8, 4521; CHECK-NEXT: vor.vv v8, v9, v8522; CHECK-NEXT: vsrl.vi v9, v8, 2523; CHECK-NEXT: vand.vx v8, v8, a0524; CHECK-NEXT: vand.vx v9, v9, a0525; CHECK-NEXT: lui a0, 349525526; CHECK-NEXT: addi a0, a0, 1365527; CHECK-NEXT: vsll.vi v8, v8, 2528; CHECK-NEXT: vor.vv v8, v9, v8529; CHECK-NEXT: vsrl.vi v9, v8, 1530; CHECK-NEXT: vand.vx v8, v8, a0531; CHECK-NEXT: vand.vx v9, v9, a0532; CHECK-NEXT: vadd.vv v8, v8, v8533; CHECK-NEXT: vor.vv v8, v9, v8534; CHECK-NEXT: ret535;536; CHECK-ZVBB-LABEL: bitreverse_nxv2i32:537; CHECK-ZVBB: # %bb.0:538; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma539; CHECK-ZVBB-NEXT: vbrev.v v8, v8540; CHECK-ZVBB-NEXT: ret541 %a = call <vscale x 2 x i32> @llvm.bitreverse.nxv2i32(<vscale x 2 x i32> %va)542 ret <vscale x 2 x i32> %a543}544 545define <vscale x 4 x i32> @bitreverse_nxv4i32(<vscale x 4 x i32> %va) {546; CHECK-LABEL: bitreverse_nxv4i32:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma549; CHECK-NEXT: vsrl.vi v10, v8, 8550; CHECK-NEXT: lui a0, 16551; CHECK-NEXT: vsrl.vi v12, v8, 24552; CHECK-NEXT: addi a0, a0, -256553; CHECK-NEXT: vand.vx v10, v10, a0554; CHECK-NEXT: vor.vv v10, v10, v12555; CHECK-NEXT: vsll.vi v12, v8, 24556; CHECK-NEXT: vand.vx v8, v8, a0557; CHECK-NEXT: lui a0, 61681558; CHECK-NEXT: addi a0, a0, -241559; CHECK-NEXT: vsll.vi v8, v8, 8560; CHECK-NEXT: vor.vv v8, v12, v8561; CHECK-NEXT: vor.vv v8, v8, v10562; CHECK-NEXT: vsrl.vi v10, v8, 4563; CHECK-NEXT: vand.vx v8, v8, a0564; CHECK-NEXT: vand.vx v10, v10, a0565; CHECK-NEXT: lui a0, 209715566; CHECK-NEXT: addi a0, a0, 819567; CHECK-NEXT: vsll.vi v8, v8, 4568; CHECK-NEXT: vor.vv v8, v10, v8569; CHECK-NEXT: vsrl.vi v10, v8, 2570; CHECK-NEXT: vand.vx v8, v8, a0571; CHECK-NEXT: vand.vx v10, v10, a0572; CHECK-NEXT: lui a0, 349525573; CHECK-NEXT: addi a0, a0, 1365574; CHECK-NEXT: vsll.vi v8, v8, 2575; CHECK-NEXT: vor.vv v8, v10, v8576; CHECK-NEXT: vsrl.vi v10, v8, 1577; CHECK-NEXT: vand.vx v8, v8, a0578; CHECK-NEXT: vand.vx v10, v10, a0579; CHECK-NEXT: vadd.vv v8, v8, v8580; CHECK-NEXT: vor.vv v8, v10, v8581; CHECK-NEXT: ret582;583; CHECK-ZVBB-LABEL: bitreverse_nxv4i32:584; CHECK-ZVBB: # %bb.0:585; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma586; CHECK-ZVBB-NEXT: vbrev.v v8, v8587; CHECK-ZVBB-NEXT: ret588 %a = call <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32> %va)589 ret <vscale x 4 x i32> %a590}591 592define <vscale x 8 x i32> @bitreverse_nxv8i32(<vscale x 8 x i32> %va) {593; CHECK-LABEL: bitreverse_nxv8i32:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma596; CHECK-NEXT: vsrl.vi v12, v8, 8597; CHECK-NEXT: lui a0, 16598; CHECK-NEXT: vsrl.vi v16, v8, 24599; CHECK-NEXT: addi a0, a0, -256600; CHECK-NEXT: vand.vx v12, v12, a0601; CHECK-NEXT: vor.vv v12, v12, v16602; CHECK-NEXT: vsll.vi v16, v8, 24603; CHECK-NEXT: vand.vx v8, v8, a0604; CHECK-NEXT: lui a0, 61681605; CHECK-NEXT: addi a0, a0, -241606; CHECK-NEXT: vsll.vi v8, v8, 8607; CHECK-NEXT: vor.vv v8, v16, v8608; CHECK-NEXT: vor.vv v8, v8, v12609; CHECK-NEXT: vsrl.vi v12, v8, 4610; CHECK-NEXT: vand.vx v8, v8, a0611; CHECK-NEXT: vand.vx v12, v12, a0612; CHECK-NEXT: lui a0, 209715613; CHECK-NEXT: addi a0, a0, 819614; CHECK-NEXT: vsll.vi v8, v8, 4615; CHECK-NEXT: vor.vv v8, v12, v8616; CHECK-NEXT: vsrl.vi v12, v8, 2617; CHECK-NEXT: vand.vx v8, v8, a0618; CHECK-NEXT: vand.vx v12, v12, a0619; CHECK-NEXT: lui a0, 349525620; CHECK-NEXT: addi a0, a0, 1365621; CHECK-NEXT: vsll.vi v8, v8, 2622; CHECK-NEXT: vor.vv v8, v12, v8623; CHECK-NEXT: vsrl.vi v12, v8, 1624; CHECK-NEXT: vand.vx v8, v8, a0625; CHECK-NEXT: vand.vx v12, v12, a0626; CHECK-NEXT: vadd.vv v8, v8, v8627; CHECK-NEXT: vor.vv v8, v12, v8628; CHECK-NEXT: ret629;630; CHECK-ZVBB-LABEL: bitreverse_nxv8i32:631; CHECK-ZVBB: # %bb.0:632; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma633; CHECK-ZVBB-NEXT: vbrev.v v8, v8634; CHECK-ZVBB-NEXT: ret635 %a = call <vscale x 8 x i32> @llvm.bitreverse.nxv8i32(<vscale x 8 x i32> %va)636 ret <vscale x 8 x i32> %a637}638 639define <vscale x 16 x i32> @bitreverse_nxv16i32(<vscale x 16 x i32> %va) {640; CHECK-LABEL: bitreverse_nxv16i32:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma643; CHECK-NEXT: vsrl.vi v16, v8, 8644; CHECK-NEXT: lui a0, 16645; CHECK-NEXT: vsrl.vi v24, v8, 24646; CHECK-NEXT: addi a0, a0, -256647; CHECK-NEXT: vand.vx v16, v16, a0648; CHECK-NEXT: vor.vv v16, v16, v24649; CHECK-NEXT: vsll.vi v24, v8, 24650; CHECK-NEXT: vand.vx v8, v8, a0651; CHECK-NEXT: lui a0, 61681652; CHECK-NEXT: addi a0, a0, -241653; CHECK-NEXT: vsll.vi v8, v8, 8654; CHECK-NEXT: vor.vv v8, v24, v8655; CHECK-NEXT: vor.vv v8, v8, v16656; CHECK-NEXT: vsrl.vi v16, v8, 4657; CHECK-NEXT: vand.vx v8, v8, a0658; CHECK-NEXT: vand.vx v16, v16, a0659; CHECK-NEXT: lui a0, 209715660; CHECK-NEXT: addi a0, a0, 819661; CHECK-NEXT: vsll.vi v8, v8, 4662; CHECK-NEXT: vor.vv v8, v16, v8663; CHECK-NEXT: vsrl.vi v16, v8, 2664; CHECK-NEXT: vand.vx v8, v8, a0665; CHECK-NEXT: vand.vx v16, v16, a0666; CHECK-NEXT: lui a0, 349525667; CHECK-NEXT: addi a0, a0, 1365668; CHECK-NEXT: vsll.vi v8, v8, 2669; CHECK-NEXT: vor.vv v8, v16, v8670; CHECK-NEXT: vsrl.vi v16, v8, 1671; CHECK-NEXT: vand.vx v8, v8, a0672; CHECK-NEXT: vand.vx v16, v16, a0673; CHECK-NEXT: vadd.vv v8, v8, v8674; CHECK-NEXT: vor.vv v8, v16, v8675; CHECK-NEXT: ret676;677; CHECK-ZVBB-LABEL: bitreverse_nxv16i32:678; CHECK-ZVBB: # %bb.0:679; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma680; CHECK-ZVBB-NEXT: vbrev.v v8, v8681; CHECK-ZVBB-NEXT: ret682 %a = call <vscale x 16 x i32> @llvm.bitreverse.nxv16i32(<vscale x 16 x i32> %va)683 ret <vscale x 16 x i32> %a684}685 686define <vscale x 1 x i64> @bitreverse_nxv1i64(<vscale x 1 x i64> %va) {687; RV32-LABEL: bitreverse_nxv1i64:688; RV32: # %bb.0:689; RV32-NEXT: addi sp, sp, -16690; RV32-NEXT: .cfi_def_cfa_offset 16691; RV32-NEXT: lui a0, 1044480692; RV32-NEXT: li a1, 56693; RV32-NEXT: li a2, 40694; RV32-NEXT: lui a3, 16695; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma696; RV32-NEXT: vsrl.vi v9, v8, 24697; RV32-NEXT: lui a4, 4080698; RV32-NEXT: addi a5, sp, 8699; RV32-NEXT: sw a0, 8(sp)700; RV32-NEXT: sw zero, 12(sp)701; RV32-NEXT: vsrl.vx v10, v8, a1702; RV32-NEXT: vsrl.vx v11, v8, a2703; RV32-NEXT: addi a0, a3, -256704; RV32-NEXT: vsll.vx v12, v8, a1705; RV32-NEXT: vand.vx v11, v11, a0706; RV32-NEXT: vlse64.v v13, (a5), zero707; RV32-NEXT: vor.vv v10, v11, v10708; RV32-NEXT: vand.vx v11, v8, a0709; RV32-NEXT: vsll.vx v11, v11, a2710; RV32-NEXT: vor.vv v11, v12, v11711; RV32-NEXT: vsrl.vi v12, v8, 8712; RV32-NEXT: vand.vx v9, v9, a4713; RV32-NEXT: vand.vv v12, v12, v13714; RV32-NEXT: vor.vv v9, v12, v9715; RV32-NEXT: lui a0, 61681716; RV32-NEXT: lui a1, 209715717; RV32-NEXT: lui a2, 349525718; RV32-NEXT: vand.vv v12, v8, v13719; RV32-NEXT: vand.vx v8, v8, a4720; RV32-NEXT: addi a0, a0, -241721; RV32-NEXT: addi a1, a1, 819722; RV32-NEXT: addi a2, a2, 1365723; RV32-NEXT: vsll.vi v8, v8, 24724; RV32-NEXT: vor.vv v9, v9, v10725; RV32-NEXT: vsetvli a3, zero, e32, m1, ta, ma726; RV32-NEXT: vmv.v.x v10, a0727; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma728; RV32-NEXT: vsll.vi v12, v12, 8729; RV32-NEXT: vor.vv v8, v8, v12730; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma731; RV32-NEXT: vmv.v.x v12, a1732; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma733; RV32-NEXT: vor.vv v8, v11, v8734; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma735; RV32-NEXT: vmv.v.x v11, a2736; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma737; RV32-NEXT: vor.vv v8, v8, v9738; RV32-NEXT: vsrl.vi v9, v8, 4739; RV32-NEXT: vand.vv v8, v8, v10740; RV32-NEXT: vand.vv v9, v9, v10741; RV32-NEXT: vsll.vi v8, v8, 4742; RV32-NEXT: vor.vv v8, v9, v8743; RV32-NEXT: vsrl.vi v9, v8, 2744; RV32-NEXT: vand.vv v8, v8, v12745; RV32-NEXT: vand.vv v9, v9, v12746; RV32-NEXT: vsll.vi v8, v8, 2747; RV32-NEXT: vor.vv v8, v9, v8748; RV32-NEXT: vsrl.vi v9, v8, 1749; RV32-NEXT: vand.vv v8, v8, v11750; RV32-NEXT: vand.vv v9, v9, v11751; RV32-NEXT: vadd.vv v8, v8, v8752; RV32-NEXT: vor.vv v8, v9, v8753; RV32-NEXT: addi sp, sp, 16754; RV32-NEXT: .cfi_def_cfa_offset 0755; RV32-NEXT: ret756;757; RV64-LABEL: bitreverse_nxv1i64:758; RV64: # %bb.0:759; RV64-NEXT: li a1, 56760; RV64-NEXT: li a0, 40761; RV64-NEXT: lui a2, 16762; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma763; RV64-NEXT: vsrl.vi v9, v8, 24764; RV64-NEXT: lui a3, 4080765; RV64-NEXT: vsrl.vx v10, v8, a1766; RV64-NEXT: vsrl.vx v11, v8, a0767; RV64-NEXT: addi a2, a2, -256768; RV64-NEXT: vand.vx v11, v11, a2769; RV64-NEXT: vor.vv v10, v11, v10770; RV64-NEXT: vsrl.vi v11, v8, 8771; RV64-NEXT: li a4, 255772; RV64-NEXT: vand.vx v9, v9, a3773; RV64-NEXT: slli a4, a4, 24774; RV64-NEXT: vand.vx v11, v11, a4775; RV64-NEXT: vor.vv v9, v11, v9776; RV64-NEXT: vand.vx v11, v8, a3777; RV64-NEXT: lui a3, 61681778; RV64-NEXT: vor.vv v9, v9, v10779; RV64-NEXT: vand.vx v10, v8, a4780; RV64-NEXT: lui a4, 209715781; RV64-NEXT: vsll.vi v11, v11, 24782; RV64-NEXT: vsll.vi v10, v10, 8783; RV64-NEXT: vor.vv v10, v11, v10784; RV64-NEXT: vsll.vx v11, v8, a1785; RV64-NEXT: lui a1, 349525786; RV64-NEXT: addi a3, a3, -241787; RV64-NEXT: addi a4, a4, 819788; RV64-NEXT: addi a1, a1, 1365789; RV64-NEXT: vand.vx v8, v8, a2790; RV64-NEXT: slli a2, a3, 32791; RV64-NEXT: vsll.vx v8, v8, a0792; RV64-NEXT: slli a0, a4, 32793; RV64-NEXT: add a2, a3, a2794; RV64-NEXT: slli a3, a1, 32795; RV64-NEXT: add a0, a4, a0796; RV64-NEXT: add a1, a1, a3797; RV64-NEXT: vor.vv v8, v11, v8798; RV64-NEXT: vor.vv v8, v8, v10799; RV64-NEXT: vor.vv v8, v8, v9800; RV64-NEXT: vsrl.vi v9, v8, 4801; RV64-NEXT: vand.vx v8, v8, a2802; RV64-NEXT: vand.vx v9, v9, a2803; RV64-NEXT: vsll.vi v8, v8, 4804; RV64-NEXT: vor.vv v8, v9, v8805; RV64-NEXT: vsrl.vi v9, v8, 2806; RV64-NEXT: vand.vx v8, v8, a0807; RV64-NEXT: vand.vx v9, v9, a0808; RV64-NEXT: vsll.vi v8, v8, 2809; RV64-NEXT: vor.vv v8, v9, v8810; RV64-NEXT: vsrl.vi v9, v8, 1811; RV64-NEXT: vand.vx v8, v8, a1812; RV64-NEXT: vand.vx v9, v9, a1813; RV64-NEXT: vadd.vv v8, v8, v8814; RV64-NEXT: vor.vv v8, v9, v8815; RV64-NEXT: ret816;817; CHECK-ZVBB-LABEL: bitreverse_nxv1i64:818; CHECK-ZVBB: # %bb.0:819; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma820; CHECK-ZVBB-NEXT: vbrev.v v8, v8821; CHECK-ZVBB-NEXT: ret822 %a = call <vscale x 1 x i64> @llvm.bitreverse.nxv1i64(<vscale x 1 x i64> %va)823 ret <vscale x 1 x i64> %a824}825 826define <vscale x 2 x i64> @bitreverse_nxv2i64(<vscale x 2 x i64> %va) {827; RV32-LABEL: bitreverse_nxv2i64:828; RV32: # %bb.0:829; RV32-NEXT: addi sp, sp, -16830; RV32-NEXT: .cfi_def_cfa_offset 16831; RV32-NEXT: lui a0, 1044480832; RV32-NEXT: li a1, 56833; RV32-NEXT: li a2, 40834; RV32-NEXT: lui a3, 16835; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma836; RV32-NEXT: vsrl.vi v16, v8, 24837; RV32-NEXT: lui a4, 4080838; RV32-NEXT: addi a5, sp, 8839; RV32-NEXT: sw a0, 8(sp)840; RV32-NEXT: sw zero, 12(sp)841; RV32-NEXT: vsrl.vx v10, v8, a1842; RV32-NEXT: vsrl.vx v12, v8, a2843; RV32-NEXT: addi a0, a3, -256844; RV32-NEXT: vsll.vx v18, v8, a1845; RV32-NEXT: vand.vx v12, v12, a0846; RV32-NEXT: vlse64.v v14, (a5), zero847; RV32-NEXT: vor.vv v12, v12, v10848; RV32-NEXT: vand.vx v10, v8, a0849; RV32-NEXT: vsll.vx v10, v10, a2850; RV32-NEXT: vor.vv v10, v18, v10851; RV32-NEXT: vsrl.vi v18, v8, 8852; RV32-NEXT: vand.vx v16, v16, a4853; RV32-NEXT: vand.vv v18, v18, v14854; RV32-NEXT: vor.vv v16, v18, v16855; RV32-NEXT: lui a0, 61681856; RV32-NEXT: lui a1, 209715857; RV32-NEXT: lui a2, 349525858; RV32-NEXT: vand.vv v14, v8, v14859; RV32-NEXT: vand.vx v8, v8, a4860; RV32-NEXT: addi a0, a0, -241861; RV32-NEXT: addi a1, a1, 819862; RV32-NEXT: addi a2, a2, 1365863; RV32-NEXT: vsll.vi v8, v8, 24864; RV32-NEXT: vor.vv v12, v16, v12865; RV32-NEXT: vsetvli a3, zero, e32, m2, ta, ma866; RV32-NEXT: vmv.v.x v16, a0867; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma868; RV32-NEXT: vsll.vi v14, v14, 8869; RV32-NEXT: vor.vv v8, v8, v14870; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma871; RV32-NEXT: vmv.v.x v14, a1872; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma873; RV32-NEXT: vor.vv v8, v10, v8874; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma875; RV32-NEXT: vmv.v.x v10, a2876; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma877; RV32-NEXT: vor.vv v8, v8, v12878; RV32-NEXT: vsrl.vi v12, v8, 4879; RV32-NEXT: vand.vv v8, v8, v16880; RV32-NEXT: vand.vv v12, v12, v16881; RV32-NEXT: vsll.vi v8, v8, 4882; RV32-NEXT: vor.vv v8, v12, v8883; RV32-NEXT: vsrl.vi v12, v8, 2884; RV32-NEXT: vand.vv v8, v8, v14885; RV32-NEXT: vand.vv v12, v12, v14886; RV32-NEXT: vsll.vi v8, v8, 2887; RV32-NEXT: vor.vv v8, v12, v8888; RV32-NEXT: vsrl.vi v12, v8, 1889; RV32-NEXT: vand.vv v8, v8, v10890; RV32-NEXT: vand.vv v10, v12, v10891; RV32-NEXT: vadd.vv v8, v8, v8892; RV32-NEXT: vor.vv v8, v10, v8893; RV32-NEXT: addi sp, sp, 16894; RV32-NEXT: .cfi_def_cfa_offset 0895; RV32-NEXT: ret896;897; RV64-LABEL: bitreverse_nxv2i64:898; RV64: # %bb.0:899; RV64-NEXT: li a1, 56900; RV64-NEXT: li a0, 40901; RV64-NEXT: lui a2, 16902; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma903; RV64-NEXT: vsrl.vi v10, v8, 24904; RV64-NEXT: lui a3, 4080905; RV64-NEXT: vsrl.vx v12, v8, a1906; RV64-NEXT: vsrl.vx v14, v8, a0907; RV64-NEXT: addi a2, a2, -256908; RV64-NEXT: vand.vx v14, v14, a2909; RV64-NEXT: vor.vv v12, v14, v12910; RV64-NEXT: vsrl.vi v14, v8, 8911; RV64-NEXT: li a4, 255912; RV64-NEXT: vand.vx v10, v10, a3913; RV64-NEXT: slli a4, a4, 24914; RV64-NEXT: vand.vx v14, v14, a4915; RV64-NEXT: vor.vv v10, v14, v10916; RV64-NEXT: vand.vx v14, v8, a3917; RV64-NEXT: lui a3, 61681918; RV64-NEXT: vor.vv v10, v10, v12919; RV64-NEXT: vand.vx v12, v8, a4920; RV64-NEXT: lui a4, 209715921; RV64-NEXT: vsll.vi v14, v14, 24922; RV64-NEXT: vsll.vi v12, v12, 8923; RV64-NEXT: vor.vv v12, v14, v12924; RV64-NEXT: vsll.vx v14, v8, a1925; RV64-NEXT: lui a1, 349525926; RV64-NEXT: addi a3, a3, -241927; RV64-NEXT: addi a4, a4, 819928; RV64-NEXT: addi a1, a1, 1365929; RV64-NEXT: vand.vx v8, v8, a2930; RV64-NEXT: slli a2, a3, 32931; RV64-NEXT: vsll.vx v8, v8, a0932; RV64-NEXT: slli a0, a4, 32933; RV64-NEXT: add a2, a3, a2934; RV64-NEXT: slli a3, a1, 32935; RV64-NEXT: add a0, a4, a0936; RV64-NEXT: add a1, a1, a3937; RV64-NEXT: vor.vv v8, v14, v8938; RV64-NEXT: vor.vv v8, v8, v12939; RV64-NEXT: vor.vv v8, v8, v10940; RV64-NEXT: vsrl.vi v10, v8, 4941; RV64-NEXT: vand.vx v8, v8, a2942; RV64-NEXT: vand.vx v10, v10, a2943; RV64-NEXT: vsll.vi v8, v8, 4944; RV64-NEXT: vor.vv v8, v10, v8945; RV64-NEXT: vsrl.vi v10, v8, 2946; RV64-NEXT: vand.vx v8, v8, a0947; RV64-NEXT: vand.vx v10, v10, a0948; RV64-NEXT: vsll.vi v8, v8, 2949; RV64-NEXT: vor.vv v8, v10, v8950; RV64-NEXT: vsrl.vi v10, v8, 1951; RV64-NEXT: vand.vx v8, v8, a1952; RV64-NEXT: vand.vx v10, v10, a1953; RV64-NEXT: vadd.vv v8, v8, v8954; RV64-NEXT: vor.vv v8, v10, v8955; RV64-NEXT: ret956;957; CHECK-ZVBB-LABEL: bitreverse_nxv2i64:958; CHECK-ZVBB: # %bb.0:959; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma960; CHECK-ZVBB-NEXT: vbrev.v v8, v8961; CHECK-ZVBB-NEXT: ret962 %a = call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %va)963 ret <vscale x 2 x i64> %a964}965 966define <vscale x 4 x i64> @bitreverse_nxv4i64(<vscale x 4 x i64> %va) {967; RV32-LABEL: bitreverse_nxv4i64:968; RV32: # %bb.0:969; RV32-NEXT: addi sp, sp, -16970; RV32-NEXT: .cfi_def_cfa_offset 16971; RV32-NEXT: lui a0, 1044480972; RV32-NEXT: li a1, 56973; RV32-NEXT: li a2, 40974; RV32-NEXT: lui a3, 16975; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma976; RV32-NEXT: vsrl.vi v24, v8, 24977; RV32-NEXT: lui a4, 4080978; RV32-NEXT: addi a5, sp, 8979; RV32-NEXT: sw a0, 8(sp)980; RV32-NEXT: sw zero, 12(sp)981; RV32-NEXT: vsrl.vx v12, v8, a1982; RV32-NEXT: vsrl.vx v16, v8, a2983; RV32-NEXT: addi a0, a3, -256984; RV32-NEXT: vsll.vx v28, v8, a1985; RV32-NEXT: vand.vx v16, v16, a0986; RV32-NEXT: vlse64.v v20, (a5), zero987; RV32-NEXT: vor.vv v16, v16, v12988; RV32-NEXT: vand.vx v12, v8, a0989; RV32-NEXT: vsll.vx v12, v12, a2990; RV32-NEXT: vor.vv v12, v28, v12991; RV32-NEXT: vsrl.vi v28, v8, 8992; RV32-NEXT: vand.vx v24, v24, a4993; RV32-NEXT: vand.vv v28, v28, v20994; RV32-NEXT: vor.vv v24, v28, v24995; RV32-NEXT: lui a0, 61681996; RV32-NEXT: lui a1, 209715997; RV32-NEXT: lui a2, 349525998; RV32-NEXT: vand.vv v20, v8, v20999; RV32-NEXT: vand.vx v8, v8, a41000; RV32-NEXT: addi a0, a0, -2411001; RV32-NEXT: addi a1, a1, 8191002; RV32-NEXT: addi a2, a2, 13651003; RV32-NEXT: vsll.vi v8, v8, 241004; RV32-NEXT: vor.vv v16, v24, v161005; RV32-NEXT: vsetvli a3, zero, e32, m4, ta, ma1006; RV32-NEXT: vmv.v.x v24, a01007; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1008; RV32-NEXT: vsll.vi v20, v20, 81009; RV32-NEXT: vor.vv v8, v8, v201010; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma1011; RV32-NEXT: vmv.v.x v20, a11012; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1013; RV32-NEXT: vor.vv v8, v12, v81014; RV32-NEXT: vsetvli a0, zero, e32, m4, ta, ma1015; RV32-NEXT: vmv.v.x v12, a21016; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1017; RV32-NEXT: vor.vv v8, v8, v161018; RV32-NEXT: vsrl.vi v16, v8, 41019; RV32-NEXT: vand.vv v8, v8, v241020; RV32-NEXT: vand.vv v16, v16, v241021; RV32-NEXT: vsll.vi v8, v8, 41022; RV32-NEXT: vor.vv v8, v16, v81023; RV32-NEXT: vsrl.vi v16, v8, 21024; RV32-NEXT: vand.vv v8, v8, v201025; RV32-NEXT: vand.vv v16, v16, v201026; RV32-NEXT: vsll.vi v8, v8, 21027; RV32-NEXT: vor.vv v8, v16, v81028; RV32-NEXT: vsrl.vi v16, v8, 11029; RV32-NEXT: vand.vv v8, v8, v121030; RV32-NEXT: vand.vv v12, v16, v121031; RV32-NEXT: vadd.vv v8, v8, v81032; RV32-NEXT: vor.vv v8, v12, v81033; RV32-NEXT: addi sp, sp, 161034; RV32-NEXT: .cfi_def_cfa_offset 01035; RV32-NEXT: ret1036;1037; RV64-LABEL: bitreverse_nxv4i64:1038; RV64: # %bb.0:1039; RV64-NEXT: li a1, 561040; RV64-NEXT: li a0, 401041; RV64-NEXT: lui a2, 161042; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma1043; RV64-NEXT: vsrl.vi v16, v8, 241044; RV64-NEXT: lui a3, 40801045; RV64-NEXT: vsrl.vx v12, v8, a11046; RV64-NEXT: vsrl.vx v20, v8, a01047; RV64-NEXT: addi a2, a2, -2561048; RV64-NEXT: vand.vx v20, v20, a21049; RV64-NEXT: vor.vv v12, v20, v121050; RV64-NEXT: vsrl.vi v20, v8, 81051; RV64-NEXT: li a4, 2551052; RV64-NEXT: vand.vx v16, v16, a31053; RV64-NEXT: slli a4, a4, 241054; RV64-NEXT: vand.vx v20, v20, a41055; RV64-NEXT: vor.vv v20, v20, v161056; RV64-NEXT: vand.vx v16, v8, a31057; RV64-NEXT: lui a3, 616811058; RV64-NEXT: vor.vv v12, v20, v121059; RV64-NEXT: vand.vx v20, v8, a41060; RV64-NEXT: lui a4, 2097151061; RV64-NEXT: vsll.vi v16, v16, 241062; RV64-NEXT: vsll.vi v20, v20, 81063; RV64-NEXT: vor.vv v16, v16, v201064; RV64-NEXT: vsll.vx v20, v8, a11065; RV64-NEXT: lui a1, 3495251066; RV64-NEXT: addi a3, a3, -2411067; RV64-NEXT: addi a4, a4, 8191068; RV64-NEXT: addi a1, a1, 13651069; RV64-NEXT: vand.vx v8, v8, a21070; RV64-NEXT: slli a2, a3, 321071; RV64-NEXT: vsll.vx v8, v8, a01072; RV64-NEXT: slli a0, a4, 321073; RV64-NEXT: add a2, a3, a21074; RV64-NEXT: slli a3, a1, 321075; RV64-NEXT: add a0, a4, a01076; RV64-NEXT: add a1, a1, a31077; RV64-NEXT: vor.vv v8, v20, v81078; RV64-NEXT: vor.vv v8, v8, v161079; RV64-NEXT: vor.vv v8, v8, v121080; RV64-NEXT: vsrl.vi v12, v8, 41081; RV64-NEXT: vand.vx v8, v8, a21082; RV64-NEXT: vand.vx v12, v12, a21083; RV64-NEXT: vsll.vi v8, v8, 41084; RV64-NEXT: vor.vv v8, v12, v81085; RV64-NEXT: vsrl.vi v12, v8, 21086; RV64-NEXT: vand.vx v8, v8, a01087; RV64-NEXT: vand.vx v12, v12, a01088; RV64-NEXT: vsll.vi v8, v8, 21089; RV64-NEXT: vor.vv v8, v12, v81090; RV64-NEXT: vsrl.vi v12, v8, 11091; RV64-NEXT: vand.vx v8, v8, a11092; RV64-NEXT: vand.vx v12, v12, a11093; RV64-NEXT: vadd.vv v8, v8, v81094; RV64-NEXT: vor.vv v8, v12, v81095; RV64-NEXT: ret1096;1097; CHECK-ZVBB-LABEL: bitreverse_nxv4i64:1098; CHECK-ZVBB: # %bb.0:1099; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1100; CHECK-ZVBB-NEXT: vbrev.v v8, v81101; CHECK-ZVBB-NEXT: ret1102 %a = call <vscale x 4 x i64> @llvm.bitreverse.nxv4i64(<vscale x 4 x i64> %va)1103 ret <vscale x 4 x i64> %a1104}1105 1106define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) {1107; RV32-LABEL: bitreverse_nxv8i64:1108; RV32: # %bb.0:1109; RV32-NEXT: addi sp, sp, -161110; RV32-NEXT: .cfi_def_cfa_offset 161111; RV32-NEXT: csrr a0, vlenb1112; RV32-NEXT: slli a0, a0, 41113; RV32-NEXT: sub sp, sp, a01114; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1115; RV32-NEXT: lui a0, 10444801116; RV32-NEXT: li a1, 561117; RV32-NEXT: li a2, 401118; RV32-NEXT: lui a3, 161119; RV32-NEXT: lui a4, 40801120; RV32-NEXT: addi a5, sp, 81121; RV32-NEXT: sw a0, 8(sp)1122; RV32-NEXT: sw zero, 12(sp)1123; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma1124; RV32-NEXT: vsrl.vx v16, v8, a11125; RV32-NEXT: vsrl.vx v24, v8, a21126; RV32-NEXT: addi a0, a3, -2561127; RV32-NEXT: vsll.vx v0, v8, a11128; RV32-NEXT: vand.vx v24, v24, a01129; RV32-NEXT: vor.vv v16, v24, v161130; RV32-NEXT: addi a1, sp, 161131; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1132; RV32-NEXT: vand.vx v16, v8, a01133; RV32-NEXT: vsll.vx v16, v16, a21134; RV32-NEXT: vor.vv v16, v0, v161135; RV32-NEXT: csrr a0, vlenb1136; RV32-NEXT: slli a0, a0, 31137; RV32-NEXT: add a0, sp, a01138; RV32-NEXT: addi a0, a0, 161139; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1140; RV32-NEXT: vlse64.v v0, (a5), zero1141; RV32-NEXT: vsrl.vi v16, v8, 241142; RV32-NEXT: vand.vx v16, v16, a41143; RV32-NEXT: vsrl.vi v24, v8, 81144; RV32-NEXT: vand.vv v24, v24, v01145; RV32-NEXT: vor.vv v16, v24, v161146; RV32-NEXT: addi a0, sp, 161147; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1148; RV32-NEXT: vor.vv v24, v16, v241149; RV32-NEXT: vand.vv v16, v8, v01150; RV32-NEXT: vand.vx v8, v8, a41151; RV32-NEXT: vsll.vi v8, v8, 241152; RV32-NEXT: vsll.vi v16, v16, 81153; RV32-NEXT: vor.vv v8, v8, v161154; RV32-NEXT: lui a0, 616811155; RV32-NEXT: lui a1, 2097151156; RV32-NEXT: lui a2, 3495251157; RV32-NEXT: addi a0, a0, -2411158; RV32-NEXT: addi a1, a1, 8191159; RV32-NEXT: addi a2, a2, 13651160; RV32-NEXT: csrr a3, vlenb1161; RV32-NEXT: slli a3, a3, 31162; RV32-NEXT: add a3, sp, a31163; RV32-NEXT: addi a3, a3, 161164; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1165; RV32-NEXT: vor.vv v8, v16, v81166; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma1167; RV32-NEXT: vmv.v.x v16, a01168; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma1169; RV32-NEXT: vor.vv v8, v8, v241170; RV32-NEXT: vsrl.vi v24, v8, 41171; RV32-NEXT: vand.vv v8, v8, v161172; RV32-NEXT: vand.vv v16, v24, v161173; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma1174; RV32-NEXT: vmv.v.x v24, a11175; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma1176; RV32-NEXT: vsll.vi v8, v8, 41177; RV32-NEXT: vor.vv v8, v16, v81178; RV32-NEXT: vsrl.vi v16, v8, 21179; RV32-NEXT: vand.vv v8, v8, v241180; RV32-NEXT: vand.vv v16, v16, v241181; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma1182; RV32-NEXT: vmv.v.x v24, a21183; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma1184; RV32-NEXT: vsll.vi v8, v8, 21185; RV32-NEXT: vor.vv v8, v16, v81186; RV32-NEXT: vsrl.vi v16, v8, 11187; RV32-NEXT: vand.vv v8, v8, v241188; RV32-NEXT: vand.vv v16, v16, v241189; RV32-NEXT: vadd.vv v8, v8, v81190; RV32-NEXT: vor.vv v8, v16, v81191; RV32-NEXT: csrr a0, vlenb1192; RV32-NEXT: slli a0, a0, 41193; RV32-NEXT: add sp, sp, a01194; RV32-NEXT: .cfi_def_cfa sp, 161195; RV32-NEXT: addi sp, sp, 161196; RV32-NEXT: .cfi_def_cfa_offset 01197; RV32-NEXT: ret1198;1199; RV64-LABEL: bitreverse_nxv8i64:1200; RV64: # %bb.0:1201; RV64-NEXT: li a1, 561202; RV64-NEXT: li a0, 401203; RV64-NEXT: lui a2, 161204; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma1205; RV64-NEXT: vsrl.vi v24, v8, 241206; RV64-NEXT: lui a3, 40801207; RV64-NEXT: vsrl.vx v16, v8, a11208; RV64-NEXT: vsrl.vx v0, v8, a01209; RV64-NEXT: addi a2, a2, -2561210; RV64-NEXT: vand.vx v0, v0, a21211; RV64-NEXT: vor.vv v16, v0, v161212; RV64-NEXT: vsrl.vi v0, v8, 81213; RV64-NEXT: li a4, 2551214; RV64-NEXT: vand.vx v24, v24, a31215; RV64-NEXT: slli a4, a4, 241216; RV64-NEXT: vand.vx v0, v0, a41217; RV64-NEXT: vor.vv v0, v0, v241218; RV64-NEXT: vand.vx v24, v8, a31219; RV64-NEXT: lui a3, 616811220; RV64-NEXT: vor.vv v16, v0, v161221; RV64-NEXT: vand.vx v0, v8, a41222; RV64-NEXT: lui a4, 2097151223; RV64-NEXT: vsll.vi v24, v24, 241224; RV64-NEXT: vsll.vi v0, v0, 81225; RV64-NEXT: vor.vv v24, v24, v01226; RV64-NEXT: vsll.vx v0, v8, a11227; RV64-NEXT: lui a1, 3495251228; RV64-NEXT: addi a3, a3, -2411229; RV64-NEXT: addi a4, a4, 8191230; RV64-NEXT: addi a1, a1, 13651231; RV64-NEXT: vand.vx v8, v8, a21232; RV64-NEXT: slli a2, a3, 321233; RV64-NEXT: vsll.vx v8, v8, a01234; RV64-NEXT: slli a0, a4, 321235; RV64-NEXT: add a2, a3, a21236; RV64-NEXT: slli a3, a1, 321237; RV64-NEXT: add a0, a4, a01238; RV64-NEXT: add a1, a1, a31239; RV64-NEXT: vor.vv v8, v0, v81240; RV64-NEXT: vor.vv v8, v8, v241241; RV64-NEXT: vor.vv v8, v8, v161242; RV64-NEXT: vsrl.vi v16, v8, 41243; RV64-NEXT: vand.vx v8, v8, a21244; RV64-NEXT: vand.vx v16, v16, a21245; RV64-NEXT: vsll.vi v8, v8, 41246; RV64-NEXT: vor.vv v8, v16, v81247; RV64-NEXT: vsrl.vi v16, v8, 21248; RV64-NEXT: vand.vx v8, v8, a01249; RV64-NEXT: vand.vx v16, v16, a01250; RV64-NEXT: vsll.vi v8, v8, 21251; RV64-NEXT: vor.vv v8, v16, v81252; RV64-NEXT: vsrl.vi v16, v8, 11253; RV64-NEXT: vand.vx v8, v8, a11254; RV64-NEXT: vand.vx v16, v16, a11255; RV64-NEXT: vadd.vv v8, v8, v81256; RV64-NEXT: vor.vv v8, v16, v81257; RV64-NEXT: ret1258;1259; CHECK-ZVBB-LABEL: bitreverse_nxv8i64:1260; CHECK-ZVBB: # %bb.0:1261; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1262; CHECK-ZVBB-NEXT: vbrev.v v8, v81263; CHECK-ZVBB-NEXT: ret1264 %a = call <vscale x 8 x i64> @llvm.bitreverse.nxv8i64(<vscale x 8 x i64> %va)1265 ret <vscale x 8 x i64> %a1266}1267