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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB8; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB10 11define <vscale x 1 x i8> @vp_bitreverse_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vp_bitreverse_nxv1i8:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vand.vi v9, v8, 15, v0.t16; CHECK-NEXT: li a0, 5117; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t18; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t19; CHECK-NEXT: vand.vi v8, v8, 15, v0.t20; CHECK-NEXT: vor.vv v8, v8, v9, v0.t21; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t22; CHECK-NEXT: vand.vx v9, v9, a0, v0.t23; CHECK-NEXT: vand.vx v8, v8, a0, v0.t24; CHECK-NEXT: li a0, 8525; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t26; CHECK-NEXT: vor.vv v8, v9, v8, v0.t27; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t28; CHECK-NEXT: vand.vx v9, v9, a0, v0.t29; CHECK-NEXT: vand.vx v8, v8, a0, v0.t30; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t31; CHECK-NEXT: vor.vv v8, v9, v8, v0.t32; CHECK-NEXT: ret33;34; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i8:35; CHECK-ZVBB: # %bb.0:36; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma37; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t38; CHECK-ZVBB-NEXT: ret39 %v = call <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)40 ret <vscale x 1 x i8> %v41}42 43define <vscale x 1 x i8> @vp_bitreverse_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {44; CHECK-LABEL: vp_bitreverse_nxv1i8_unmasked:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma47; CHECK-NEXT: vand.vi v9, v8, 1548; CHECK-NEXT: vsrl.vi v8, v8, 449; CHECK-NEXT: li a0, 5150; CHECK-NEXT: vsll.vi v9, v9, 451; CHECK-NEXT: vand.vi v8, v8, 1552; CHECK-NEXT: vor.vv v8, v8, v953; CHECK-NEXT: vsrl.vi v9, v8, 254; CHECK-NEXT: vand.vx v8, v8, a055; CHECK-NEXT: vand.vx v9, v9, a056; CHECK-NEXT: li a0, 8557; CHECK-NEXT: vsll.vi v8, v8, 258; CHECK-NEXT: vor.vv v8, v9, v859; CHECK-NEXT: vsrl.vi v9, v8, 160; CHECK-NEXT: vand.vx v8, v8, a061; CHECK-NEXT: vand.vx v9, v9, a062; CHECK-NEXT: vadd.vv v8, v8, v863; CHECK-NEXT: vor.vv v8, v9, v864; CHECK-NEXT: ret65;66; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i8_unmasked:67; CHECK-ZVBB: # %bb.0:68; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma69; CHECK-ZVBB-NEXT: vbrev.v v8, v870; CHECK-ZVBB-NEXT: ret71 %v = call <vscale x 1 x i8> @llvm.vp.bitreverse.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)72 ret <vscale x 1 x i8> %v73}74 75define <vscale x 2 x i8> @vp_bitreverse_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vp_bitreverse_nxv2i8:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma79; CHECK-NEXT: vand.vi v9, v8, 15, v0.t80; CHECK-NEXT: li a0, 5181; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t82; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t83; CHECK-NEXT: vand.vi v8, v8, 15, v0.t84; CHECK-NEXT: vor.vv v8, v8, v9, v0.t85; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t86; CHECK-NEXT: vand.vx v9, v9, a0, v0.t87; CHECK-NEXT: vand.vx v8, v8, a0, v0.t88; CHECK-NEXT: li a0, 8589; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t90; CHECK-NEXT: vor.vv v8, v9, v8, v0.t91; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t92; CHECK-NEXT: vand.vx v9, v9, a0, v0.t93; CHECK-NEXT: vand.vx v8, v8, a0, v0.t94; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t95; CHECK-NEXT: vor.vv v8, v9, v8, v0.t96; CHECK-NEXT: ret97;98; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i8:99; CHECK-ZVBB: # %bb.0:100; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma101; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t102; CHECK-ZVBB-NEXT: ret103 %v = call <vscale x 2 x i8> @llvm.vp.bitreverse.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 %evl)104 ret <vscale x 2 x i8> %v105}106 107define <vscale x 2 x i8> @vp_bitreverse_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {108; CHECK-LABEL: vp_bitreverse_nxv2i8_unmasked:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma111; CHECK-NEXT: vand.vi v9, v8, 15112; CHECK-NEXT: vsrl.vi v8, v8, 4113; CHECK-NEXT: li a0, 51114; CHECK-NEXT: vsll.vi v9, v9, 4115; CHECK-NEXT: vand.vi v8, v8, 15116; CHECK-NEXT: vor.vv v8, v8, v9117; CHECK-NEXT: vsrl.vi v9, v8, 2118; CHECK-NEXT: vand.vx v8, v8, a0119; CHECK-NEXT: vand.vx v9, v9, a0120; CHECK-NEXT: li a0, 85121; CHECK-NEXT: vsll.vi v8, v8, 2122; CHECK-NEXT: vor.vv v8, v9, v8123; CHECK-NEXT: vsrl.vi v9, v8, 1124; CHECK-NEXT: vand.vx v8, v8, a0125; CHECK-NEXT: vand.vx v9, v9, a0126; CHECK-NEXT: vadd.vv v8, v8, v8127; CHECK-NEXT: vor.vv v8, v9, v8128; CHECK-NEXT: ret129;130; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i8_unmasked:131; CHECK-ZVBB: # %bb.0:132; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma133; CHECK-ZVBB-NEXT: vbrev.v v8, v8134; CHECK-ZVBB-NEXT: ret135 %v = call <vscale x 2 x i8> @llvm.vp.bitreverse.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)136 ret <vscale x 2 x i8> %v137}138 139define <vscale x 4 x i8> @vp_bitreverse_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vp_bitreverse_nxv4i8:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma143; CHECK-NEXT: vand.vi v9, v8, 15, v0.t144; CHECK-NEXT: li a0, 51145; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t146; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t147; CHECK-NEXT: vand.vi v8, v8, 15, v0.t148; CHECK-NEXT: vor.vv v8, v8, v9, v0.t149; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t150; CHECK-NEXT: vand.vx v9, v9, a0, v0.t151; CHECK-NEXT: vand.vx v8, v8, a0, v0.t152; CHECK-NEXT: li a0, 85153; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t154; CHECK-NEXT: vor.vv v8, v9, v8, v0.t155; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t156; CHECK-NEXT: vand.vx v9, v9, a0, v0.t157; CHECK-NEXT: vand.vx v8, v8, a0, v0.t158; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t159; CHECK-NEXT: vor.vv v8, v9, v8, v0.t160; CHECK-NEXT: ret161;162; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i8:163; CHECK-ZVBB: # %bb.0:164; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma165; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t166; CHECK-ZVBB-NEXT: ret167 %v = call <vscale x 4 x i8> @llvm.vp.bitreverse.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 %evl)168 ret <vscale x 4 x i8> %v169}170 171define <vscale x 4 x i8> @vp_bitreverse_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {172; CHECK-LABEL: vp_bitreverse_nxv4i8_unmasked:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma175; CHECK-NEXT: vand.vi v9, v8, 15176; CHECK-NEXT: vsrl.vi v8, v8, 4177; CHECK-NEXT: li a0, 51178; CHECK-NEXT: vsll.vi v9, v9, 4179; CHECK-NEXT: vand.vi v8, v8, 15180; CHECK-NEXT: vor.vv v8, v8, v9181; CHECK-NEXT: vsrl.vi v9, v8, 2182; CHECK-NEXT: vand.vx v8, v8, a0183; CHECK-NEXT: vand.vx v9, v9, a0184; CHECK-NEXT: li a0, 85185; CHECK-NEXT: vsll.vi v8, v8, 2186; CHECK-NEXT: vor.vv v8, v9, v8187; CHECK-NEXT: vsrl.vi v9, v8, 1188; CHECK-NEXT: vand.vx v8, v8, a0189; CHECK-NEXT: vand.vx v9, v9, a0190; CHECK-NEXT: vadd.vv v8, v8, v8191; CHECK-NEXT: vor.vv v8, v9, v8192; CHECK-NEXT: ret193;194; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i8_unmasked:195; CHECK-ZVBB: # %bb.0:196; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma197; CHECK-ZVBB-NEXT: vbrev.v v8, v8198; CHECK-ZVBB-NEXT: ret199 %v = call <vscale x 4 x i8> @llvm.vp.bitreverse.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)200 ret <vscale x 4 x i8> %v201}202 203define <vscale x 8 x i8> @vp_bitreverse_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {204; CHECK-LABEL: vp_bitreverse_nxv8i8:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma207; CHECK-NEXT: vand.vi v9, v8, 15, v0.t208; CHECK-NEXT: li a0, 51209; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t210; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t211; CHECK-NEXT: vand.vi v8, v8, 15, v0.t212; CHECK-NEXT: vor.vv v8, v8, v9, v0.t213; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t214; CHECK-NEXT: vand.vx v9, v9, a0, v0.t215; CHECK-NEXT: vand.vx v8, v8, a0, v0.t216; CHECK-NEXT: li a0, 85217; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t218; CHECK-NEXT: vor.vv v8, v9, v8, v0.t219; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t220; CHECK-NEXT: vand.vx v9, v9, a0, v0.t221; CHECK-NEXT: vand.vx v8, v8, a0, v0.t222; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t223; CHECK-NEXT: vor.vv v8, v9, v8, v0.t224; CHECK-NEXT: ret225;226; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i8:227; CHECK-ZVBB: # %bb.0:228; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma229; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t230; CHECK-ZVBB-NEXT: ret231 %v = call <vscale x 8 x i8> @llvm.vp.bitreverse.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 %evl)232 ret <vscale x 8 x i8> %v233}234 235define <vscale x 8 x i8> @vp_bitreverse_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {236; CHECK-LABEL: vp_bitreverse_nxv8i8_unmasked:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma239; CHECK-NEXT: vand.vi v9, v8, 15240; CHECK-NEXT: vsrl.vi v8, v8, 4241; CHECK-NEXT: li a0, 51242; CHECK-NEXT: vsll.vi v9, v9, 4243; CHECK-NEXT: vand.vi v8, v8, 15244; CHECK-NEXT: vor.vv v8, v8, v9245; CHECK-NEXT: vsrl.vi v9, v8, 2246; CHECK-NEXT: vand.vx v8, v8, a0247; CHECK-NEXT: vand.vx v9, v9, a0248; CHECK-NEXT: li a0, 85249; CHECK-NEXT: vsll.vi v8, v8, 2250; CHECK-NEXT: vor.vv v8, v9, v8251; CHECK-NEXT: vsrl.vi v9, v8, 1252; CHECK-NEXT: vand.vx v8, v8, a0253; CHECK-NEXT: vand.vx v9, v9, a0254; CHECK-NEXT: vadd.vv v8, v8, v8255; CHECK-NEXT: vor.vv v8, v9, v8256; CHECK-NEXT: ret257;258; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i8_unmasked:259; CHECK-ZVBB: # %bb.0:260; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma261; CHECK-ZVBB-NEXT: vbrev.v v8, v8262; CHECK-ZVBB-NEXT: ret263 %v = call <vscale x 8 x i8> @llvm.vp.bitreverse.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)264 ret <vscale x 8 x i8> %v265}266 267define <vscale x 16 x i8> @vp_bitreverse_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {268; CHECK-LABEL: vp_bitreverse_nxv16i8:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma271; CHECK-NEXT: vand.vi v10, v8, 15, v0.t272; CHECK-NEXT: li a0, 51273; CHECK-NEXT: vsll.vi v10, v10, 4, v0.t274; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t275; CHECK-NEXT: vand.vi v8, v8, 15, v0.t276; CHECK-NEXT: vor.vv v8, v8, v10, v0.t277; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t278; CHECK-NEXT: vand.vx v10, v10, a0, v0.t279; CHECK-NEXT: vand.vx v8, v8, a0, v0.t280; CHECK-NEXT: li a0, 85281; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t282; CHECK-NEXT: vor.vv v8, v10, v8, v0.t283; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t284; CHECK-NEXT: vand.vx v10, v10, a0, v0.t285; CHECK-NEXT: vand.vx v8, v8, a0, v0.t286; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t287; CHECK-NEXT: vor.vv v8, v10, v8, v0.t288; CHECK-NEXT: ret289;290; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i8:291; CHECK-ZVBB: # %bb.0:292; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma293; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t294; CHECK-ZVBB-NEXT: ret295 %v = call <vscale x 16 x i8> @llvm.vp.bitreverse.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 %evl)296 ret <vscale x 16 x i8> %v297}298 299define <vscale x 16 x i8> @vp_bitreverse_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {300; CHECK-LABEL: vp_bitreverse_nxv16i8_unmasked:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma303; CHECK-NEXT: vand.vi v10, v8, 15304; CHECK-NEXT: vsrl.vi v8, v8, 4305; CHECK-NEXT: li a0, 51306; CHECK-NEXT: vsll.vi v10, v10, 4307; CHECK-NEXT: vand.vi v8, v8, 15308; CHECK-NEXT: vor.vv v8, v8, v10309; CHECK-NEXT: vsrl.vi v10, v8, 2310; CHECK-NEXT: vand.vx v8, v8, a0311; CHECK-NEXT: vand.vx v10, v10, a0312; CHECK-NEXT: li a0, 85313; CHECK-NEXT: vsll.vi v8, v8, 2314; CHECK-NEXT: vor.vv v8, v10, v8315; CHECK-NEXT: vsrl.vi v10, v8, 1316; CHECK-NEXT: vand.vx v8, v8, a0317; CHECK-NEXT: vand.vx v10, v10, a0318; CHECK-NEXT: vadd.vv v8, v8, v8319; CHECK-NEXT: vor.vv v8, v10, v8320; CHECK-NEXT: ret321;322; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i8_unmasked:323; CHECK-ZVBB: # %bb.0:324; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma325; CHECK-ZVBB-NEXT: vbrev.v v8, v8326; CHECK-ZVBB-NEXT: ret327 %v = call <vscale x 16 x i8> @llvm.vp.bitreverse.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)328 ret <vscale x 16 x i8> %v329}330 331define <vscale x 32 x i8> @vp_bitreverse_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vp_bitreverse_nxv32i8:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma335; CHECK-NEXT: vand.vi v12, v8, 15, v0.t336; CHECK-NEXT: li a0, 51337; CHECK-NEXT: vsll.vi v12, v12, 4, v0.t338; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t339; CHECK-NEXT: vand.vi v8, v8, 15, v0.t340; CHECK-NEXT: vor.vv v8, v8, v12, v0.t341; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t342; CHECK-NEXT: vand.vx v12, v12, a0, v0.t343; CHECK-NEXT: vand.vx v8, v8, a0, v0.t344; CHECK-NEXT: li a0, 85345; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t346; CHECK-NEXT: vor.vv v8, v12, v8, v0.t347; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t348; CHECK-NEXT: vand.vx v12, v12, a0, v0.t349; CHECK-NEXT: vand.vx v8, v8, a0, v0.t350; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t351; CHECK-NEXT: vor.vv v8, v12, v8, v0.t352; CHECK-NEXT: ret353;354; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i8:355; CHECK-ZVBB: # %bb.0:356; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma357; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t358; CHECK-ZVBB-NEXT: ret359 %v = call <vscale x 32 x i8> @llvm.vp.bitreverse.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 %evl)360 ret <vscale x 32 x i8> %v361}362 363define <vscale x 32 x i8> @vp_bitreverse_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {364; CHECK-LABEL: vp_bitreverse_nxv32i8_unmasked:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma367; CHECK-NEXT: vand.vi v12, v8, 15368; CHECK-NEXT: vsrl.vi v8, v8, 4369; CHECK-NEXT: li a0, 51370; CHECK-NEXT: vsll.vi v12, v12, 4371; CHECK-NEXT: vand.vi v8, v8, 15372; CHECK-NEXT: vor.vv v8, v8, v12373; CHECK-NEXT: vsrl.vi v12, v8, 2374; CHECK-NEXT: vand.vx v8, v8, a0375; CHECK-NEXT: vand.vx v12, v12, a0376; CHECK-NEXT: li a0, 85377; CHECK-NEXT: vsll.vi v8, v8, 2378; CHECK-NEXT: vor.vv v8, v12, v8379; CHECK-NEXT: vsrl.vi v12, v8, 1380; CHECK-NEXT: vand.vx v8, v8, a0381; CHECK-NEXT: vand.vx v12, v12, a0382; CHECK-NEXT: vadd.vv v8, v8, v8383; CHECK-NEXT: vor.vv v8, v12, v8384; CHECK-NEXT: ret385;386; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i8_unmasked:387; CHECK-ZVBB: # %bb.0:388; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma389; CHECK-ZVBB-NEXT: vbrev.v v8, v8390; CHECK-ZVBB-NEXT: ret391 %v = call <vscale x 32 x i8> @llvm.vp.bitreverse.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)392 ret <vscale x 32 x i8> %v393}394 395define <vscale x 64 x i8> @vp_bitreverse_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {396; CHECK-LABEL: vp_bitreverse_nxv64i8:397; CHECK: # %bb.0:398; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma399; CHECK-NEXT: vand.vi v16, v8, 15, v0.t400; CHECK-NEXT: li a0, 51401; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t402; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t403; CHECK-NEXT: vand.vi v8, v8, 15, v0.t404; CHECK-NEXT: vor.vv v16, v8, v16, v0.t405; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t406; CHECK-NEXT: vand.vx v8, v8, a0, v0.t407; CHECK-NEXT: vand.vx v16, v16, a0, v0.t408; CHECK-NEXT: li a0, 85409; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t410; CHECK-NEXT: vor.vv v8, v8, v16, v0.t411; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t412; CHECK-NEXT: vand.vx v16, v16, a0, v0.t413; CHECK-NEXT: vand.vx v8, v8, a0, v0.t414; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t415; CHECK-NEXT: vor.vv v8, v16, v8, v0.t416; CHECK-NEXT: ret417;418; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i8:419; CHECK-ZVBB: # %bb.0:420; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma421; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t422; CHECK-ZVBB-NEXT: ret423 %v = call <vscale x 64 x i8> @llvm.vp.bitreverse.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 %evl)424 ret <vscale x 64 x i8> %v425}426 427define <vscale x 64 x i8> @vp_bitreverse_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {428; CHECK-LABEL: vp_bitreverse_nxv64i8_unmasked:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma431; CHECK-NEXT: vand.vi v16, v8, 15432; CHECK-NEXT: vsrl.vi v8, v8, 4433; CHECK-NEXT: li a0, 51434; CHECK-NEXT: vsll.vi v16, v16, 4435; CHECK-NEXT: vand.vi v8, v8, 15436; CHECK-NEXT: vor.vv v8, v8, v16437; CHECK-NEXT: vsrl.vi v16, v8, 2438; CHECK-NEXT: vand.vx v8, v8, a0439; CHECK-NEXT: vand.vx v16, v16, a0440; CHECK-NEXT: li a0, 85441; CHECK-NEXT: vsll.vi v8, v8, 2442; CHECK-NEXT: vor.vv v8, v16, v8443; CHECK-NEXT: vsrl.vi v16, v8, 1444; CHECK-NEXT: vand.vx v8, v8, a0445; CHECK-NEXT: vand.vx v16, v16, a0446; CHECK-NEXT: vadd.vv v8, v8, v8447; CHECK-NEXT: vor.vv v8, v16, v8448; CHECK-NEXT: ret449;450; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i8_unmasked:451; CHECK-ZVBB: # %bb.0:452; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma453; CHECK-ZVBB-NEXT: vbrev.v v8, v8454; CHECK-ZVBB-NEXT: ret455 %v = call <vscale x 64 x i8> @llvm.vp.bitreverse.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)456 ret <vscale x 64 x i8> %v457}458 459define <vscale x 1 x i16> @vp_bitreverse_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: vp_bitreverse_nxv1i16:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma463; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t464; CHECK-NEXT: lui a0, 1465; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t466; CHECK-NEXT: addi a0, a0, -241467; CHECK-NEXT: vor.vv v8, v8, v9, v0.t468; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t469; CHECK-NEXT: vand.vx v9, v9, a0, v0.t470; CHECK-NEXT: vand.vx v8, v8, a0, v0.t471; CHECK-NEXT: lui a0, 3472; CHECK-NEXT: addi a0, a0, 819473; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t474; CHECK-NEXT: vor.vv v8, v9, v8, v0.t475; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t476; CHECK-NEXT: vand.vx v9, v9, a0, v0.t477; CHECK-NEXT: vand.vx v8, v8, a0, v0.t478; CHECK-NEXT: lui a0, 5479; CHECK-NEXT: addi a0, a0, 1365480; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t481; CHECK-NEXT: vor.vv v8, v9, v8, v0.t482; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t483; CHECK-NEXT: vand.vx v9, v9, a0, v0.t484; CHECK-NEXT: vand.vx v8, v8, a0, v0.t485; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t486; CHECK-NEXT: vor.vv v8, v9, v8, v0.t487; CHECK-NEXT: ret488;489; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i16:490; CHECK-ZVBB: # %bb.0:491; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma492; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t493; CHECK-ZVBB-NEXT: ret494 %v = call <vscale x 1 x i16> @llvm.vp.bitreverse.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)495 ret <vscale x 1 x i16> %v496}497 498define <vscale x 1 x i16> @vp_bitreverse_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {499; CHECK-LABEL: vp_bitreverse_nxv1i16_unmasked:500; CHECK: # %bb.0:501; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma502; CHECK-NEXT: vsrl.vi v9, v8, 8503; CHECK-NEXT: vsll.vi v8, v8, 8504; CHECK-NEXT: lui a0, 1505; CHECK-NEXT: vor.vv v8, v8, v9506; CHECK-NEXT: addi a0, a0, -241507; CHECK-NEXT: vsrl.vi v9, v8, 4508; CHECK-NEXT: vand.vx v8, v8, a0509; CHECK-NEXT: vand.vx v9, v9, a0510; CHECK-NEXT: lui a0, 3511; CHECK-NEXT: addi a0, a0, 819512; CHECK-NEXT: vsll.vi v8, v8, 4513; CHECK-NEXT: vor.vv v8, v9, v8514; CHECK-NEXT: vsrl.vi v9, v8, 2515; CHECK-NEXT: vand.vx v8, v8, a0516; CHECK-NEXT: vand.vx v9, v9, a0517; CHECK-NEXT: lui a0, 5518; CHECK-NEXT: addi a0, a0, 1365519; CHECK-NEXT: vsll.vi v8, v8, 2520; CHECK-NEXT: vor.vv v8, v9, v8521; CHECK-NEXT: vsrl.vi v9, v8, 1522; CHECK-NEXT: vand.vx v8, v8, a0523; CHECK-NEXT: vand.vx v9, v9, a0524; CHECK-NEXT: vadd.vv v8, v8, v8525; CHECK-NEXT: vor.vv v8, v9, v8526; CHECK-NEXT: ret527;528; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i16_unmasked:529; CHECK-ZVBB: # %bb.0:530; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma531; CHECK-ZVBB-NEXT: vbrev.v v8, v8532; CHECK-ZVBB-NEXT: ret533 %v = call <vscale x 1 x i16> @llvm.vp.bitreverse.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)534 ret <vscale x 1 x i16> %v535}536 537define <vscale x 2 x i16> @vp_bitreverse_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {538; CHECK-LABEL: vp_bitreverse_nxv2i16:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma541; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t542; CHECK-NEXT: lui a0, 1543; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t544; CHECK-NEXT: addi a0, a0, -241545; CHECK-NEXT: vor.vv v8, v8, v9, v0.t546; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t547; CHECK-NEXT: vand.vx v9, v9, a0, v0.t548; CHECK-NEXT: vand.vx v8, v8, a0, v0.t549; CHECK-NEXT: lui a0, 3550; CHECK-NEXT: addi a0, a0, 819551; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t552; CHECK-NEXT: vor.vv v8, v9, v8, v0.t553; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t554; CHECK-NEXT: vand.vx v9, v9, a0, v0.t555; CHECK-NEXT: vand.vx v8, v8, a0, v0.t556; CHECK-NEXT: lui a0, 5557; CHECK-NEXT: addi a0, a0, 1365558; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t559; CHECK-NEXT: vor.vv v8, v9, v8, v0.t560; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t561; CHECK-NEXT: vand.vx v9, v9, a0, v0.t562; CHECK-NEXT: vand.vx v8, v8, a0, v0.t563; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t564; CHECK-NEXT: vor.vv v8, v9, v8, v0.t565; CHECK-NEXT: ret566;567; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i16:568; CHECK-ZVBB: # %bb.0:569; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma570; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t571; CHECK-ZVBB-NEXT: ret572 %v = call <vscale x 2 x i16> @llvm.vp.bitreverse.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)573 ret <vscale x 2 x i16> %v574}575 576define <vscale x 2 x i16> @vp_bitreverse_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {577; CHECK-LABEL: vp_bitreverse_nxv2i16_unmasked:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma580; CHECK-NEXT: vsrl.vi v9, v8, 8581; CHECK-NEXT: vsll.vi v8, v8, 8582; CHECK-NEXT: lui a0, 1583; CHECK-NEXT: vor.vv v8, v8, v9584; CHECK-NEXT: addi a0, a0, -241585; CHECK-NEXT: vsrl.vi v9, v8, 4586; CHECK-NEXT: vand.vx v8, v8, a0587; CHECK-NEXT: vand.vx v9, v9, a0588; CHECK-NEXT: lui a0, 3589; CHECK-NEXT: addi a0, a0, 819590; CHECK-NEXT: vsll.vi v8, v8, 4591; CHECK-NEXT: vor.vv v8, v9, v8592; CHECK-NEXT: vsrl.vi v9, v8, 2593; CHECK-NEXT: vand.vx v8, v8, a0594; CHECK-NEXT: vand.vx v9, v9, a0595; CHECK-NEXT: lui a0, 5596; CHECK-NEXT: addi a0, a0, 1365597; CHECK-NEXT: vsll.vi v8, v8, 2598; CHECK-NEXT: vor.vv v8, v9, v8599; CHECK-NEXT: vsrl.vi v9, v8, 1600; CHECK-NEXT: vand.vx v8, v8, a0601; CHECK-NEXT: vand.vx v9, v9, a0602; CHECK-NEXT: vadd.vv v8, v8, v8603; CHECK-NEXT: vor.vv v8, v9, v8604; CHECK-NEXT: ret605;606; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i16_unmasked:607; CHECK-ZVBB: # %bb.0:608; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma609; CHECK-ZVBB-NEXT: vbrev.v v8, v8610; CHECK-ZVBB-NEXT: ret611 %v = call <vscale x 2 x i16> @llvm.vp.bitreverse.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)612 ret <vscale x 2 x i16> %v613}614 615define <vscale x 4 x i16> @vp_bitreverse_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {616; CHECK-LABEL: vp_bitreverse_nxv4i16:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma619; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t620; CHECK-NEXT: lui a0, 1621; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t622; CHECK-NEXT: addi a0, a0, -241623; CHECK-NEXT: vor.vv v8, v8, v9, v0.t624; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t625; CHECK-NEXT: vand.vx v9, v9, a0, v0.t626; CHECK-NEXT: vand.vx v8, v8, a0, v0.t627; CHECK-NEXT: lui a0, 3628; CHECK-NEXT: addi a0, a0, 819629; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t630; CHECK-NEXT: vor.vv v8, v9, v8, v0.t631; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t632; CHECK-NEXT: vand.vx v9, v9, a0, v0.t633; CHECK-NEXT: vand.vx v8, v8, a0, v0.t634; CHECK-NEXT: lui a0, 5635; CHECK-NEXT: addi a0, a0, 1365636; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t637; CHECK-NEXT: vor.vv v8, v9, v8, v0.t638; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t639; CHECK-NEXT: vand.vx v9, v9, a0, v0.t640; CHECK-NEXT: vand.vx v8, v8, a0, v0.t641; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t642; CHECK-NEXT: vor.vv v8, v9, v8, v0.t643; CHECK-NEXT: ret644;645; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i16:646; CHECK-ZVBB: # %bb.0:647; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma648; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t649; CHECK-ZVBB-NEXT: ret650 %v = call <vscale x 4 x i16> @llvm.vp.bitreverse.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)651 ret <vscale x 4 x i16> %v652}653 654define <vscale x 4 x i16> @vp_bitreverse_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {655; CHECK-LABEL: vp_bitreverse_nxv4i16_unmasked:656; CHECK: # %bb.0:657; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma658; CHECK-NEXT: vsrl.vi v9, v8, 8659; CHECK-NEXT: vsll.vi v8, v8, 8660; CHECK-NEXT: lui a0, 1661; CHECK-NEXT: vor.vv v8, v8, v9662; CHECK-NEXT: addi a0, a0, -241663; CHECK-NEXT: vsrl.vi v9, v8, 4664; CHECK-NEXT: vand.vx v8, v8, a0665; CHECK-NEXT: vand.vx v9, v9, a0666; CHECK-NEXT: lui a0, 3667; CHECK-NEXT: addi a0, a0, 819668; CHECK-NEXT: vsll.vi v8, v8, 4669; CHECK-NEXT: vor.vv v8, v9, v8670; CHECK-NEXT: vsrl.vi v9, v8, 2671; CHECK-NEXT: vand.vx v8, v8, a0672; CHECK-NEXT: vand.vx v9, v9, a0673; CHECK-NEXT: lui a0, 5674; CHECK-NEXT: addi a0, a0, 1365675; CHECK-NEXT: vsll.vi v8, v8, 2676; CHECK-NEXT: vor.vv v8, v9, v8677; CHECK-NEXT: vsrl.vi v9, v8, 1678; CHECK-NEXT: vand.vx v8, v8, a0679; CHECK-NEXT: vand.vx v9, v9, a0680; CHECK-NEXT: vadd.vv v8, v8, v8681; CHECK-NEXT: vor.vv v8, v9, v8682; CHECK-NEXT: ret683;684; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i16_unmasked:685; CHECK-ZVBB: # %bb.0:686; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma687; CHECK-ZVBB-NEXT: vbrev.v v8, v8688; CHECK-ZVBB-NEXT: ret689 %v = call <vscale x 4 x i16> @llvm.vp.bitreverse.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)690 ret <vscale x 4 x i16> %v691}692 693define <vscale x 8 x i16> @vp_bitreverse_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {694; CHECK-LABEL: vp_bitreverse_nxv8i16:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma697; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t698; CHECK-NEXT: lui a0, 1699; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t700; CHECK-NEXT: addi a0, a0, -241701; CHECK-NEXT: vor.vv v8, v8, v10, v0.t702; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t703; CHECK-NEXT: vand.vx v10, v10, a0, v0.t704; CHECK-NEXT: vand.vx v8, v8, a0, v0.t705; CHECK-NEXT: lui a0, 3706; CHECK-NEXT: addi a0, a0, 819707; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t708; CHECK-NEXT: vor.vv v8, v10, v8, v0.t709; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t710; CHECK-NEXT: vand.vx v10, v10, a0, v0.t711; CHECK-NEXT: vand.vx v8, v8, a0, v0.t712; CHECK-NEXT: lui a0, 5713; CHECK-NEXT: addi a0, a0, 1365714; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t715; CHECK-NEXT: vor.vv v8, v10, v8, v0.t716; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t717; CHECK-NEXT: vand.vx v10, v10, a0, v0.t718; CHECK-NEXT: vand.vx v8, v8, a0, v0.t719; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t720; CHECK-NEXT: vor.vv v8, v10, v8, v0.t721; CHECK-NEXT: ret722;723; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i16:724; CHECK-ZVBB: # %bb.0:725; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma726; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t727; CHECK-ZVBB-NEXT: ret728 %v = call <vscale x 8 x i16> @llvm.vp.bitreverse.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl)729 ret <vscale x 8 x i16> %v730}731 732define <vscale x 8 x i16> @vp_bitreverse_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {733; CHECK-LABEL: vp_bitreverse_nxv8i16_unmasked:734; CHECK: # %bb.0:735; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma736; CHECK-NEXT: vsrl.vi v10, v8, 8737; CHECK-NEXT: vsll.vi v8, v8, 8738; CHECK-NEXT: lui a0, 1739; CHECK-NEXT: vor.vv v8, v8, v10740; CHECK-NEXT: addi a0, a0, -241741; CHECK-NEXT: vsrl.vi v10, v8, 4742; CHECK-NEXT: vand.vx v8, v8, a0743; CHECK-NEXT: vand.vx v10, v10, a0744; CHECK-NEXT: lui a0, 3745; CHECK-NEXT: addi a0, a0, 819746; CHECK-NEXT: vsll.vi v8, v8, 4747; CHECK-NEXT: vor.vv v8, v10, v8748; CHECK-NEXT: vsrl.vi v10, v8, 2749; CHECK-NEXT: vand.vx v8, v8, a0750; CHECK-NEXT: vand.vx v10, v10, a0751; CHECK-NEXT: lui a0, 5752; CHECK-NEXT: addi a0, a0, 1365753; CHECK-NEXT: vsll.vi v8, v8, 2754; CHECK-NEXT: vor.vv v8, v10, v8755; CHECK-NEXT: vsrl.vi v10, v8, 1756; CHECK-NEXT: vand.vx v8, v8, a0757; CHECK-NEXT: vand.vx v10, v10, a0758; CHECK-NEXT: vadd.vv v8, v8, v8759; CHECK-NEXT: vor.vv v8, v10, v8760; CHECK-NEXT: ret761;762; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i16_unmasked:763; CHECK-ZVBB: # %bb.0:764; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma765; CHECK-ZVBB-NEXT: vbrev.v v8, v8766; CHECK-ZVBB-NEXT: ret767 %v = call <vscale x 8 x i16> @llvm.vp.bitreverse.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)768 ret <vscale x 8 x i16> %v769}770 771define <vscale x 16 x i16> @vp_bitreverse_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {772; CHECK-LABEL: vp_bitreverse_nxv16i16:773; CHECK: # %bb.0:774; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma775; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t776; CHECK-NEXT: lui a0, 1777; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t778; CHECK-NEXT: addi a0, a0, -241779; CHECK-NEXT: vor.vv v8, v8, v12, v0.t780; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t781; CHECK-NEXT: vand.vx v12, v12, a0, v0.t782; CHECK-NEXT: vand.vx v8, v8, a0, v0.t783; CHECK-NEXT: lui a0, 3784; CHECK-NEXT: addi a0, a0, 819785; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t786; CHECK-NEXT: vor.vv v8, v12, v8, v0.t787; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t788; CHECK-NEXT: vand.vx v12, v12, a0, v0.t789; CHECK-NEXT: vand.vx v8, v8, a0, v0.t790; CHECK-NEXT: lui a0, 5791; CHECK-NEXT: addi a0, a0, 1365792; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t793; CHECK-NEXT: vor.vv v8, v12, v8, v0.t794; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t795; CHECK-NEXT: vand.vx v12, v12, a0, v0.t796; CHECK-NEXT: vand.vx v8, v8, a0, v0.t797; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t798; CHECK-NEXT: vor.vv v8, v12, v8, v0.t799; CHECK-NEXT: ret800;801; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i16:802; CHECK-ZVBB: # %bb.0:803; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma804; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t805; CHECK-ZVBB-NEXT: ret806 %v = call <vscale x 16 x i16> @llvm.vp.bitreverse.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl)807 ret <vscale x 16 x i16> %v808}809 810define <vscale x 16 x i16> @vp_bitreverse_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {811; CHECK-LABEL: vp_bitreverse_nxv16i16_unmasked:812; CHECK: # %bb.0:813; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma814; CHECK-NEXT: vsrl.vi v12, v8, 8815; CHECK-NEXT: vsll.vi v8, v8, 8816; CHECK-NEXT: lui a0, 1817; CHECK-NEXT: vor.vv v8, v8, v12818; CHECK-NEXT: addi a0, a0, -241819; CHECK-NEXT: vsrl.vi v12, v8, 4820; CHECK-NEXT: vand.vx v8, v8, a0821; CHECK-NEXT: vand.vx v12, v12, a0822; CHECK-NEXT: lui a0, 3823; CHECK-NEXT: addi a0, a0, 819824; CHECK-NEXT: vsll.vi v8, v8, 4825; CHECK-NEXT: vor.vv v8, v12, v8826; CHECK-NEXT: vsrl.vi v12, v8, 2827; CHECK-NEXT: vand.vx v8, v8, a0828; CHECK-NEXT: vand.vx v12, v12, a0829; CHECK-NEXT: lui a0, 5830; CHECK-NEXT: addi a0, a0, 1365831; CHECK-NEXT: vsll.vi v8, v8, 2832; CHECK-NEXT: vor.vv v8, v12, v8833; CHECK-NEXT: vsrl.vi v12, v8, 1834; CHECK-NEXT: vand.vx v8, v8, a0835; CHECK-NEXT: vand.vx v12, v12, a0836; CHECK-NEXT: vadd.vv v8, v8, v8837; CHECK-NEXT: vor.vv v8, v12, v8838; CHECK-NEXT: ret839;840; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i16_unmasked:841; CHECK-ZVBB: # %bb.0:842; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma843; CHECK-ZVBB-NEXT: vbrev.v v8, v8844; CHECK-ZVBB-NEXT: ret845 %v = call <vscale x 16 x i16> @llvm.vp.bitreverse.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)846 ret <vscale x 16 x i16> %v847}848 849define <vscale x 32 x i16> @vp_bitreverse_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {850; CHECK-LABEL: vp_bitreverse_nxv32i16:851; CHECK: # %bb.0:852; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma853; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t854; CHECK-NEXT: lui a0, 1855; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t856; CHECK-NEXT: addi a0, a0, -241857; CHECK-NEXT: vor.vv v16, v8, v16, v0.t858; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t859; CHECK-NEXT: vand.vx v8, v8, a0, v0.t860; CHECK-NEXT: vand.vx v16, v16, a0, v0.t861; CHECK-NEXT: lui a0, 3862; CHECK-NEXT: addi a0, a0, 819863; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t864; CHECK-NEXT: vor.vv v16, v8, v16, v0.t865; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t866; CHECK-NEXT: vand.vx v8, v8, a0, v0.t867; CHECK-NEXT: vand.vx v16, v16, a0, v0.t868; CHECK-NEXT: lui a0, 5869; CHECK-NEXT: addi a0, a0, 1365870; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t871; CHECK-NEXT: vor.vv v8, v8, v16, v0.t872; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t873; CHECK-NEXT: vand.vx v16, v16, a0, v0.t874; CHECK-NEXT: vand.vx v8, v8, a0, v0.t875; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t876; CHECK-NEXT: vor.vv v8, v16, v8, v0.t877; CHECK-NEXT: ret878;879; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i16:880; CHECK-ZVBB: # %bb.0:881; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma882; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t883; CHECK-ZVBB-NEXT: ret884 %v = call <vscale x 32 x i16> @llvm.vp.bitreverse.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl)885 ret <vscale x 32 x i16> %v886}887 888define <vscale x 32 x i16> @vp_bitreverse_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {889; CHECK-LABEL: vp_bitreverse_nxv32i16_unmasked:890; CHECK: # %bb.0:891; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma892; CHECK-NEXT: vsrl.vi v16, v8, 8893; CHECK-NEXT: vsll.vi v8, v8, 8894; CHECK-NEXT: lui a0, 1895; CHECK-NEXT: vor.vv v8, v8, v16896; CHECK-NEXT: addi a0, a0, -241897; CHECK-NEXT: vsrl.vi v16, v8, 4898; CHECK-NEXT: vand.vx v8, v8, a0899; CHECK-NEXT: vand.vx v16, v16, a0900; CHECK-NEXT: lui a0, 3901; CHECK-NEXT: addi a0, a0, 819902; CHECK-NEXT: vsll.vi v8, v8, 4903; CHECK-NEXT: vor.vv v8, v16, v8904; CHECK-NEXT: vsrl.vi v16, v8, 2905; CHECK-NEXT: vand.vx v8, v8, a0906; CHECK-NEXT: vand.vx v16, v16, a0907; CHECK-NEXT: lui a0, 5908; CHECK-NEXT: addi a0, a0, 1365909; CHECK-NEXT: vsll.vi v8, v8, 2910; CHECK-NEXT: vor.vv v8, v16, v8911; CHECK-NEXT: vsrl.vi v16, v8, 1912; CHECK-NEXT: vand.vx v8, v8, a0913; CHECK-NEXT: vand.vx v16, v16, a0914; CHECK-NEXT: vadd.vv v8, v8, v8915; CHECK-NEXT: vor.vv v8, v16, v8916; CHECK-NEXT: ret917;918; CHECK-ZVBB-LABEL: vp_bitreverse_nxv32i16_unmasked:919; CHECK-ZVBB: # %bb.0:920; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma921; CHECK-ZVBB-NEXT: vbrev.v v8, v8922; CHECK-ZVBB-NEXT: ret923 %v = call <vscale x 32 x i16> @llvm.vp.bitreverse.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)924 ret <vscale x 32 x i16> %v925}926 927define <vscale x 1 x i32> @vp_bitreverse_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {928; CHECK-LABEL: vp_bitreverse_nxv1i32:929; CHECK: # %bb.0:930; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma931; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t932; CHECK-NEXT: lui a0, 16933; CHECK-NEXT: addi a0, a0, -256934; CHECK-NEXT: vand.vx v9, v9, a0, v0.t935; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t936; CHECK-NEXT: vor.vv v9, v9, v10, v0.t937; CHECK-NEXT: vand.vx v10, v8, a0, v0.t938; CHECK-NEXT: lui a0, 61681939; CHECK-NEXT: addi a0, a0, -241940; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t941; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t942; CHECK-NEXT: vor.vv v8, v8, v10, v0.t943; CHECK-NEXT: vor.vv v8, v8, v9, v0.t944; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t945; CHECK-NEXT: vand.vx v9, v9, a0, v0.t946; CHECK-NEXT: vand.vx v8, v8, a0, v0.t947; CHECK-NEXT: lui a0, 209715948; CHECK-NEXT: addi a0, a0, 819949; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t950; CHECK-NEXT: vor.vv v8, v9, v8, v0.t951; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t952; CHECK-NEXT: vand.vx v9, v9, a0, v0.t953; CHECK-NEXT: vand.vx v8, v8, a0, v0.t954; CHECK-NEXT: lui a0, 349525955; CHECK-NEXT: addi a0, a0, 1365956; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t957; CHECK-NEXT: vor.vv v8, v9, v8, v0.t958; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t959; CHECK-NEXT: vand.vx v9, v9, a0, v0.t960; CHECK-NEXT: vand.vx v8, v8, a0, v0.t961; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t962; CHECK-NEXT: vor.vv v8, v9, v8, v0.t963; CHECK-NEXT: ret964;965; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i32:966; CHECK-ZVBB: # %bb.0:967; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma968; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t969; CHECK-ZVBB-NEXT: ret970 %v = call <vscale x 1 x i32> @llvm.vp.bitreverse.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl)971 ret <vscale x 1 x i32> %v972}973 974define <vscale x 1 x i32> @vp_bitreverse_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {975; CHECK-LABEL: vp_bitreverse_nxv1i32_unmasked:976; CHECK: # %bb.0:977; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma978; CHECK-NEXT: vsrl.vi v9, v8, 8979; CHECK-NEXT: lui a0, 16980; CHECK-NEXT: vsrl.vi v10, v8, 24981; CHECK-NEXT: addi a0, a0, -256982; CHECK-NEXT: vand.vx v9, v9, a0983; CHECK-NEXT: vor.vv v9, v9, v10984; CHECK-NEXT: vsll.vi v10, v8, 24985; CHECK-NEXT: vand.vx v8, v8, a0986; CHECK-NEXT: lui a0, 61681987; CHECK-NEXT: addi a0, a0, -241988; CHECK-NEXT: vsll.vi v8, v8, 8989; CHECK-NEXT: vor.vv v8, v10, v8990; CHECK-NEXT: vor.vv v8, v8, v9991; CHECK-NEXT: vsrl.vi v9, v8, 4992; CHECK-NEXT: vand.vx v8, v8, a0993; CHECK-NEXT: vand.vx v9, v9, a0994; CHECK-NEXT: lui a0, 209715995; CHECK-NEXT: addi a0, a0, 819996; CHECK-NEXT: vsll.vi v8, v8, 4997; CHECK-NEXT: vor.vv v8, v9, v8998; CHECK-NEXT: vsrl.vi v9, v8, 2999; CHECK-NEXT: vand.vx v8, v8, a01000; CHECK-NEXT: vand.vx v9, v9, a01001; CHECK-NEXT: lui a0, 3495251002; CHECK-NEXT: addi a0, a0, 13651003; CHECK-NEXT: vsll.vi v8, v8, 21004; CHECK-NEXT: vor.vv v8, v9, v81005; CHECK-NEXT: vsrl.vi v9, v8, 11006; CHECK-NEXT: vand.vx v8, v8, a01007; CHECK-NEXT: vand.vx v9, v9, a01008; CHECK-NEXT: vadd.vv v8, v8, v81009; CHECK-NEXT: vor.vv v8, v9, v81010; CHECK-NEXT: ret1011;1012; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i32_unmasked:1013; CHECK-ZVBB: # %bb.0:1014; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1015; CHECK-ZVBB-NEXT: vbrev.v v8, v81016; CHECK-ZVBB-NEXT: ret1017 %v = call <vscale x 1 x i32> @llvm.vp.bitreverse.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1018 ret <vscale x 1 x i32> %v1019}1020 1021define <vscale x 2 x i32> @vp_bitreverse_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1022; CHECK-LABEL: vp_bitreverse_nxv2i32:1023; CHECK: # %bb.0:1024; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1025; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t1026; CHECK-NEXT: lui a0, 161027; CHECK-NEXT: addi a0, a0, -2561028; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1029; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t1030; CHECK-NEXT: vor.vv v9, v9, v10, v0.t1031; CHECK-NEXT: vand.vx v10, v8, a0, v0.t1032; CHECK-NEXT: lui a0, 616811033; CHECK-NEXT: addi a0, a0, -2411034; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t1035; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t1036; CHECK-NEXT: vor.vv v8, v8, v10, v0.t1037; CHECK-NEXT: vor.vv v8, v8, v9, v0.t1038; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t1039; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1040; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1041; CHECK-NEXT: lui a0, 2097151042; CHECK-NEXT: addi a0, a0, 8191043; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t1044; CHECK-NEXT: vor.vv v8, v9, v8, v0.t1045; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t1046; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1047; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1048; CHECK-NEXT: lui a0, 3495251049; CHECK-NEXT: addi a0, a0, 13651050; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t1051; CHECK-NEXT: vor.vv v8, v9, v8, v0.t1052; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t1053; CHECK-NEXT: vand.vx v9, v9, a0, v0.t1054; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1055; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1056; CHECK-NEXT: vor.vv v8, v9, v8, v0.t1057; CHECK-NEXT: ret1058;1059; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i32:1060; CHECK-ZVBB: # %bb.0:1061; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma1062; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1063; CHECK-ZVBB-NEXT: ret1064 %v = call <vscale x 2 x i32> @llvm.vp.bitreverse.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)1065 ret <vscale x 2 x i32> %v1066}1067 1068define <vscale x 2 x i32> @vp_bitreverse_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1069; CHECK-LABEL: vp_bitreverse_nxv2i32_unmasked:1070; CHECK: # %bb.0:1071; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1072; CHECK-NEXT: vsrl.vi v9, v8, 81073; CHECK-NEXT: lui a0, 161074; CHECK-NEXT: vsrl.vi v10, v8, 241075; CHECK-NEXT: addi a0, a0, -2561076; CHECK-NEXT: vand.vx v9, v9, a01077; CHECK-NEXT: vor.vv v9, v9, v101078; CHECK-NEXT: vsll.vi v10, v8, 241079; CHECK-NEXT: vand.vx v8, v8, a01080; CHECK-NEXT: lui a0, 616811081; CHECK-NEXT: addi a0, a0, -2411082; CHECK-NEXT: vsll.vi v8, v8, 81083; CHECK-NEXT: vor.vv v8, v10, v81084; CHECK-NEXT: vor.vv v8, v8, v91085; CHECK-NEXT: vsrl.vi v9, v8, 41086; CHECK-NEXT: vand.vx v8, v8, a01087; CHECK-NEXT: vand.vx v9, v9, a01088; CHECK-NEXT: lui a0, 2097151089; CHECK-NEXT: addi a0, a0, 8191090; CHECK-NEXT: vsll.vi v8, v8, 41091; CHECK-NEXT: vor.vv v8, v9, v81092; CHECK-NEXT: vsrl.vi v9, v8, 21093; CHECK-NEXT: vand.vx v8, v8, a01094; CHECK-NEXT: vand.vx v9, v9, a01095; CHECK-NEXT: lui a0, 3495251096; CHECK-NEXT: addi a0, a0, 13651097; CHECK-NEXT: vsll.vi v8, v8, 21098; CHECK-NEXT: vor.vv v8, v9, v81099; CHECK-NEXT: vsrl.vi v9, v8, 11100; CHECK-NEXT: vand.vx v8, v8, a01101; CHECK-NEXT: vand.vx v9, v9, a01102; CHECK-NEXT: vadd.vv v8, v8, v81103; CHECK-NEXT: vor.vv v8, v9, v81104; CHECK-NEXT: ret1105;1106; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i32_unmasked:1107; CHECK-ZVBB: # %bb.0:1108; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma1109; CHECK-ZVBB-NEXT: vbrev.v v8, v81110; CHECK-ZVBB-NEXT: ret1111 %v = call <vscale x 2 x i32> @llvm.vp.bitreverse.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1112 ret <vscale x 2 x i32> %v1113}1114 1115define <vscale x 4 x i32> @vp_bitreverse_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1116; CHECK-LABEL: vp_bitreverse_nxv4i32:1117; CHECK: # %bb.0:1118; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1119; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t1120; CHECK-NEXT: lui a0, 161121; CHECK-NEXT: addi a0, a0, -2561122; CHECK-NEXT: vand.vx v10, v10, a0, v0.t1123; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t1124; CHECK-NEXT: vor.vv v10, v10, v12, v0.t1125; CHECK-NEXT: vand.vx v12, v8, a0, v0.t1126; CHECK-NEXT: lui a0, 616811127; CHECK-NEXT: addi a0, a0, -2411128; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t1129; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t1130; CHECK-NEXT: vor.vv v8, v8, v12, v0.t1131; CHECK-NEXT: vor.vv v8, v8, v10, v0.t1132; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t1133; CHECK-NEXT: vand.vx v10, v10, a0, v0.t1134; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1135; CHECK-NEXT: lui a0, 2097151136; CHECK-NEXT: addi a0, a0, 8191137; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t1138; CHECK-NEXT: vor.vv v8, v10, v8, v0.t1139; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t1140; CHECK-NEXT: vand.vx v10, v10, a0, v0.t1141; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1142; CHECK-NEXT: lui a0, 3495251143; CHECK-NEXT: addi a0, a0, 13651144; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t1145; CHECK-NEXT: vor.vv v8, v10, v8, v0.t1146; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t1147; CHECK-NEXT: vand.vx v10, v10, a0, v0.t1148; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1149; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1150; CHECK-NEXT: vor.vv v8, v10, v8, v0.t1151; CHECK-NEXT: ret1152;1153; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i32:1154; CHECK-ZVBB: # %bb.0:1155; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma1156; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1157; CHECK-ZVBB-NEXT: ret1158 %v = call <vscale x 4 x i32> @llvm.vp.bitreverse.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)1159 ret <vscale x 4 x i32> %v1160}1161 1162define <vscale x 4 x i32> @vp_bitreverse_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1163; CHECK-LABEL: vp_bitreverse_nxv4i32_unmasked:1164; CHECK: # %bb.0:1165; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1166; CHECK-NEXT: vsrl.vi v10, v8, 81167; CHECK-NEXT: lui a0, 161168; CHECK-NEXT: vsrl.vi v12, v8, 241169; CHECK-NEXT: addi a0, a0, -2561170; CHECK-NEXT: vand.vx v10, v10, a01171; CHECK-NEXT: vor.vv v10, v10, v121172; CHECK-NEXT: vsll.vi v12, v8, 241173; CHECK-NEXT: vand.vx v8, v8, a01174; CHECK-NEXT: lui a0, 616811175; CHECK-NEXT: addi a0, a0, -2411176; CHECK-NEXT: vsll.vi v8, v8, 81177; CHECK-NEXT: vor.vv v8, v12, v81178; CHECK-NEXT: vor.vv v8, v8, v101179; CHECK-NEXT: vsrl.vi v10, v8, 41180; CHECK-NEXT: vand.vx v8, v8, a01181; CHECK-NEXT: vand.vx v10, v10, a01182; CHECK-NEXT: lui a0, 2097151183; CHECK-NEXT: addi a0, a0, 8191184; CHECK-NEXT: vsll.vi v8, v8, 41185; CHECK-NEXT: vor.vv v8, v10, v81186; CHECK-NEXT: vsrl.vi v10, v8, 21187; CHECK-NEXT: vand.vx v8, v8, a01188; CHECK-NEXT: vand.vx v10, v10, a01189; CHECK-NEXT: lui a0, 3495251190; CHECK-NEXT: addi a0, a0, 13651191; CHECK-NEXT: vsll.vi v8, v8, 21192; CHECK-NEXT: vor.vv v8, v10, v81193; CHECK-NEXT: vsrl.vi v10, v8, 11194; CHECK-NEXT: vand.vx v8, v8, a01195; CHECK-NEXT: vand.vx v10, v10, a01196; CHECK-NEXT: vadd.vv v8, v8, v81197; CHECK-NEXT: vor.vv v8, v10, v81198; CHECK-NEXT: ret1199;1200; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i32_unmasked:1201; CHECK-ZVBB: # %bb.0:1202; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma1203; CHECK-ZVBB-NEXT: vbrev.v v8, v81204; CHECK-ZVBB-NEXT: ret1205 %v = call <vscale x 4 x i32> @llvm.vp.bitreverse.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1206 ret <vscale x 4 x i32> %v1207}1208 1209define <vscale x 8 x i32> @vp_bitreverse_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1210; CHECK-LABEL: vp_bitreverse_nxv8i32:1211; CHECK: # %bb.0:1212; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1213; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t1214; CHECK-NEXT: lui a0, 161215; CHECK-NEXT: addi a0, a0, -2561216; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1217; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t1218; CHECK-NEXT: vor.vv v12, v12, v16, v0.t1219; CHECK-NEXT: vand.vx v16, v8, a0, v0.t1220; CHECK-NEXT: lui a0, 616811221; CHECK-NEXT: addi a0, a0, -2411222; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t1223; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t1224; CHECK-NEXT: vor.vv v8, v8, v16, v0.t1225; CHECK-NEXT: vor.vv v8, v8, v12, v0.t1226; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t1227; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1228; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1229; CHECK-NEXT: lui a0, 2097151230; CHECK-NEXT: addi a0, a0, 8191231; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t1232; CHECK-NEXT: vor.vv v8, v12, v8, v0.t1233; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t1234; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1235; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1236; CHECK-NEXT: lui a0, 3495251237; CHECK-NEXT: addi a0, a0, 13651238; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t1239; CHECK-NEXT: vor.vv v8, v12, v8, v0.t1240; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t1241; CHECK-NEXT: vand.vx v12, v12, a0, v0.t1242; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1243; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1244; CHECK-NEXT: vor.vv v8, v12, v8, v0.t1245; CHECK-NEXT: ret1246;1247; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i32:1248; CHECK-ZVBB: # %bb.0:1249; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1250; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1251; CHECK-ZVBB-NEXT: ret1252 %v = call <vscale x 8 x i32> @llvm.vp.bitreverse.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl)1253 ret <vscale x 8 x i32> %v1254}1255 1256define <vscale x 8 x i32> @vp_bitreverse_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1257; CHECK-LABEL: vp_bitreverse_nxv8i32_unmasked:1258; CHECK: # %bb.0:1259; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1260; CHECK-NEXT: vsrl.vi v12, v8, 81261; CHECK-NEXT: lui a0, 161262; CHECK-NEXT: vsrl.vi v16, v8, 241263; CHECK-NEXT: addi a0, a0, -2561264; CHECK-NEXT: vand.vx v12, v12, a01265; CHECK-NEXT: vor.vv v12, v12, v161266; CHECK-NEXT: vsll.vi v16, v8, 241267; CHECK-NEXT: vand.vx v8, v8, a01268; CHECK-NEXT: lui a0, 616811269; CHECK-NEXT: addi a0, a0, -2411270; CHECK-NEXT: vsll.vi v8, v8, 81271; CHECK-NEXT: vor.vv v8, v16, v81272; CHECK-NEXT: vor.vv v8, v8, v121273; CHECK-NEXT: vsrl.vi v12, v8, 41274; CHECK-NEXT: vand.vx v8, v8, a01275; CHECK-NEXT: vand.vx v12, v12, a01276; CHECK-NEXT: lui a0, 2097151277; CHECK-NEXT: addi a0, a0, 8191278; CHECK-NEXT: vsll.vi v8, v8, 41279; CHECK-NEXT: vor.vv v8, v12, v81280; CHECK-NEXT: vsrl.vi v12, v8, 21281; CHECK-NEXT: vand.vx v8, v8, a01282; CHECK-NEXT: vand.vx v12, v12, a01283; CHECK-NEXT: lui a0, 3495251284; CHECK-NEXT: addi a0, a0, 13651285; CHECK-NEXT: vsll.vi v8, v8, 21286; CHECK-NEXT: vor.vv v8, v12, v81287; CHECK-NEXT: vsrl.vi v12, v8, 11288; CHECK-NEXT: vand.vx v8, v8, a01289; CHECK-NEXT: vand.vx v12, v12, a01290; CHECK-NEXT: vadd.vv v8, v8, v81291; CHECK-NEXT: vor.vv v8, v12, v81292; CHECK-NEXT: ret1293;1294; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i32_unmasked:1295; CHECK-ZVBB: # %bb.0:1296; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma1297; CHECK-ZVBB-NEXT: vbrev.v v8, v81298; CHECK-ZVBB-NEXT: ret1299 %v = call <vscale x 8 x i32> @llvm.vp.bitreverse.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1300 ret <vscale x 8 x i32> %v1301}1302 1303define <vscale x 16 x i32> @vp_bitreverse_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1304; CHECK-LABEL: vp_bitreverse_nxv16i32:1305; CHECK: # %bb.0:1306; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1307; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t1308; CHECK-NEXT: lui a0, 161309; CHECK-NEXT: addi a0, a0, -2561310; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1311; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t1312; CHECK-NEXT: vor.vv v16, v16, v24, v0.t1313; CHECK-NEXT: vand.vx v24, v8, a0, v0.t1314; CHECK-NEXT: lui a0, 616811315; CHECK-NEXT: addi a0, a0, -2411316; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t1317; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t1318; CHECK-NEXT: vor.vv v8, v8, v24, v0.t1319; CHECK-NEXT: vor.vv v16, v8, v16, v0.t1320; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t1321; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1322; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1323; CHECK-NEXT: lui a0, 2097151324; CHECK-NEXT: addi a0, a0, 8191325; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t1326; CHECK-NEXT: vor.vv v16, v8, v16, v0.t1327; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t1328; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1329; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1330; CHECK-NEXT: lui a0, 3495251331; CHECK-NEXT: addi a0, a0, 13651332; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t1333; CHECK-NEXT: vor.vv v8, v8, v16, v0.t1334; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t1335; CHECK-NEXT: vand.vx v16, v16, a0, v0.t1336; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1337; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t1338; CHECK-NEXT: vor.vv v8, v16, v8, v0.t1339; CHECK-NEXT: ret1340;1341; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i32:1342; CHECK-ZVBB: # %bb.0:1343; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1344; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1345; CHECK-ZVBB-NEXT: ret1346 %v = call <vscale x 16 x i32> @llvm.vp.bitreverse.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl)1347 ret <vscale x 16 x i32> %v1348}1349 1350define <vscale x 16 x i32> @vp_bitreverse_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1351; CHECK-LABEL: vp_bitreverse_nxv16i32_unmasked:1352; CHECK: # %bb.0:1353; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1354; CHECK-NEXT: vsrl.vi v16, v8, 81355; CHECK-NEXT: lui a0, 161356; CHECK-NEXT: vsrl.vi v24, v8, 241357; CHECK-NEXT: addi a0, a0, -2561358; CHECK-NEXT: vand.vx v16, v16, a01359; CHECK-NEXT: vor.vv v16, v16, v241360; CHECK-NEXT: vsll.vi v24, v8, 241361; CHECK-NEXT: vand.vx v8, v8, a01362; CHECK-NEXT: lui a0, 616811363; CHECK-NEXT: addi a0, a0, -2411364; CHECK-NEXT: vsll.vi v8, v8, 81365; CHECK-NEXT: vor.vv v8, v24, v81366; CHECK-NEXT: vor.vv v8, v8, v161367; CHECK-NEXT: vsrl.vi v16, v8, 41368; CHECK-NEXT: vand.vx v8, v8, a01369; CHECK-NEXT: vand.vx v16, v16, a01370; CHECK-NEXT: lui a0, 2097151371; CHECK-NEXT: addi a0, a0, 8191372; CHECK-NEXT: vsll.vi v8, v8, 41373; CHECK-NEXT: vor.vv v8, v16, v81374; CHECK-NEXT: vsrl.vi v16, v8, 21375; CHECK-NEXT: vand.vx v8, v8, a01376; CHECK-NEXT: vand.vx v16, v16, a01377; CHECK-NEXT: lui a0, 3495251378; CHECK-NEXT: addi a0, a0, 13651379; CHECK-NEXT: vsll.vi v8, v8, 21380; CHECK-NEXT: vor.vv v8, v16, v81381; CHECK-NEXT: vsrl.vi v16, v8, 11382; CHECK-NEXT: vand.vx v8, v8, a01383; CHECK-NEXT: vand.vx v16, v16, a01384; CHECK-NEXT: vadd.vv v8, v8, v81385; CHECK-NEXT: vor.vv v8, v16, v81386; CHECK-NEXT: ret1387;1388; CHECK-ZVBB-LABEL: vp_bitreverse_nxv16i32_unmasked:1389; CHECK-ZVBB: # %bb.0:1390; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma1391; CHECK-ZVBB-NEXT: vbrev.v v8, v81392; CHECK-ZVBB-NEXT: ret1393 %v = call <vscale x 16 x i32> @llvm.vp.bitreverse.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1394 ret <vscale x 16 x i32> %v1395}1396 1397define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1398; RV32-LABEL: vp_bitreverse_nxv1i64:1399; RV32: # %bb.0:1400; RV32-NEXT: addi sp, sp, -161401; RV32-NEXT: .cfi_def_cfa_offset 161402; RV32-NEXT: lui a4, 10444801403; RV32-NEXT: li a3, 561404; RV32-NEXT: lui a5, 161405; RV32-NEXT: li a2, 401406; RV32-NEXT: lui a1, 40801407; RV32-NEXT: addi a6, sp, 81408; RV32-NEXT: sw a4, 8(sp)1409; RV32-NEXT: sw zero, 12(sp)1410; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1411; RV32-NEXT: vlse64.v v9, (a6), zero1412; RV32-NEXT: lui a4, 616811413; RV32-NEXT: vsll.vx v10, v8, a3, v0.t1414; RV32-NEXT: addi a5, a5, -2561415; RV32-NEXT: vand.vx v11, v8, a5, v0.t1416; RV32-NEXT: vsll.vx v11, v11, a2, v0.t1417; RV32-NEXT: vor.vv v10, v10, v11, v0.t1418; RV32-NEXT: vand.vx v11, v8, a1, v0.t1419; RV32-NEXT: vsll.vi v11, v11, 24, v0.t1420; RV32-NEXT: vand.vv v12, v8, v9, v0.t1421; RV32-NEXT: vsll.vi v12, v12, 8, v0.t1422; RV32-NEXT: vor.vv v11, v11, v12, v0.t1423; RV32-NEXT: vor.vv v10, v10, v11, v0.t1424; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t1425; RV32-NEXT: lui a3, 2097151426; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t1427; RV32-NEXT: lui a2, 3495251428; RV32-NEXT: addi a4, a4, -2411429; RV32-NEXT: addi a3, a3, 8191430; RV32-NEXT: addi a2, a2, 13651431; RV32-NEXT: vand.vx v12, v12, a5, v0.t1432; RV32-NEXT: vor.vv v11, v12, v11, v0.t1433; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t1434; RV32-NEXT: vand.vx v12, v12, a1, v0.t1435; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1436; RV32-NEXT: vand.vv v8, v8, v9, v0.t1437; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma1438; RV32-NEXT: vmv.v.x v9, a41439; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1440; RV32-NEXT: vor.vv v8, v8, v12, v0.t1441; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma1442; RV32-NEXT: vmv.v.x v12, a31443; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1444; RV32-NEXT: vor.vv v8, v8, v11, v0.t1445; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma1446; RV32-NEXT: vmv.v.x v11, a21447; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1448; RV32-NEXT: vor.vv v8, v10, v8, v0.t1449; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t1450; RV32-NEXT: vand.vv v10, v10, v9, v0.t1451; RV32-NEXT: vand.vv v8, v8, v9, v0.t1452; RV32-NEXT: vsll.vi v8, v8, 4, v0.t1453; RV32-NEXT: vor.vv v8, v10, v8, v0.t1454; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t1455; RV32-NEXT: vand.vv v9, v9, v12, v0.t1456; RV32-NEXT: vand.vv v8, v8, v12, v0.t1457; RV32-NEXT: vsll.vi v8, v8, 2, v0.t1458; RV32-NEXT: vor.vv v8, v9, v8, v0.t1459; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t1460; RV32-NEXT: vand.vv v9, v9, v11, v0.t1461; RV32-NEXT: vand.vv v8, v8, v11, v0.t1462; RV32-NEXT: vsll.vi v8, v8, 1, v0.t1463; RV32-NEXT: vor.vv v8, v9, v8, v0.t1464; RV32-NEXT: addi sp, sp, 161465; RV32-NEXT: .cfi_def_cfa_offset 01466; RV32-NEXT: ret1467;1468; RV64-LABEL: vp_bitreverse_nxv1i64:1469; RV64: # %bb.0:1470; RV64-NEXT: lui a1, 40801471; RV64-NEXT: li a3, 2551472; RV64-NEXT: li a2, 561473; RV64-NEXT: lui a4, 161474; RV64-NEXT: lui a5, 616811475; RV64-NEXT: lui a6, 2097151476; RV64-NEXT: lui a7, 3495251477; RV64-NEXT: addi a5, a5, -2411478; RV64-NEXT: addi a6, a6, 8191479; RV64-NEXT: addi a7, a7, 13651480; RV64-NEXT: slli t0, a5, 321481; RV64-NEXT: add t0, a5, t01482; RV64-NEXT: slli a5, a6, 321483; RV64-NEXT: add a6, a6, a51484; RV64-NEXT: slli a5, a7, 321485; RV64-NEXT: add a5, a7, a51486; RV64-NEXT: li a7, 401487; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1488; RV64-NEXT: vand.vx v9, v8, a1, v0.t1489; RV64-NEXT: slli a3, a3, 241490; RV64-NEXT: addi a0, a4, -2561491; RV64-NEXT: vsll.vi v9, v9, 24, v0.t1492; RV64-NEXT: vand.vx v10, v8, a3, v0.t1493; RV64-NEXT: vsll.vi v10, v10, 8, v0.t1494; RV64-NEXT: vor.vv v9, v9, v10, v0.t1495; RV64-NEXT: vsll.vx v10, v8, a2, v0.t1496; RV64-NEXT: vand.vx v11, v8, a0, v0.t1497; RV64-NEXT: vsll.vx v11, v11, a7, v0.t1498; RV64-NEXT: vor.vv v10, v10, v11, v0.t1499; RV64-NEXT: vor.vv v9, v10, v9, v0.t1500; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t1501; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t1502; RV64-NEXT: vand.vx v11, v11, a0, v0.t1503; RV64-NEXT: vor.vv v10, v11, v10, v0.t1504; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t1505; RV64-NEXT: vand.vx v11, v11, a1, v0.t1506; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1507; RV64-NEXT: vand.vx v8, v8, a3, v0.t1508; RV64-NEXT: vor.vv v8, v8, v11, v0.t1509; RV64-NEXT: vor.vv v8, v8, v10, v0.t1510; RV64-NEXT: vor.vv v8, v9, v8, v0.t1511; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t1512; RV64-NEXT: vand.vx v9, v9, t0, v0.t1513; RV64-NEXT: vand.vx v8, v8, t0, v0.t1514; RV64-NEXT: vsll.vi v8, v8, 4, v0.t1515; RV64-NEXT: vor.vv v8, v9, v8, v0.t1516; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t1517; RV64-NEXT: vand.vx v9, v9, a6, v0.t1518; RV64-NEXT: vand.vx v8, v8, a6, v0.t1519; RV64-NEXT: vsll.vi v8, v8, 2, v0.t1520; RV64-NEXT: vor.vv v8, v9, v8, v0.t1521; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t1522; RV64-NEXT: vand.vx v9, v9, a5, v0.t1523; RV64-NEXT: vand.vx v8, v8, a5, v0.t1524; RV64-NEXT: vsll.vi v8, v8, 1, v0.t1525; RV64-NEXT: vor.vv v8, v9, v8, v0.t1526; RV64-NEXT: ret1527;1528; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i64:1529; CHECK-ZVBB: # %bb.0:1530; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1531; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1532; CHECK-ZVBB-NEXT: ret1533 %v = call <vscale x 1 x i64> @llvm.vp.bitreverse.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)1534 ret <vscale x 1 x i64> %v1535}1536 1537define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1538; RV32-LABEL: vp_bitreverse_nxv1i64_unmasked:1539; RV32: # %bb.0:1540; RV32-NEXT: addi sp, sp, -161541; RV32-NEXT: .cfi_def_cfa_offset 161542; RV32-NEXT: lui a1, 10444801543; RV32-NEXT: li a2, 561544; RV32-NEXT: lui a3, 161545; RV32-NEXT: li a4, 401546; RV32-NEXT: lui a5, 40801547; RV32-NEXT: addi a6, sp, 81548; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1549; RV32-NEXT: vsrl.vi v9, v8, 241550; RV32-NEXT: sw a1, 8(sp)1551; RV32-NEXT: sw zero, 12(sp)1552; RV32-NEXT: vsll.vx v10, v8, a21553; RV32-NEXT: addi a1, a3, -2561554; RV32-NEXT: vsrl.vx v11, v8, a21555; RV32-NEXT: vsrl.vx v12, v8, a41556; RV32-NEXT: vand.vx v13, v8, a11557; RV32-NEXT: vand.vx v12, v12, a11558; RV32-NEXT: vor.vv v11, v12, v111559; RV32-NEXT: vlse64.v v12, (a6), zero1560; RV32-NEXT: vsll.vx v13, v13, a41561; RV32-NEXT: vor.vv v10, v10, v131562; RV32-NEXT: vsrl.vi v13, v8, 81563; RV32-NEXT: vand.vx v9, v9, a51564; RV32-NEXT: vand.vv v13, v13, v121565; RV32-NEXT: vor.vv v9, v13, v91566; RV32-NEXT: lui a1, 616811567; RV32-NEXT: lui a2, 2097151568; RV32-NEXT: lui a3, 3495251569; RV32-NEXT: vand.vv v12, v8, v121570; RV32-NEXT: vand.vx v8, v8, a51571; RV32-NEXT: addi a1, a1, -2411572; RV32-NEXT: addi a2, a2, 8191573; RV32-NEXT: addi a3, a3, 13651574; RV32-NEXT: vsll.vi v8, v8, 241575; RV32-NEXT: vsll.vi v12, v12, 81576; RV32-NEXT: vor.vv v8, v8, v121577; RV32-NEXT: vsetvli a4, zero, e32, m1, ta, ma1578; RV32-NEXT: vmv.v.x v12, a11579; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1580; RV32-NEXT: vor.vv v9, v9, v111581; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma1582; RV32-NEXT: vmv.v.x v11, a21583; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1584; RV32-NEXT: vor.vv v8, v10, v81585; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma1586; RV32-NEXT: vmv.v.x v10, a31587; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1588; RV32-NEXT: vor.vv v8, v8, v91589; RV32-NEXT: vsrl.vi v9, v8, 41590; RV32-NEXT: vand.vv v8, v8, v121591; RV32-NEXT: vand.vv v9, v9, v121592; RV32-NEXT: vsll.vi v8, v8, 41593; RV32-NEXT: vor.vv v8, v9, v81594; RV32-NEXT: vsrl.vi v9, v8, 21595; RV32-NEXT: vand.vv v8, v8, v111596; RV32-NEXT: vand.vv v9, v9, v111597; RV32-NEXT: vsll.vi v8, v8, 21598; RV32-NEXT: vor.vv v8, v9, v81599; RV32-NEXT: vsrl.vi v9, v8, 11600; RV32-NEXT: vand.vv v8, v8, v101601; RV32-NEXT: vand.vv v9, v9, v101602; RV32-NEXT: vadd.vv v8, v8, v81603; RV32-NEXT: vor.vv v8, v9, v81604; RV32-NEXT: addi sp, sp, 161605; RV32-NEXT: .cfi_def_cfa_offset 01606; RV32-NEXT: ret1607;1608; RV64-LABEL: vp_bitreverse_nxv1i64_unmasked:1609; RV64: # %bb.0:1610; RV64-NEXT: lui a1, 40801611; RV64-NEXT: li a2, 2551612; RV64-NEXT: li a3, 561613; RV64-NEXT: lui a4, 161614; RV64-NEXT: li a5, 401615; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1616; RV64-NEXT: vsrl.vi v9, v8, 241617; RV64-NEXT: vsrl.vi v10, v8, 81618; RV64-NEXT: addi a0, a4, -2561619; RV64-NEXT: vsrl.vx v11, v8, a31620; RV64-NEXT: vsrl.vx v12, v8, a51621; RV64-NEXT: vand.vx v12, v12, a01622; RV64-NEXT: vor.vv v11, v12, v111623; RV64-NEXT: vand.vx v12, v8, a11624; RV64-NEXT: slli a2, a2, 241625; RV64-NEXT: vand.vx v9, v9, a11626; RV64-NEXT: vsll.vi v12, v12, 241627; RV64-NEXT: vand.vx v10, v10, a21628; RV64-NEXT: vor.vv v9, v10, v91629; RV64-NEXT: vand.vx v10, v8, a21630; RV64-NEXT: vsll.vi v10, v10, 81631; RV64-NEXT: vor.vv v10, v12, v101632; RV64-NEXT: vsll.vx v12, v8, a31633; RV64-NEXT: vand.vx v8, v8, a01634; RV64-NEXT: vsll.vx v8, v8, a51635; RV64-NEXT: vor.vv v8, v12, v81636; RV64-NEXT: lui a0, 616811637; RV64-NEXT: lui a1, 2097151638; RV64-NEXT: lui a2, 3495251639; RV64-NEXT: addi a0, a0, -2411640; RV64-NEXT: addi a1, a1, 8191641; RV64-NEXT: addi a2, a2, 13651642; RV64-NEXT: slli a3, a0, 321643; RV64-NEXT: slli a4, a1, 321644; RV64-NEXT: add a0, a0, a31645; RV64-NEXT: slli a3, a2, 321646; RV64-NEXT: add a1, a1, a41647; RV64-NEXT: add a2, a2, a31648; RV64-NEXT: vor.vv v9, v9, v111649; RV64-NEXT: vor.vv v8, v8, v101650; RV64-NEXT: vor.vv v8, v8, v91651; RV64-NEXT: vsrl.vi v9, v8, 41652; RV64-NEXT: vand.vx v8, v8, a01653; RV64-NEXT: vand.vx v9, v9, a01654; RV64-NEXT: vsll.vi v8, v8, 41655; RV64-NEXT: vor.vv v8, v9, v81656; RV64-NEXT: vsrl.vi v9, v8, 21657; RV64-NEXT: vand.vx v8, v8, a11658; RV64-NEXT: vand.vx v9, v9, a11659; RV64-NEXT: vsll.vi v8, v8, 21660; RV64-NEXT: vor.vv v8, v9, v81661; RV64-NEXT: vsrl.vi v9, v8, 11662; RV64-NEXT: vand.vx v8, v8, a21663; RV64-NEXT: vand.vx v9, v9, a21664; RV64-NEXT: vadd.vv v8, v8, v81665; RV64-NEXT: vor.vv v8, v9, v81666; RV64-NEXT: ret1667;1668; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i64_unmasked:1669; CHECK-ZVBB: # %bb.0:1670; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1671; CHECK-ZVBB-NEXT: vbrev.v v8, v81672; CHECK-ZVBB-NEXT: ret1673 %v = call <vscale x 1 x i64> @llvm.vp.bitreverse.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1674 ret <vscale x 1 x i64> %v1675}1676 1677define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1678; RV32-LABEL: vp_bitreverse_nxv2i64:1679; RV32: # %bb.0:1680; RV32-NEXT: addi sp, sp, -161681; RV32-NEXT: .cfi_def_cfa_offset 161682; RV32-NEXT: lui a4, 10444801683; RV32-NEXT: li a3, 561684; RV32-NEXT: lui a5, 161685; RV32-NEXT: li a2, 401686; RV32-NEXT: lui a1, 40801687; RV32-NEXT: addi a6, sp, 81688; RV32-NEXT: sw a4, 8(sp)1689; RV32-NEXT: sw zero, 12(sp)1690; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1691; RV32-NEXT: vlse64.v v10, (a6), zero1692; RV32-NEXT: lui a4, 616811693; RV32-NEXT: vsll.vx v12, v8, a3, v0.t1694; RV32-NEXT: addi a5, a5, -2561695; RV32-NEXT: vand.vx v14, v8, a5, v0.t1696; RV32-NEXT: vsll.vx v14, v14, a2, v0.t1697; RV32-NEXT: vor.vv v12, v12, v14, v0.t1698; RV32-NEXT: vand.vx v14, v8, a1, v0.t1699; RV32-NEXT: vsll.vi v14, v14, 24, v0.t1700; RV32-NEXT: vand.vv v16, v8, v10, v0.t1701; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1702; RV32-NEXT: vor.vv v14, v14, v16, v0.t1703; RV32-NEXT: vor.vv v12, v12, v14, v0.t1704; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t1705; RV32-NEXT: lui a3, 2097151706; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1707; RV32-NEXT: lui a2, 3495251708; RV32-NEXT: addi a4, a4, -2411709; RV32-NEXT: addi a3, a3, 8191710; RV32-NEXT: addi a2, a2, 13651711; RV32-NEXT: vand.vx v16, v16, a5, v0.t1712; RV32-NEXT: vor.vv v14, v16, v14, v0.t1713; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t1714; RV32-NEXT: vand.vx v16, v16, a1, v0.t1715; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1716; RV32-NEXT: vand.vv v8, v8, v10, v0.t1717; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma1718; RV32-NEXT: vmv.v.x v10, a41719; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1720; RV32-NEXT: vor.vv v8, v8, v16, v0.t1721; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma1722; RV32-NEXT: vmv.v.x v16, a31723; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1724; RV32-NEXT: vor.vv v8, v8, v14, v0.t1725; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma1726; RV32-NEXT: vmv.v.x v14, a21727; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1728; RV32-NEXT: vor.vv v8, v12, v8, v0.t1729; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t1730; RV32-NEXT: vand.vv v12, v12, v10, v0.t1731; RV32-NEXT: vand.vv v8, v8, v10, v0.t1732; RV32-NEXT: vsll.vi v8, v8, 4, v0.t1733; RV32-NEXT: vor.vv v8, v12, v8, v0.t1734; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t1735; RV32-NEXT: vand.vv v10, v10, v16, v0.t1736; RV32-NEXT: vand.vv v8, v8, v16, v0.t1737; RV32-NEXT: vsll.vi v8, v8, 2, v0.t1738; RV32-NEXT: vor.vv v8, v10, v8, v0.t1739; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t1740; RV32-NEXT: vand.vv v10, v10, v14, v0.t1741; RV32-NEXT: vand.vv v8, v8, v14, v0.t1742; RV32-NEXT: vsll.vi v8, v8, 1, v0.t1743; RV32-NEXT: vor.vv v8, v10, v8, v0.t1744; RV32-NEXT: addi sp, sp, 161745; RV32-NEXT: .cfi_def_cfa_offset 01746; RV32-NEXT: ret1747;1748; RV64-LABEL: vp_bitreverse_nxv2i64:1749; RV64: # %bb.0:1750; RV64-NEXT: lui a1, 40801751; RV64-NEXT: li a3, 2551752; RV64-NEXT: li a2, 561753; RV64-NEXT: lui a4, 161754; RV64-NEXT: lui a5, 616811755; RV64-NEXT: lui a6, 2097151756; RV64-NEXT: lui a7, 3495251757; RV64-NEXT: addi a5, a5, -2411758; RV64-NEXT: addi a6, a6, 8191759; RV64-NEXT: addi a7, a7, 13651760; RV64-NEXT: slli t0, a5, 321761; RV64-NEXT: add t0, a5, t01762; RV64-NEXT: slli a5, a6, 321763; RV64-NEXT: add a6, a6, a51764; RV64-NEXT: slli a5, a7, 321765; RV64-NEXT: add a5, a7, a51766; RV64-NEXT: li a7, 401767; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1768; RV64-NEXT: vand.vx v10, v8, a1, v0.t1769; RV64-NEXT: slli a3, a3, 241770; RV64-NEXT: addi a0, a4, -2561771; RV64-NEXT: vsll.vi v10, v10, 24, v0.t1772; RV64-NEXT: vand.vx v12, v8, a3, v0.t1773; RV64-NEXT: vsll.vi v12, v12, 8, v0.t1774; RV64-NEXT: vor.vv v10, v10, v12, v0.t1775; RV64-NEXT: vsll.vx v12, v8, a2, v0.t1776; RV64-NEXT: vand.vx v14, v8, a0, v0.t1777; RV64-NEXT: vsll.vx v14, v14, a7, v0.t1778; RV64-NEXT: vor.vv v12, v12, v14, v0.t1779; RV64-NEXT: vor.vv v10, v12, v10, v0.t1780; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t1781; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t1782; RV64-NEXT: vand.vx v14, v14, a0, v0.t1783; RV64-NEXT: vor.vv v12, v14, v12, v0.t1784; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t1785; RV64-NEXT: vand.vx v14, v14, a1, v0.t1786; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1787; RV64-NEXT: vand.vx v8, v8, a3, v0.t1788; RV64-NEXT: vor.vv v8, v8, v14, v0.t1789; RV64-NEXT: vor.vv v8, v8, v12, v0.t1790; RV64-NEXT: vor.vv v8, v10, v8, v0.t1791; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t1792; RV64-NEXT: vand.vx v10, v10, t0, v0.t1793; RV64-NEXT: vand.vx v8, v8, t0, v0.t1794; RV64-NEXT: vsll.vi v8, v8, 4, v0.t1795; RV64-NEXT: vor.vv v8, v10, v8, v0.t1796; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t1797; RV64-NEXT: vand.vx v10, v10, a6, v0.t1798; RV64-NEXT: vand.vx v8, v8, a6, v0.t1799; RV64-NEXT: vsll.vi v8, v8, 2, v0.t1800; RV64-NEXT: vor.vv v8, v10, v8, v0.t1801; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t1802; RV64-NEXT: vand.vx v10, v10, a5, v0.t1803; RV64-NEXT: vand.vx v8, v8, a5, v0.t1804; RV64-NEXT: vsll.vi v8, v8, 1, v0.t1805; RV64-NEXT: vor.vv v8, v10, v8, v0.t1806; RV64-NEXT: ret1807;1808; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i64:1809; CHECK-ZVBB: # %bb.0:1810; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1811; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t1812; CHECK-ZVBB-NEXT: ret1813 %v = call <vscale x 2 x i64> @llvm.vp.bitreverse.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)1814 ret <vscale x 2 x i64> %v1815}1816 1817define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1818; RV32-LABEL: vp_bitreverse_nxv2i64_unmasked:1819; RV32: # %bb.0:1820; RV32-NEXT: addi sp, sp, -161821; RV32-NEXT: .cfi_def_cfa_offset 161822; RV32-NEXT: lui a1, 10444801823; RV32-NEXT: li a2, 561824; RV32-NEXT: lui a3, 161825; RV32-NEXT: li a4, 401826; RV32-NEXT: lui a5, 40801827; RV32-NEXT: addi a6, sp, 81828; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1829; RV32-NEXT: vsrl.vi v14, v8, 241830; RV32-NEXT: sw a1, 8(sp)1831; RV32-NEXT: sw zero, 12(sp)1832; RV32-NEXT: vsll.vx v12, v8, a21833; RV32-NEXT: addi a1, a3, -2561834; RV32-NEXT: vsrl.vx v10, v8, a21835; RV32-NEXT: vsrl.vx v16, v8, a41836; RV32-NEXT: vand.vx v18, v8, a11837; RV32-NEXT: vand.vx v16, v16, a11838; RV32-NEXT: vor.vv v10, v16, v101839; RV32-NEXT: vlse64.v v16, (a6), zero1840; RV32-NEXT: vsll.vx v18, v18, a41841; RV32-NEXT: vor.vv v12, v12, v181842; RV32-NEXT: vsrl.vi v18, v8, 81843; RV32-NEXT: vand.vx v14, v14, a51844; RV32-NEXT: vand.vv v18, v18, v161845; RV32-NEXT: vor.vv v14, v18, v141846; RV32-NEXT: lui a1, 616811847; RV32-NEXT: lui a2, 2097151848; RV32-NEXT: lui a3, 3495251849; RV32-NEXT: vand.vv v16, v8, v161850; RV32-NEXT: vand.vx v8, v8, a51851; RV32-NEXT: addi a1, a1, -2411852; RV32-NEXT: addi a2, a2, 8191853; RV32-NEXT: addi a3, a3, 13651854; RV32-NEXT: vsll.vi v8, v8, 241855; RV32-NEXT: vsll.vi v16, v16, 81856; RV32-NEXT: vor.vv v8, v8, v161857; RV32-NEXT: vsetvli a4, zero, e32, m2, ta, ma1858; RV32-NEXT: vmv.v.x v16, a11859; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1860; RV32-NEXT: vor.vv v10, v14, v101861; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma1862; RV32-NEXT: vmv.v.x v14, a21863; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1864; RV32-NEXT: vor.vv v8, v12, v81865; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma1866; RV32-NEXT: vmv.v.x v12, a31867; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma1868; RV32-NEXT: vor.vv v8, v8, v101869; RV32-NEXT: vsrl.vi v10, v8, 41870; RV32-NEXT: vand.vv v8, v8, v161871; RV32-NEXT: vand.vv v10, v10, v161872; RV32-NEXT: vsll.vi v8, v8, 41873; RV32-NEXT: vor.vv v8, v10, v81874; RV32-NEXT: vsrl.vi v10, v8, 21875; RV32-NEXT: vand.vv v8, v8, v141876; RV32-NEXT: vand.vv v10, v10, v141877; RV32-NEXT: vsll.vi v8, v8, 21878; RV32-NEXT: vor.vv v8, v10, v81879; RV32-NEXT: vsrl.vi v10, v8, 11880; RV32-NEXT: vand.vv v8, v8, v121881; RV32-NEXT: vand.vv v10, v10, v121882; RV32-NEXT: vadd.vv v8, v8, v81883; RV32-NEXT: vor.vv v8, v10, v81884; RV32-NEXT: addi sp, sp, 161885; RV32-NEXT: .cfi_def_cfa_offset 01886; RV32-NEXT: ret1887;1888; RV64-LABEL: vp_bitreverse_nxv2i64_unmasked:1889; RV64: # %bb.0:1890; RV64-NEXT: lui a1, 40801891; RV64-NEXT: li a2, 2551892; RV64-NEXT: li a3, 561893; RV64-NEXT: lui a4, 161894; RV64-NEXT: li a5, 401895; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma1896; RV64-NEXT: vsrl.vi v12, v8, 241897; RV64-NEXT: vsrl.vi v14, v8, 81898; RV64-NEXT: addi a0, a4, -2561899; RV64-NEXT: vsrl.vx v10, v8, a31900; RV64-NEXT: vsrl.vx v16, v8, a51901; RV64-NEXT: vand.vx v16, v16, a01902; RV64-NEXT: vor.vv v10, v16, v101903; RV64-NEXT: vand.vx v16, v8, a11904; RV64-NEXT: slli a2, a2, 241905; RV64-NEXT: vand.vx v12, v12, a11906; RV64-NEXT: vsll.vi v16, v16, 241907; RV64-NEXT: vand.vx v14, v14, a21908; RV64-NEXT: vor.vv v12, v14, v121909; RV64-NEXT: vand.vx v14, v8, a21910; RV64-NEXT: vsll.vi v14, v14, 81911; RV64-NEXT: vor.vv v14, v16, v141912; RV64-NEXT: vsll.vx v16, v8, a31913; RV64-NEXT: vand.vx v8, v8, a01914; RV64-NEXT: vsll.vx v8, v8, a51915; RV64-NEXT: vor.vv v8, v16, v81916; RV64-NEXT: lui a0, 616811917; RV64-NEXT: lui a1, 2097151918; RV64-NEXT: lui a2, 3495251919; RV64-NEXT: addi a0, a0, -2411920; RV64-NEXT: addi a1, a1, 8191921; RV64-NEXT: addi a2, a2, 13651922; RV64-NEXT: slli a3, a0, 321923; RV64-NEXT: slli a4, a1, 321924; RV64-NEXT: add a0, a0, a31925; RV64-NEXT: slli a3, a2, 321926; RV64-NEXT: add a1, a1, a41927; RV64-NEXT: add a2, a2, a31928; RV64-NEXT: vor.vv v10, v12, v101929; RV64-NEXT: vor.vv v8, v8, v141930; RV64-NEXT: vor.vv v8, v8, v101931; RV64-NEXT: vsrl.vi v10, v8, 41932; RV64-NEXT: vand.vx v8, v8, a01933; RV64-NEXT: vand.vx v10, v10, a01934; RV64-NEXT: vsll.vi v8, v8, 41935; RV64-NEXT: vor.vv v8, v10, v81936; RV64-NEXT: vsrl.vi v10, v8, 21937; RV64-NEXT: vand.vx v8, v8, a11938; RV64-NEXT: vand.vx v10, v10, a11939; RV64-NEXT: vsll.vi v8, v8, 21940; RV64-NEXT: vor.vv v8, v10, v81941; RV64-NEXT: vsrl.vi v10, v8, 11942; RV64-NEXT: vand.vx v8, v8, a21943; RV64-NEXT: vand.vx v10, v10, a21944; RV64-NEXT: vadd.vv v8, v8, v81945; RV64-NEXT: vor.vv v8, v10, v81946; RV64-NEXT: ret1947;1948; CHECK-ZVBB-LABEL: vp_bitreverse_nxv2i64_unmasked:1949; CHECK-ZVBB: # %bb.0:1950; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma1951; CHECK-ZVBB-NEXT: vbrev.v v8, v81952; CHECK-ZVBB-NEXT: ret1953 %v = call <vscale x 2 x i64> @llvm.vp.bitreverse.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1954 ret <vscale x 2 x i64> %v1955}1956 1957define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1958; RV32-LABEL: vp_bitreverse_nxv4i64:1959; RV32: # %bb.0:1960; RV32-NEXT: addi sp, sp, -161961; RV32-NEXT: .cfi_def_cfa_offset 161962; RV32-NEXT: lui a4, 10444801963; RV32-NEXT: li a3, 561964; RV32-NEXT: lui a5, 161965; RV32-NEXT: li a2, 401966; RV32-NEXT: lui a1, 40801967; RV32-NEXT: addi a6, sp, 81968; RV32-NEXT: sw a4, 8(sp)1969; RV32-NEXT: sw zero, 12(sp)1970; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma1971; RV32-NEXT: vlse64.v v12, (a6), zero1972; RV32-NEXT: lui a4, 616811973; RV32-NEXT: vsll.vx v16, v8, a3, v0.t1974; RV32-NEXT: addi a5, a5, -2561975; RV32-NEXT: vand.vx v20, v8, a5, v0.t1976; RV32-NEXT: vsll.vx v20, v20, a2, v0.t1977; RV32-NEXT: vor.vv v16, v16, v20, v0.t1978; RV32-NEXT: vand.vx v20, v8, a1, v0.t1979; RV32-NEXT: vsll.vi v20, v20, 24, v0.t1980; RV32-NEXT: vand.vv v24, v8, v12, v0.t1981; RV32-NEXT: vsll.vi v24, v24, 8, v0.t1982; RV32-NEXT: vor.vv v20, v20, v24, v0.t1983; RV32-NEXT: vor.vv v16, v16, v20, v0.t1984; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t1985; RV32-NEXT: lui a3, 2097151986; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t1987; RV32-NEXT: lui a2, 3495251988; RV32-NEXT: addi a4, a4, -2411989; RV32-NEXT: addi a3, a3, 8191990; RV32-NEXT: addi a2, a2, 13651991; RV32-NEXT: vand.vx v24, v24, a5, v0.t1992; RV32-NEXT: vor.vv v20, v24, v20, v0.t1993; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1994; RV32-NEXT: vand.vx v24, v24, a1, v0.t1995; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1996; RV32-NEXT: vand.vv v8, v8, v12, v0.t1997; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma1998; RV32-NEXT: vmv.v.x v28, a41999; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2000; RV32-NEXT: vor.vv v8, v8, v24, v0.t2001; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma2002; RV32-NEXT: vmv.v.x v12, a32003; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2004; RV32-NEXT: vor.vv v20, v8, v20, v0.t2005; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma2006; RV32-NEXT: vmv.v.x v8, a22007; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2008; RV32-NEXT: vor.vv v16, v16, v20, v0.t2009; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t2010; RV32-NEXT: vand.vv v20, v20, v28, v0.t2011; RV32-NEXT: vand.vv v16, v16, v28, v0.t2012; RV32-NEXT: vsll.vi v16, v16, 4, v0.t2013; RV32-NEXT: vor.vv v16, v20, v16, v0.t2014; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t2015; RV32-NEXT: vand.vv v20, v20, v12, v0.t2016; RV32-NEXT: vand.vv v12, v16, v12, v0.t2017; RV32-NEXT: vsll.vi v12, v12, 2, v0.t2018; RV32-NEXT: vor.vv v12, v20, v12, v0.t2019; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t2020; RV32-NEXT: vand.vv v16, v16, v8, v0.t2021; RV32-NEXT: vand.vv v8, v12, v8, v0.t2022; RV32-NEXT: vsll.vi v8, v8, 1, v0.t2023; RV32-NEXT: vor.vv v8, v16, v8, v0.t2024; RV32-NEXT: addi sp, sp, 162025; RV32-NEXT: .cfi_def_cfa_offset 02026; RV32-NEXT: ret2027;2028; RV64-LABEL: vp_bitreverse_nxv4i64:2029; RV64: # %bb.0:2030; RV64-NEXT: lui a1, 40802031; RV64-NEXT: li a3, 2552032; RV64-NEXT: li a2, 562033; RV64-NEXT: lui a4, 162034; RV64-NEXT: lui a5, 616812035; RV64-NEXT: lui a6, 2097152036; RV64-NEXT: lui a7, 3495252037; RV64-NEXT: addi a5, a5, -2412038; RV64-NEXT: addi a6, a6, 8192039; RV64-NEXT: addi a7, a7, 13652040; RV64-NEXT: slli t0, a5, 322041; RV64-NEXT: add t0, a5, t02042; RV64-NEXT: slli a5, a6, 322043; RV64-NEXT: add a6, a6, a52044; RV64-NEXT: slli a5, a7, 322045; RV64-NEXT: add a5, a7, a52046; RV64-NEXT: li a7, 402047; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma2048; RV64-NEXT: vand.vx v12, v8, a1, v0.t2049; RV64-NEXT: slli a3, a3, 242050; RV64-NEXT: addi a0, a4, -2562051; RV64-NEXT: vsll.vi v12, v12, 24, v0.t2052; RV64-NEXT: vand.vx v16, v8, a3, v0.t2053; RV64-NEXT: vsll.vi v16, v16, 8, v0.t2054; RV64-NEXT: vor.vv v12, v12, v16, v0.t2055; RV64-NEXT: vsll.vx v16, v8, a2, v0.t2056; RV64-NEXT: vand.vx v20, v8, a0, v0.t2057; RV64-NEXT: vsll.vx v20, v20, a7, v0.t2058; RV64-NEXT: vor.vv v16, v16, v20, v0.t2059; RV64-NEXT: vor.vv v12, v16, v12, v0.t2060; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t2061; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t2062; RV64-NEXT: vand.vx v20, v20, a0, v0.t2063; RV64-NEXT: vor.vv v16, v20, v16, v0.t2064; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t2065; RV64-NEXT: vand.vx v20, v20, a1, v0.t2066; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t2067; RV64-NEXT: vand.vx v8, v8, a3, v0.t2068; RV64-NEXT: vor.vv v8, v8, v20, v0.t2069; RV64-NEXT: vor.vv v8, v8, v16, v0.t2070; RV64-NEXT: vor.vv v8, v12, v8, v0.t2071; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t2072; RV64-NEXT: vand.vx v12, v12, t0, v0.t2073; RV64-NEXT: vand.vx v8, v8, t0, v0.t2074; RV64-NEXT: vsll.vi v8, v8, 4, v0.t2075; RV64-NEXT: vor.vv v8, v12, v8, v0.t2076; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t2077; RV64-NEXT: vand.vx v12, v12, a6, v0.t2078; RV64-NEXT: vand.vx v8, v8, a6, v0.t2079; RV64-NEXT: vsll.vi v8, v8, 2, v0.t2080; RV64-NEXT: vor.vv v8, v12, v8, v0.t2081; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t2082; RV64-NEXT: vand.vx v12, v12, a5, v0.t2083; RV64-NEXT: vand.vx v8, v8, a5, v0.t2084; RV64-NEXT: vsll.vi v8, v8, 1, v0.t2085; RV64-NEXT: vor.vv v8, v12, v8, v0.t2086; RV64-NEXT: ret2087;2088; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i64:2089; CHECK-ZVBB: # %bb.0:2090; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma2091; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t2092; CHECK-ZVBB-NEXT: ret2093 %v = call <vscale x 4 x i64> @llvm.vp.bitreverse.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)2094 ret <vscale x 4 x i64> %v2095}2096 2097define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {2098; RV32-LABEL: vp_bitreverse_nxv4i64_unmasked:2099; RV32: # %bb.0:2100; RV32-NEXT: addi sp, sp, -162101; RV32-NEXT: .cfi_def_cfa_offset 162102; RV32-NEXT: lui a1, 10444802103; RV32-NEXT: li a2, 562104; RV32-NEXT: lui a3, 162105; RV32-NEXT: li a4, 402106; RV32-NEXT: lui a5, 40802107; RV32-NEXT: addi a6, sp, 82108; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2109; RV32-NEXT: vsrl.vi v20, v8, 242110; RV32-NEXT: sw a1, 8(sp)2111; RV32-NEXT: sw zero, 12(sp)2112; RV32-NEXT: vsll.vx v16, v8, a22113; RV32-NEXT: addi a1, a3, -2562114; RV32-NEXT: vsrl.vx v12, v8, a22115; RV32-NEXT: vsrl.vx v24, v8, a42116; RV32-NEXT: vand.vx v28, v8, a12117; RV32-NEXT: vand.vx v24, v24, a12118; RV32-NEXT: vor.vv v12, v24, v122119; RV32-NEXT: vlse64.v v24, (a6), zero2120; RV32-NEXT: vsll.vx v28, v28, a42121; RV32-NEXT: vor.vv v16, v16, v282122; RV32-NEXT: vsrl.vi v28, v8, 82123; RV32-NEXT: vand.vx v20, v20, a52124; RV32-NEXT: vand.vv v28, v28, v242125; RV32-NEXT: vor.vv v20, v28, v202126; RV32-NEXT: lui a1, 616812127; RV32-NEXT: lui a2, 2097152128; RV32-NEXT: lui a3, 3495252129; RV32-NEXT: vand.vv v24, v8, v242130; RV32-NEXT: vand.vx v8, v8, a52131; RV32-NEXT: addi a1, a1, -2412132; RV32-NEXT: addi a2, a2, 8192133; RV32-NEXT: addi a3, a3, 13652134; RV32-NEXT: vsll.vi v8, v8, 242135; RV32-NEXT: vsll.vi v24, v24, 82136; RV32-NEXT: vor.vv v8, v8, v242137; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, ma2138; RV32-NEXT: vmv.v.x v24, a12139; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2140; RV32-NEXT: vor.vv v12, v20, v122141; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma2142; RV32-NEXT: vmv.v.x v20, a22143; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2144; RV32-NEXT: vor.vv v8, v16, v82145; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma2146; RV32-NEXT: vmv.v.x v16, a32147; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma2148; RV32-NEXT: vor.vv v8, v8, v122149; RV32-NEXT: vsrl.vi v12, v8, 42150; RV32-NEXT: vand.vv v8, v8, v242151; RV32-NEXT: vand.vv v12, v12, v242152; RV32-NEXT: vsll.vi v8, v8, 42153; RV32-NEXT: vor.vv v8, v12, v82154; RV32-NEXT: vsrl.vi v12, v8, 22155; RV32-NEXT: vand.vv v8, v8, v202156; RV32-NEXT: vand.vv v12, v12, v202157; RV32-NEXT: vsll.vi v8, v8, 22158; RV32-NEXT: vor.vv v8, v12, v82159; RV32-NEXT: vsrl.vi v12, v8, 12160; RV32-NEXT: vand.vv v8, v8, v162161; RV32-NEXT: vand.vv v12, v12, v162162; RV32-NEXT: vadd.vv v8, v8, v82163; RV32-NEXT: vor.vv v8, v12, v82164; RV32-NEXT: addi sp, sp, 162165; RV32-NEXT: .cfi_def_cfa_offset 02166; RV32-NEXT: ret2167;2168; RV64-LABEL: vp_bitreverse_nxv4i64_unmasked:2169; RV64: # %bb.0:2170; RV64-NEXT: lui a1, 40802171; RV64-NEXT: li a2, 2552172; RV64-NEXT: li a3, 562173; RV64-NEXT: lui a4, 162174; RV64-NEXT: li a5, 402175; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma2176; RV64-NEXT: vsrl.vi v16, v8, 242177; RV64-NEXT: vsrl.vi v20, v8, 82178; RV64-NEXT: addi a0, a4, -2562179; RV64-NEXT: vsrl.vx v12, v8, a32180; RV64-NEXT: vsrl.vx v24, v8, a52181; RV64-NEXT: vand.vx v24, v24, a02182; RV64-NEXT: vor.vv v12, v24, v122183; RV64-NEXT: vand.vx v24, v8, a12184; RV64-NEXT: slli a2, a2, 242185; RV64-NEXT: vand.vx v16, v16, a12186; RV64-NEXT: vsll.vi v24, v24, 242187; RV64-NEXT: vand.vx v20, v20, a22188; RV64-NEXT: vor.vv v16, v20, v162189; RV64-NEXT: vand.vx v20, v8, a22190; RV64-NEXT: vsll.vi v20, v20, 82191; RV64-NEXT: vor.vv v20, v24, v202192; RV64-NEXT: vsll.vx v24, v8, a32193; RV64-NEXT: vand.vx v8, v8, a02194; RV64-NEXT: vsll.vx v8, v8, a52195; RV64-NEXT: vor.vv v8, v24, v82196; RV64-NEXT: lui a0, 616812197; RV64-NEXT: lui a1, 2097152198; RV64-NEXT: lui a2, 3495252199; RV64-NEXT: addi a0, a0, -2412200; RV64-NEXT: addi a1, a1, 8192201; RV64-NEXT: addi a2, a2, 13652202; RV64-NEXT: slli a3, a0, 322203; RV64-NEXT: slli a4, a1, 322204; RV64-NEXT: add a0, a0, a32205; RV64-NEXT: slli a3, a2, 322206; RV64-NEXT: add a1, a1, a42207; RV64-NEXT: add a2, a2, a32208; RV64-NEXT: vor.vv v12, v16, v122209; RV64-NEXT: vor.vv v8, v8, v202210; RV64-NEXT: vor.vv v8, v8, v122211; RV64-NEXT: vsrl.vi v12, v8, 42212; RV64-NEXT: vand.vx v8, v8, a02213; RV64-NEXT: vand.vx v12, v12, a02214; RV64-NEXT: vsll.vi v8, v8, 42215; RV64-NEXT: vor.vv v8, v12, v82216; RV64-NEXT: vsrl.vi v12, v8, 22217; RV64-NEXT: vand.vx v8, v8, a12218; RV64-NEXT: vand.vx v12, v12, a12219; RV64-NEXT: vsll.vi v8, v8, 22220; RV64-NEXT: vor.vv v8, v12, v82221; RV64-NEXT: vsrl.vi v12, v8, 12222; RV64-NEXT: vand.vx v8, v8, a22223; RV64-NEXT: vand.vx v12, v12, a22224; RV64-NEXT: vadd.vv v8, v8, v82225; RV64-NEXT: vor.vv v8, v12, v82226; RV64-NEXT: ret2227;2228; CHECK-ZVBB-LABEL: vp_bitreverse_nxv4i64_unmasked:2229; CHECK-ZVBB: # %bb.0:2230; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma2231; CHECK-ZVBB-NEXT: vbrev.v v8, v82232; CHECK-ZVBB-NEXT: ret2233 %v = call <vscale x 4 x i64> @llvm.vp.bitreverse.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)2234 ret <vscale x 4 x i64> %v2235}2236 2237define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {2238; RV32-LABEL: vp_bitreverse_nxv7i64:2239; RV32: # %bb.0:2240; RV32-NEXT: addi sp, sp, -162241; RV32-NEXT: .cfi_def_cfa_offset 162242; RV32-NEXT: csrr a1, vlenb2243; RV32-NEXT: li a2, 242244; RV32-NEXT: mul a1, a1, a22245; RV32-NEXT: sub sp, sp, a12246; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb2247; RV32-NEXT: lui a1, 10444802248; RV32-NEXT: li a2, 562249; RV32-NEXT: lui a3, 162250; RV32-NEXT: li a4, 402251; RV32-NEXT: addi a5, sp, 82252; RV32-NEXT: sw a1, 8(sp)2253; RV32-NEXT: sw zero, 12(sp)2254; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2255; RV32-NEXT: vsll.vx v16, v8, a2, v0.t2256; RV32-NEXT: addi a1, a3, -2562257; RV32-NEXT: vand.vx v24, v8, a1, v0.t2258; RV32-NEXT: vsll.vx v24, v24, a4, v0.t2259; RV32-NEXT: vor.vv v16, v16, v24, v0.t2260; RV32-NEXT: csrr a3, vlenb2261; RV32-NEXT: slli a3, a3, 32262; RV32-NEXT: add a3, sp, a32263; RV32-NEXT: addi a3, a3, 162264; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2265; RV32-NEXT: vlse64.v v16, (a5), zero2266; RV32-NEXT: csrr a3, vlenb2267; RV32-NEXT: slli a3, a3, 42268; RV32-NEXT: add a3, sp, a32269; RV32-NEXT: addi a3, a3, 162270; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2271; RV32-NEXT: lui a3, 40802272; RV32-NEXT: vand.vx v16, v8, a3, v0.t2273; RV32-NEXT: vsll.vi v24, v16, 24, v0.t2274; RV32-NEXT: csrr a5, vlenb2275; RV32-NEXT: slli a5, a5, 42276; RV32-NEXT: add a5, sp, a52277; RV32-NEXT: addi a5, a5, 162278; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload2279; RV32-NEXT: vand.vv v16, v8, v16, v0.t2280; RV32-NEXT: vsll.vi v16, v16, 8, v0.t2281; RV32-NEXT: vor.vv v16, v24, v16, v0.t2282; RV32-NEXT: csrr a5, vlenb2283; RV32-NEXT: slli a5, a5, 32284; RV32-NEXT: add a5, sp, a52285; RV32-NEXT: addi a5, a5, 162286; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload2287; RV32-NEXT: vor.vv v16, v24, v16, v0.t2288; RV32-NEXT: csrr a5, vlenb2289; RV32-NEXT: slli a5, a5, 32290; RV32-NEXT: add a5, sp, a52291; RV32-NEXT: addi a5, a5, 162292; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill2293; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t2294; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t2295; RV32-NEXT: vand.vx v24, v24, a1, v0.t2296; RV32-NEXT: vor.vv v16, v24, v16, v0.t2297; RV32-NEXT: addi a1, sp, 162298; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2299; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t2300; RV32-NEXT: vand.vx v24, v24, a3, v0.t2301; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t2302; RV32-NEXT: csrr a1, vlenb2303; RV32-NEXT: slli a1, a1, 42304; RV32-NEXT: add a1, sp, a12305; RV32-NEXT: addi a1, a1, 162306; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2307; RV32-NEXT: vand.vv v8, v8, v16, v0.t2308; RV32-NEXT: vor.vv v8, v8, v24, v0.t2309; RV32-NEXT: addi a1, sp, 162310; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2311; RV32-NEXT: vor.vv v8, v8, v16, v0.t2312; RV32-NEXT: lui a1, 616812313; RV32-NEXT: lui a2, 2097152314; RV32-NEXT: lui a3, 3495252315; RV32-NEXT: addi a1, a1, -2412316; RV32-NEXT: addi a2, a2, 8192317; RV32-NEXT: addi a3, a3, 13652318; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2319; RV32-NEXT: vmv.v.x v24, a12320; RV32-NEXT: csrr a1, vlenb2321; RV32-NEXT: slli a1, a1, 32322; RV32-NEXT: add a1, sp, a12323; RV32-NEXT: addi a1, a1, 162324; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2325; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2326; RV32-NEXT: vor.vv v8, v16, v8, v0.t2327; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2328; RV32-NEXT: vand.vv v16, v16, v24, v0.t2329; RV32-NEXT: vand.vv v24, v8, v24, v0.t2330; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2331; RV32-NEXT: vmv.v.x v8, a22332; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2333; RV32-NEXT: vsll.vi v24, v24, 4, v0.t2334; RV32-NEXT: vor.vv v24, v16, v24, v0.t2335; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t2336; RV32-NEXT: vand.vv v16, v16, v8, v0.t2337; RV32-NEXT: vand.vv v24, v24, v8, v0.t2338; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2339; RV32-NEXT: vmv.v.x v8, a32340; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2341; RV32-NEXT: vsll.vi v24, v24, 2, v0.t2342; RV32-NEXT: vor.vv v16, v16, v24, v0.t2343; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t2344; RV32-NEXT: vand.vv v24, v24, v8, v0.t2345; RV32-NEXT: vand.vv v8, v16, v8, v0.t2346; RV32-NEXT: vsll.vi v8, v8, 1, v0.t2347; RV32-NEXT: vor.vv v8, v24, v8, v0.t2348; RV32-NEXT: csrr a0, vlenb2349; RV32-NEXT: li a1, 242350; RV32-NEXT: mul a0, a0, a12351; RV32-NEXT: add sp, sp, a02352; RV32-NEXT: .cfi_def_cfa sp, 162353; RV32-NEXT: addi sp, sp, 162354; RV32-NEXT: .cfi_def_cfa_offset 02355; RV32-NEXT: ret2356;2357; RV64-LABEL: vp_bitreverse_nxv7i64:2358; RV64: # %bb.0:2359; RV64-NEXT: addi sp, sp, -162360; RV64-NEXT: .cfi_def_cfa_offset 162361; RV64-NEXT: csrr a1, vlenb2362; RV64-NEXT: slli a1, a1, 32363; RV64-NEXT: sub sp, sp, a12364; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2365; RV64-NEXT: lui a1, 40802366; RV64-NEXT: li a2, 2552367; RV64-NEXT: li a3, 562368; RV64-NEXT: lui a4, 162369; RV64-NEXT: li a5, 402370; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2371; RV64-NEXT: vand.vx v16, v8, a1, v0.t2372; RV64-NEXT: slli a2, a2, 242373; RV64-NEXT: addi a0, a4, -2562374; RV64-NEXT: vsll.vi v16, v16, 24, v0.t2375; RV64-NEXT: vand.vx v24, v8, a2, v0.t2376; RV64-NEXT: vsll.vi v24, v24, 8, v0.t2377; RV64-NEXT: vor.vv v16, v16, v24, v0.t2378; RV64-NEXT: addi a4, sp, 162379; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2380; RV64-NEXT: vsll.vx v24, v8, a3, v0.t2381; RV64-NEXT: vand.vx v16, v8, a0, v0.t2382; RV64-NEXT: vsll.vx v16, v16, a5, v0.t2383; RV64-NEXT: vor.vv v16, v24, v16, v0.t2384; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload2385; RV64-NEXT: vor.vv v16, v16, v24, v0.t2386; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2387; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t2388; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t2389; RV64-NEXT: vand.vx v16, v16, a0, v0.t2390; RV64-NEXT: vor.vv v24, v16, v24, v0.t2391; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t2392; RV64-NEXT: vand.vx v16, v16, a1, v0.t2393; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t2394; RV64-NEXT: vand.vx v8, v8, a2, v0.t2395; RV64-NEXT: vor.vv v8, v8, v16, v0.t2396; RV64-NEXT: vor.vv v8, v8, v24, v0.t2397; RV64-NEXT: lui a0, 616812398; RV64-NEXT: lui a1, 2097152399; RV64-NEXT: lui a2, 3495252400; RV64-NEXT: addi a0, a0, -2412401; RV64-NEXT: addi a1, a1, 8192402; RV64-NEXT: addi a2, a2, 13652403; RV64-NEXT: slli a3, a0, 322404; RV64-NEXT: slli a4, a1, 322405; RV64-NEXT: add a0, a0, a32406; RV64-NEXT: slli a3, a2, 322407; RV64-NEXT: add a1, a1, a42408; RV64-NEXT: add a2, a2, a32409; RV64-NEXT: addi a3, sp, 162410; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2411; RV64-NEXT: vor.vv v8, v16, v8, v0.t2412; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t2413; RV64-NEXT: vand.vx v16, v16, a0, v0.t2414; RV64-NEXT: vand.vx v8, v8, a0, v0.t2415; RV64-NEXT: vsll.vi v8, v8, 4, v0.t2416; RV64-NEXT: vor.vv v8, v16, v8, v0.t2417; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t2418; RV64-NEXT: vand.vx v16, v16, a1, v0.t2419; RV64-NEXT: vand.vx v8, v8, a1, v0.t2420; RV64-NEXT: vsll.vi v8, v8, 2, v0.t2421; RV64-NEXT: vor.vv v8, v16, v8, v0.t2422; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t2423; RV64-NEXT: vand.vx v16, v16, a2, v0.t2424; RV64-NEXT: vand.vx v8, v8, a2, v0.t2425; RV64-NEXT: vsll.vi v8, v8, 1, v0.t2426; RV64-NEXT: vor.vv v8, v16, v8, v0.t2427; RV64-NEXT: csrr a0, vlenb2428; RV64-NEXT: slli a0, a0, 32429; RV64-NEXT: add sp, sp, a02430; RV64-NEXT: .cfi_def_cfa sp, 162431; RV64-NEXT: addi sp, sp, 162432; RV64-NEXT: .cfi_def_cfa_offset 02433; RV64-NEXT: ret2434;2435; CHECK-ZVBB-LABEL: vp_bitreverse_nxv7i64:2436; CHECK-ZVBB: # %bb.0:2437; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2438; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t2439; CHECK-ZVBB-NEXT: ret2440 %v = call <vscale x 7 x i64> @llvm.vp.bitreverse.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl)2441 ret <vscale x 7 x i64> %v2442}2443 2444define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {2445; RV32-LABEL: vp_bitreverse_nxv7i64_unmasked:2446; RV32: # %bb.0:2447; RV32-NEXT: addi sp, sp, -162448; RV32-NEXT: .cfi_def_cfa_offset 162449; RV32-NEXT: csrr a1, vlenb2450; RV32-NEXT: slli a1, a1, 42451; RV32-NEXT: sub sp, sp, a12452; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2453; RV32-NEXT: lui a1, 10444802454; RV32-NEXT: li a2, 562455; RV32-NEXT: lui a3, 162456; RV32-NEXT: li a4, 402457; RV32-NEXT: lui a5, 40802458; RV32-NEXT: addi a6, sp, 82459; RV32-NEXT: sw a1, 8(sp)2460; RV32-NEXT: sw zero, 12(sp)2461; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2462; RV32-NEXT: vsll.vx v16, v8, a22463; RV32-NEXT: addi a1, a3, -2562464; RV32-NEXT: vsrl.vx v24, v8, a22465; RV32-NEXT: vsrl.vx v0, v8, a42466; RV32-NEXT: vand.vx v0, v0, a12467; RV32-NEXT: vor.vv v24, v0, v242468; RV32-NEXT: addi a2, sp, 162469; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill2470; RV32-NEXT: vand.vx v24, v8, a12471; RV32-NEXT: vsll.vx v24, v24, a42472; RV32-NEXT: vor.vv v16, v16, v242473; RV32-NEXT: csrr a1, vlenb2474; RV32-NEXT: slli a1, a1, 32475; RV32-NEXT: add a1, sp, a12476; RV32-NEXT: addi a1, a1, 162477; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2478; RV32-NEXT: vlse64.v v24, (a6), zero2479; RV32-NEXT: vsrl.vi v16, v8, 242480; RV32-NEXT: vand.vx v16, v16, a52481; RV32-NEXT: vsrl.vi v0, v8, 82482; RV32-NEXT: vand.vv v0, v0, v242483; RV32-NEXT: vor.vv v16, v0, v162484; RV32-NEXT: vand.vv v24, v8, v242485; RV32-NEXT: vand.vx v8, v8, a52486; RV32-NEXT: vsll.vi v8, v8, 242487; RV32-NEXT: vsll.vi v24, v24, 82488; RV32-NEXT: vor.vv v24, v8, v242489; RV32-NEXT: addi a1, sp, 162490; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload2491; RV32-NEXT: vor.vv v8, v16, v82492; RV32-NEXT: lui a1, 616812493; RV32-NEXT: lui a2, 2097152494; RV32-NEXT: lui a3, 3495252495; RV32-NEXT: addi a1, a1, -2412496; RV32-NEXT: addi a2, a2, 8192497; RV32-NEXT: addi a3, a3, 13652498; RV32-NEXT: csrr a4, vlenb2499; RV32-NEXT: slli a4, a4, 32500; RV32-NEXT: add a4, sp, a42501; RV32-NEXT: addi a4, a4, 162502; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload2503; RV32-NEXT: vor.vv v16, v16, v242504; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2505; RV32-NEXT: vmv.v.x v24, a12506; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2507; RV32-NEXT: vor.vv v8, v16, v82508; RV32-NEXT: vsrl.vi v16, v8, 42509; RV32-NEXT: vand.vv v8, v8, v242510; RV32-NEXT: vand.vv v16, v16, v242511; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2512; RV32-NEXT: vmv.v.x v24, a22513; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2514; RV32-NEXT: vsll.vi v8, v8, 42515; RV32-NEXT: vor.vv v8, v16, v82516; RV32-NEXT: vsrl.vi v16, v8, 22517; RV32-NEXT: vand.vv v8, v8, v242518; RV32-NEXT: vand.vv v16, v16, v242519; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2520; RV32-NEXT: vmv.v.x v24, a32521; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2522; RV32-NEXT: vsll.vi v8, v8, 22523; RV32-NEXT: vor.vv v8, v16, v82524; RV32-NEXT: vsrl.vi v16, v8, 12525; RV32-NEXT: vand.vv v8, v8, v242526; RV32-NEXT: vand.vv v16, v16, v242527; RV32-NEXT: vadd.vv v8, v8, v82528; RV32-NEXT: vor.vv v8, v16, v82529; RV32-NEXT: csrr a0, vlenb2530; RV32-NEXT: slli a0, a0, 42531; RV32-NEXT: add sp, sp, a02532; RV32-NEXT: .cfi_def_cfa sp, 162533; RV32-NEXT: addi sp, sp, 162534; RV32-NEXT: .cfi_def_cfa_offset 02535; RV32-NEXT: ret2536;2537; RV64-LABEL: vp_bitreverse_nxv7i64_unmasked:2538; RV64: # %bb.0:2539; RV64-NEXT: addi sp, sp, -162540; RV64-NEXT: .cfi_def_cfa_offset 162541; RV64-NEXT: csrr a1, vlenb2542; RV64-NEXT: slli a1, a1, 32543; RV64-NEXT: sub sp, sp, a12544; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2545; RV64-NEXT: lui a1, 40802546; RV64-NEXT: li a2, 2552547; RV64-NEXT: li a3, 562548; RV64-NEXT: lui a4, 162549; RV64-NEXT: li a5, 402550; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2551; RV64-NEXT: vsrl.vi v24, v8, 242552; RV64-NEXT: addi a0, a4, -2562553; RV64-NEXT: vsrl.vx v16, v8, a32554; RV64-NEXT: vsrl.vx v0, v8, a52555; RV64-NEXT: vand.vx v0, v0, a02556; RV64-NEXT: vor.vv v16, v0, v162557; RV64-NEXT: addi a4, sp, 162558; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2559; RV64-NEXT: vsrl.vi v0, v8, 82560; RV64-NEXT: slli a2, a2, 242561; RV64-NEXT: vand.vx v24, v24, a12562; RV64-NEXT: vand.vx v0, v0, a22563; RV64-NEXT: vor.vv v24, v0, v242564; RV64-NEXT: vand.vx v0, v8, a12565; RV64-NEXT: vsll.vi v0, v0, 242566; RV64-NEXT: vand.vx v16, v8, a22567; RV64-NEXT: vsll.vi v16, v16, 82568; RV64-NEXT: vor.vv v0, v0, v162569; RV64-NEXT: vsll.vx v16, v8, a32570; RV64-NEXT: vand.vx v8, v8, a02571; RV64-NEXT: vsll.vx v8, v8, a52572; RV64-NEXT: vor.vv v8, v16, v82573; RV64-NEXT: lui a0, 616812574; RV64-NEXT: lui a1, 2097152575; RV64-NEXT: lui a2, 3495252576; RV64-NEXT: addi a0, a0, -2412577; RV64-NEXT: addi a1, a1, 8192578; RV64-NEXT: addi a2, a2, 13652579; RV64-NEXT: slli a3, a0, 322580; RV64-NEXT: slli a4, a1, 322581; RV64-NEXT: add a0, a0, a32582; RV64-NEXT: slli a3, a2, 322583; RV64-NEXT: add a1, a1, a42584; RV64-NEXT: add a2, a2, a32585; RV64-NEXT: addi a3, sp, 162586; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2587; RV64-NEXT: vor.vv v16, v24, v162588; RV64-NEXT: vor.vv v8, v8, v02589; RV64-NEXT: vor.vv v8, v8, v162590; RV64-NEXT: vsrl.vi v16, v8, 42591; RV64-NEXT: vand.vx v8, v8, a02592; RV64-NEXT: vand.vx v16, v16, a02593; RV64-NEXT: vsll.vi v8, v8, 42594; RV64-NEXT: vor.vv v8, v16, v82595; RV64-NEXT: vsrl.vi v16, v8, 22596; RV64-NEXT: vand.vx v8, v8, a12597; RV64-NEXT: vand.vx v16, v16, a12598; RV64-NEXT: vsll.vi v8, v8, 22599; RV64-NEXT: vor.vv v8, v16, v82600; RV64-NEXT: vsrl.vi v16, v8, 12601; RV64-NEXT: vand.vx v8, v8, a22602; RV64-NEXT: vand.vx v16, v16, a22603; RV64-NEXT: vadd.vv v8, v8, v82604; RV64-NEXT: vor.vv v8, v16, v82605; RV64-NEXT: csrr a0, vlenb2606; RV64-NEXT: slli a0, a0, 32607; RV64-NEXT: add sp, sp, a02608; RV64-NEXT: .cfi_def_cfa sp, 162609; RV64-NEXT: addi sp, sp, 162610; RV64-NEXT: .cfi_def_cfa_offset 02611; RV64-NEXT: ret2612;2613; CHECK-ZVBB-LABEL: vp_bitreverse_nxv7i64_unmasked:2614; CHECK-ZVBB: # %bb.0:2615; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2616; CHECK-ZVBB-NEXT: vbrev.v v8, v82617; CHECK-ZVBB-NEXT: ret2618 %v = call <vscale x 7 x i64> @llvm.vp.bitreverse.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)2619 ret <vscale x 7 x i64> %v2620}2621 2622define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {2623; RV32-LABEL: vp_bitreverse_nxv8i64:2624; RV32: # %bb.0:2625; RV32-NEXT: addi sp, sp, -162626; RV32-NEXT: .cfi_def_cfa_offset 162627; RV32-NEXT: csrr a1, vlenb2628; RV32-NEXT: li a2, 242629; RV32-NEXT: mul a1, a1, a22630; RV32-NEXT: sub sp, sp, a12631; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb2632; RV32-NEXT: lui a1, 10444802633; RV32-NEXT: li a2, 562634; RV32-NEXT: lui a3, 162635; RV32-NEXT: li a4, 402636; RV32-NEXT: addi a5, sp, 82637; RV32-NEXT: sw a1, 8(sp)2638; RV32-NEXT: sw zero, 12(sp)2639; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2640; RV32-NEXT: vsll.vx v16, v8, a2, v0.t2641; RV32-NEXT: addi a1, a3, -2562642; RV32-NEXT: vand.vx v24, v8, a1, v0.t2643; RV32-NEXT: vsll.vx v24, v24, a4, v0.t2644; RV32-NEXT: vor.vv v16, v16, v24, v0.t2645; RV32-NEXT: csrr a3, vlenb2646; RV32-NEXT: slli a3, a3, 32647; RV32-NEXT: add a3, sp, a32648; RV32-NEXT: addi a3, a3, 162649; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2650; RV32-NEXT: vlse64.v v16, (a5), zero2651; RV32-NEXT: csrr a3, vlenb2652; RV32-NEXT: slli a3, a3, 42653; RV32-NEXT: add a3, sp, a32654; RV32-NEXT: addi a3, a3, 162655; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill2656; RV32-NEXT: lui a3, 40802657; RV32-NEXT: vand.vx v16, v8, a3, v0.t2658; RV32-NEXT: vsll.vi v24, v16, 24, v0.t2659; RV32-NEXT: csrr a5, vlenb2660; RV32-NEXT: slli a5, a5, 42661; RV32-NEXT: add a5, sp, a52662; RV32-NEXT: addi a5, a5, 162663; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload2664; RV32-NEXT: vand.vv v16, v8, v16, v0.t2665; RV32-NEXT: vsll.vi v16, v16, 8, v0.t2666; RV32-NEXT: vor.vv v16, v24, v16, v0.t2667; RV32-NEXT: csrr a5, vlenb2668; RV32-NEXT: slli a5, a5, 32669; RV32-NEXT: add a5, sp, a52670; RV32-NEXT: addi a5, a5, 162671; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload2672; RV32-NEXT: vor.vv v16, v24, v16, v0.t2673; RV32-NEXT: csrr a5, vlenb2674; RV32-NEXT: slli a5, a5, 32675; RV32-NEXT: add a5, sp, a52676; RV32-NEXT: addi a5, a5, 162677; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill2678; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t2679; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t2680; RV32-NEXT: vand.vx v24, v24, a1, v0.t2681; RV32-NEXT: vor.vv v16, v24, v16, v0.t2682; RV32-NEXT: addi a1, sp, 162683; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2684; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t2685; RV32-NEXT: vand.vx v24, v24, a3, v0.t2686; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t2687; RV32-NEXT: csrr a1, vlenb2688; RV32-NEXT: slli a1, a1, 42689; RV32-NEXT: add a1, sp, a12690; RV32-NEXT: addi a1, a1, 162691; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2692; RV32-NEXT: vand.vv v8, v8, v16, v0.t2693; RV32-NEXT: vor.vv v8, v8, v24, v0.t2694; RV32-NEXT: addi a1, sp, 162695; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2696; RV32-NEXT: vor.vv v8, v8, v16, v0.t2697; RV32-NEXT: lui a1, 616812698; RV32-NEXT: lui a2, 2097152699; RV32-NEXT: lui a3, 3495252700; RV32-NEXT: addi a1, a1, -2412701; RV32-NEXT: addi a2, a2, 8192702; RV32-NEXT: addi a3, a3, 13652703; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2704; RV32-NEXT: vmv.v.x v24, a12705; RV32-NEXT: csrr a1, vlenb2706; RV32-NEXT: slli a1, a1, 32707; RV32-NEXT: add a1, sp, a12708; RV32-NEXT: addi a1, a1, 162709; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload2710; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2711; RV32-NEXT: vor.vv v8, v16, v8, v0.t2712; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t2713; RV32-NEXT: vand.vv v16, v16, v24, v0.t2714; RV32-NEXT: vand.vv v24, v8, v24, v0.t2715; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2716; RV32-NEXT: vmv.v.x v8, a22717; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2718; RV32-NEXT: vsll.vi v24, v24, 4, v0.t2719; RV32-NEXT: vor.vv v24, v16, v24, v0.t2720; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t2721; RV32-NEXT: vand.vv v16, v16, v8, v0.t2722; RV32-NEXT: vand.vv v24, v24, v8, v0.t2723; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2724; RV32-NEXT: vmv.v.x v8, a32725; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2726; RV32-NEXT: vsll.vi v24, v24, 2, v0.t2727; RV32-NEXT: vor.vv v16, v16, v24, v0.t2728; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t2729; RV32-NEXT: vand.vv v24, v24, v8, v0.t2730; RV32-NEXT: vand.vv v8, v16, v8, v0.t2731; RV32-NEXT: vsll.vi v8, v8, 1, v0.t2732; RV32-NEXT: vor.vv v8, v24, v8, v0.t2733; RV32-NEXT: csrr a0, vlenb2734; RV32-NEXT: li a1, 242735; RV32-NEXT: mul a0, a0, a12736; RV32-NEXT: add sp, sp, a02737; RV32-NEXT: .cfi_def_cfa sp, 162738; RV32-NEXT: addi sp, sp, 162739; RV32-NEXT: .cfi_def_cfa_offset 02740; RV32-NEXT: ret2741;2742; RV64-LABEL: vp_bitreverse_nxv8i64:2743; RV64: # %bb.0:2744; RV64-NEXT: addi sp, sp, -162745; RV64-NEXT: .cfi_def_cfa_offset 162746; RV64-NEXT: csrr a1, vlenb2747; RV64-NEXT: slli a1, a1, 32748; RV64-NEXT: sub sp, sp, a12749; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2750; RV64-NEXT: lui a1, 40802751; RV64-NEXT: li a2, 2552752; RV64-NEXT: li a3, 562753; RV64-NEXT: lui a4, 162754; RV64-NEXT: li a5, 402755; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2756; RV64-NEXT: vand.vx v16, v8, a1, v0.t2757; RV64-NEXT: slli a2, a2, 242758; RV64-NEXT: addi a0, a4, -2562759; RV64-NEXT: vsll.vi v16, v16, 24, v0.t2760; RV64-NEXT: vand.vx v24, v8, a2, v0.t2761; RV64-NEXT: vsll.vi v24, v24, 8, v0.t2762; RV64-NEXT: vor.vv v16, v16, v24, v0.t2763; RV64-NEXT: addi a4, sp, 162764; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2765; RV64-NEXT: vsll.vx v24, v8, a3, v0.t2766; RV64-NEXT: vand.vx v16, v8, a0, v0.t2767; RV64-NEXT: vsll.vx v16, v16, a5, v0.t2768; RV64-NEXT: vor.vv v16, v24, v16, v0.t2769; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload2770; RV64-NEXT: vor.vv v16, v16, v24, v0.t2771; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2772; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t2773; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t2774; RV64-NEXT: vand.vx v16, v16, a0, v0.t2775; RV64-NEXT: vor.vv v24, v16, v24, v0.t2776; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t2777; RV64-NEXT: vand.vx v16, v16, a1, v0.t2778; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t2779; RV64-NEXT: vand.vx v8, v8, a2, v0.t2780; RV64-NEXT: vor.vv v8, v8, v16, v0.t2781; RV64-NEXT: vor.vv v8, v8, v24, v0.t2782; RV64-NEXT: lui a0, 616812783; RV64-NEXT: lui a1, 2097152784; RV64-NEXT: lui a2, 3495252785; RV64-NEXT: addi a0, a0, -2412786; RV64-NEXT: addi a1, a1, 8192787; RV64-NEXT: addi a2, a2, 13652788; RV64-NEXT: slli a3, a0, 322789; RV64-NEXT: slli a4, a1, 322790; RV64-NEXT: add a0, a0, a32791; RV64-NEXT: slli a3, a2, 322792; RV64-NEXT: add a1, a1, a42793; RV64-NEXT: add a2, a2, a32794; RV64-NEXT: addi a3, sp, 162795; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2796; RV64-NEXT: vor.vv v8, v16, v8, v0.t2797; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t2798; RV64-NEXT: vand.vx v16, v16, a0, v0.t2799; RV64-NEXT: vand.vx v8, v8, a0, v0.t2800; RV64-NEXT: vsll.vi v8, v8, 4, v0.t2801; RV64-NEXT: vor.vv v8, v16, v8, v0.t2802; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t2803; RV64-NEXT: vand.vx v16, v16, a1, v0.t2804; RV64-NEXT: vand.vx v8, v8, a1, v0.t2805; RV64-NEXT: vsll.vi v8, v8, 2, v0.t2806; RV64-NEXT: vor.vv v8, v16, v8, v0.t2807; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t2808; RV64-NEXT: vand.vx v16, v16, a2, v0.t2809; RV64-NEXT: vand.vx v8, v8, a2, v0.t2810; RV64-NEXT: vsll.vi v8, v8, 1, v0.t2811; RV64-NEXT: vor.vv v8, v16, v8, v0.t2812; RV64-NEXT: csrr a0, vlenb2813; RV64-NEXT: slli a0, a0, 32814; RV64-NEXT: add sp, sp, a02815; RV64-NEXT: .cfi_def_cfa sp, 162816; RV64-NEXT: addi sp, sp, 162817; RV64-NEXT: .cfi_def_cfa_offset 02818; RV64-NEXT: ret2819;2820; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i64:2821; CHECK-ZVBB: # %bb.0:2822; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma2823; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t2824; CHECK-ZVBB-NEXT: ret2825 %v = call <vscale x 8 x i64> @llvm.vp.bitreverse.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)2826 ret <vscale x 8 x i64> %v2827}2828 2829define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {2830; RV32-LABEL: vp_bitreverse_nxv8i64_unmasked:2831; RV32: # %bb.0:2832; RV32-NEXT: addi sp, sp, -162833; RV32-NEXT: .cfi_def_cfa_offset 162834; RV32-NEXT: csrr a1, vlenb2835; RV32-NEXT: slli a1, a1, 42836; RV32-NEXT: sub sp, sp, a12837; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb2838; RV32-NEXT: lui a1, 10444802839; RV32-NEXT: li a2, 562840; RV32-NEXT: lui a3, 162841; RV32-NEXT: li a4, 402842; RV32-NEXT: lui a5, 40802843; RV32-NEXT: addi a6, sp, 82844; RV32-NEXT: sw a1, 8(sp)2845; RV32-NEXT: sw zero, 12(sp)2846; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2847; RV32-NEXT: vsll.vx v16, v8, a22848; RV32-NEXT: addi a1, a3, -2562849; RV32-NEXT: vsrl.vx v24, v8, a22850; RV32-NEXT: vsrl.vx v0, v8, a42851; RV32-NEXT: vand.vx v0, v0, a12852; RV32-NEXT: vor.vv v24, v0, v242853; RV32-NEXT: addi a2, sp, 162854; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill2855; RV32-NEXT: vand.vx v24, v8, a12856; RV32-NEXT: vsll.vx v24, v24, a42857; RV32-NEXT: vor.vv v16, v16, v242858; RV32-NEXT: csrr a1, vlenb2859; RV32-NEXT: slli a1, a1, 32860; RV32-NEXT: add a1, sp, a12861; RV32-NEXT: addi a1, a1, 162862; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill2863; RV32-NEXT: vlse64.v v24, (a6), zero2864; RV32-NEXT: vsrl.vi v16, v8, 242865; RV32-NEXT: vand.vx v16, v16, a52866; RV32-NEXT: vsrl.vi v0, v8, 82867; RV32-NEXT: vand.vv v0, v0, v242868; RV32-NEXT: vor.vv v16, v0, v162869; RV32-NEXT: vand.vv v24, v8, v242870; RV32-NEXT: vand.vx v8, v8, a52871; RV32-NEXT: vsll.vi v8, v8, 242872; RV32-NEXT: vsll.vi v24, v24, 82873; RV32-NEXT: vor.vv v24, v8, v242874; RV32-NEXT: addi a1, sp, 162875; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload2876; RV32-NEXT: vor.vv v8, v16, v82877; RV32-NEXT: lui a1, 616812878; RV32-NEXT: lui a2, 2097152879; RV32-NEXT: lui a3, 3495252880; RV32-NEXT: addi a1, a1, -2412881; RV32-NEXT: addi a2, a2, 8192882; RV32-NEXT: addi a3, a3, 13652883; RV32-NEXT: csrr a4, vlenb2884; RV32-NEXT: slli a4, a4, 32885; RV32-NEXT: add a4, sp, a42886; RV32-NEXT: addi a4, a4, 162887; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload2888; RV32-NEXT: vor.vv v16, v16, v242889; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma2890; RV32-NEXT: vmv.v.x v24, a12891; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2892; RV32-NEXT: vor.vv v8, v16, v82893; RV32-NEXT: vsrl.vi v16, v8, 42894; RV32-NEXT: vand.vv v8, v8, v242895; RV32-NEXT: vand.vv v16, v16, v242896; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2897; RV32-NEXT: vmv.v.x v24, a22898; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2899; RV32-NEXT: vsll.vi v8, v8, 42900; RV32-NEXT: vor.vv v8, v16, v82901; RV32-NEXT: vsrl.vi v16, v8, 22902; RV32-NEXT: vand.vv v8, v8, v242903; RV32-NEXT: vand.vv v16, v16, v242904; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma2905; RV32-NEXT: vmv.v.x v24, a32906; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma2907; RV32-NEXT: vsll.vi v8, v8, 22908; RV32-NEXT: vor.vv v8, v16, v82909; RV32-NEXT: vsrl.vi v16, v8, 12910; RV32-NEXT: vand.vv v8, v8, v242911; RV32-NEXT: vand.vv v16, v16, v242912; RV32-NEXT: vadd.vv v8, v8, v82913; RV32-NEXT: vor.vv v8, v16, v82914; RV32-NEXT: csrr a0, vlenb2915; RV32-NEXT: slli a0, a0, 42916; RV32-NEXT: add sp, sp, a02917; RV32-NEXT: .cfi_def_cfa sp, 162918; RV32-NEXT: addi sp, sp, 162919; RV32-NEXT: .cfi_def_cfa_offset 02920; RV32-NEXT: ret2921;2922; RV64-LABEL: vp_bitreverse_nxv8i64_unmasked:2923; RV64: # %bb.0:2924; RV64-NEXT: addi sp, sp, -162925; RV64-NEXT: .cfi_def_cfa_offset 162926; RV64-NEXT: csrr a1, vlenb2927; RV64-NEXT: slli a1, a1, 32928; RV64-NEXT: sub sp, sp, a12929; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb2930; RV64-NEXT: lui a1, 40802931; RV64-NEXT: li a2, 2552932; RV64-NEXT: li a3, 562933; RV64-NEXT: lui a4, 162934; RV64-NEXT: li a5, 402935; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma2936; RV64-NEXT: vsrl.vi v24, v8, 242937; RV64-NEXT: addi a0, a4, -2562938; RV64-NEXT: vsrl.vx v16, v8, a32939; RV64-NEXT: vsrl.vx v0, v8, a52940; RV64-NEXT: vand.vx v0, v0, a02941; RV64-NEXT: vor.vv v16, v0, v162942; RV64-NEXT: addi a4, sp, 162943; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill2944; RV64-NEXT: vsrl.vi v0, v8, 82945; RV64-NEXT: slli a2, a2, 242946; RV64-NEXT: vand.vx v24, v24, a12947; RV64-NEXT: vand.vx v0, v0, a22948; RV64-NEXT: vor.vv v24, v0, v242949; RV64-NEXT: vand.vx v0, v8, a12950; RV64-NEXT: vsll.vi v0, v0, 242951; RV64-NEXT: vand.vx v16, v8, a22952; RV64-NEXT: vsll.vi v16, v16, 82953; RV64-NEXT: vor.vv v0, v0, v162954; RV64-NEXT: vsll.vx v16, v8, a32955; RV64-NEXT: vand.vx v8, v8, a02956; RV64-NEXT: vsll.vx v8, v8, a52957; RV64-NEXT: vor.vv v8, v16, v82958; RV64-NEXT: lui a0, 616812959; RV64-NEXT: lui a1, 2097152960; RV64-NEXT: lui a2, 3495252961; RV64-NEXT: addi a0, a0, -2412962; RV64-NEXT: addi a1, a1, 8192963; RV64-NEXT: addi a2, a2, 13652964; RV64-NEXT: slli a3, a0, 322965; RV64-NEXT: slli a4, a1, 322966; RV64-NEXT: add a0, a0, a32967; RV64-NEXT: slli a3, a2, 322968; RV64-NEXT: add a1, a1, a42969; RV64-NEXT: add a2, a2, a32970; RV64-NEXT: addi a3, sp, 162971; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload2972; RV64-NEXT: vor.vv v16, v24, v162973; RV64-NEXT: vor.vv v8, v8, v02974; RV64-NEXT: vor.vv v8, v8, v162975; RV64-NEXT: vsrl.vi v16, v8, 42976; RV64-NEXT: vand.vx v8, v8, a02977; RV64-NEXT: vand.vx v16, v16, a02978; RV64-NEXT: vsll.vi v8, v8, 42979; RV64-NEXT: vor.vv v8, v16, v82980; RV64-NEXT: vsrl.vi v16, v8, 22981; RV64-NEXT: vand.vx v8, v8, a12982; RV64-NEXT: vand.vx v16, v16, a12983; RV64-NEXT: vsll.vi v8, v8, 22984; RV64-NEXT: vor.vv v8, v16, v82985; RV64-NEXT: vsrl.vi v16, v8, 12986; RV64-NEXT: vand.vx v8, v8, a22987; RV64-NEXT: vand.vx v16, v16, a22988; RV64-NEXT: vadd.vv v8, v8, v82989; RV64-NEXT: vor.vv v8, v16, v82990; RV64-NEXT: csrr a0, vlenb2991; RV64-NEXT: slli a0, a0, 32992; RV64-NEXT: add sp, sp, a02993; RV64-NEXT: .cfi_def_cfa sp, 162994; RV64-NEXT: addi sp, sp, 162995; RV64-NEXT: .cfi_def_cfa_offset 02996; RV64-NEXT: ret2997;2998; CHECK-ZVBB-LABEL: vp_bitreverse_nxv8i64_unmasked:2999; CHECK-ZVBB: # %bb.0:3000; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma3001; CHECK-ZVBB-NEXT: vbrev.v v8, v83002; CHECK-ZVBB-NEXT: ret3003 %v = call <vscale x 8 x i64> @llvm.vp.bitreverse.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)3004 ret <vscale x 8 x i64> %v3005}3006 3007; Test splitting. Use i16 version for easier check.3008 3009define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {3010; CHECK-LABEL: vp_bitreverse_nxv64i16:3011; CHECK: # %bb.0:3012; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma3013; CHECK-NEXT: vmv1r.v v7, v03014; CHECK-NEXT: csrr a3, vlenb3015; CHECK-NEXT: lui a1, 13016; CHECK-NEXT: lui a2, 33017; CHECK-NEXT: srli a4, a3, 13018; CHECK-NEXT: slli a3, a3, 23019; CHECK-NEXT: vslidedown.vx v0, v0, a43020; CHECK-NEXT: sub a4, a0, a33021; CHECK-NEXT: sltu a5, a0, a43022; CHECK-NEXT: addi a5, a5, -13023; CHECK-NEXT: and a5, a5, a43024; CHECK-NEXT: lui a6, 53025; CHECK-NEXT: addi a4, a1, -2413026; CHECK-NEXT: addi a2, a2, 8193027; CHECK-NEXT: addi a1, a6, 13653028; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma3029; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t3030; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t3031; CHECK-NEXT: vor.vv v16, v16, v24, v0.t3032; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t3033; CHECK-NEXT: vand.vx v24, v24, a4, v0.t3034; CHECK-NEXT: vand.vx v16, v16, a4, v0.t3035; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t3036; CHECK-NEXT: vor.vv v16, v24, v16, v0.t3037; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t3038; CHECK-NEXT: vand.vx v24, v24, a2, v0.t3039; CHECK-NEXT: vand.vx v16, v16, a2, v0.t3040; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t3041; CHECK-NEXT: vor.vv v16, v24, v16, v0.t3042; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t3043; CHECK-NEXT: vand.vx v24, v24, a1, v0.t3044; CHECK-NEXT: vand.vx v16, v16, a1, v0.t3045; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t3046; CHECK-NEXT: vor.vv v16, v24, v16, v0.t3047; CHECK-NEXT: bltu a0, a3, .LBB46_23048; CHECK-NEXT: # %bb.1:3049; CHECK-NEXT: mv a0, a33050; CHECK-NEXT: .LBB46_2:3051; CHECK-NEXT: vmv1r.v v0, v73052; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma3053; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t3054; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t3055; CHECK-NEXT: vor.vv v8, v8, v24, v0.t3056; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t3057; CHECK-NEXT: vand.vx v24, v24, a4, v0.t3058; CHECK-NEXT: vand.vx v8, v8, a4, v0.t3059; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t3060; CHECK-NEXT: vor.vv v8, v24, v8, v0.t3061; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t3062; CHECK-NEXT: vand.vx v24, v24, a2, v0.t3063; CHECK-NEXT: vand.vx v8, v8, a2, v0.t3064; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t3065; CHECK-NEXT: vor.vv v8, v24, v8, v0.t3066; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t3067; CHECK-NEXT: vand.vx v24, v24, a1, v0.t3068; CHECK-NEXT: vand.vx v8, v8, a1, v0.t3069; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t3070; CHECK-NEXT: vor.vv v8, v24, v8, v0.t3071; CHECK-NEXT: ret3072;3073; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:3074; CHECK-ZVBB: # %bb.0:3075; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma3076; CHECK-ZVBB-NEXT: vmv1r.v v24, v03077; CHECK-ZVBB-NEXT: csrr a1, vlenb3078; CHECK-ZVBB-NEXT: srli a2, a1, 13079; CHECK-ZVBB-NEXT: slli a1, a1, 23080; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a23081; CHECK-ZVBB-NEXT: sub a2, a0, a13082; CHECK-ZVBB-NEXT: sltu a3, a0, a23083; CHECK-ZVBB-NEXT: addi a3, a3, -13084; CHECK-ZVBB-NEXT: and a2, a3, a23085; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma3086; CHECK-ZVBB-NEXT: vbrev.v v16, v16, v0.t3087; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_23088; CHECK-ZVBB-NEXT: # %bb.1:3089; CHECK-ZVBB-NEXT: mv a0, a13090; CHECK-ZVBB-NEXT: .LBB46_2:3091; CHECK-ZVBB-NEXT: vmv1r.v v0, v243092; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma3093; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t3094; CHECK-ZVBB-NEXT: ret3095 %v = call <vscale x 64 x i16> @llvm.vp.bitreverse.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 %evl)3096 ret <vscale x 64 x i16> %v3097}3098 3099define <vscale x 64 x i16> @vp_bitreverse_nxv64i16_unmasked(<vscale x 64 x i16> %va, i32 zeroext %evl) {3100; CHECK-LABEL: vp_bitreverse_nxv64i16_unmasked:3101; CHECK: # %bb.0:3102; CHECK-NEXT: csrr a3, vlenb3103; CHECK-NEXT: lui a1, 13104; CHECK-NEXT: lui a2, 33105; CHECK-NEXT: slli a3, a3, 23106; CHECK-NEXT: sub a4, a0, a33107; CHECK-NEXT: sltu a5, a0, a43108; CHECK-NEXT: addi a5, a5, -13109; CHECK-NEXT: and a5, a5, a43110; CHECK-NEXT: lui a6, 53111; CHECK-NEXT: addi a4, a1, -2413112; CHECK-NEXT: addi a2, a2, 8193113; CHECK-NEXT: addi a1, a6, 13653114; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma3115; CHECK-NEXT: vsrl.vi v24, v16, 83116; CHECK-NEXT: vsll.vi v16, v16, 83117; CHECK-NEXT: vor.vv v16, v16, v243118; CHECK-NEXT: vsrl.vi v24, v16, 43119; CHECK-NEXT: vand.vx v16, v16, a43120; CHECK-NEXT: vand.vx v24, v24, a43121; CHECK-NEXT: vsll.vi v16, v16, 43122; CHECK-NEXT: vor.vv v16, v24, v163123; CHECK-NEXT: vsrl.vi v24, v16, 23124; CHECK-NEXT: vand.vx v16, v16, a23125; CHECK-NEXT: vand.vx v24, v24, a23126; CHECK-NEXT: vsll.vi v16, v16, 23127; CHECK-NEXT: vor.vv v16, v24, v163128; CHECK-NEXT: vsrl.vi v24, v16, 13129; CHECK-NEXT: vand.vx v16, v16, a13130; CHECK-NEXT: vand.vx v24, v24, a13131; CHECK-NEXT: vadd.vv v16, v16, v163132; CHECK-NEXT: vor.vv v16, v24, v163133; CHECK-NEXT: bltu a0, a3, .LBB47_23134; CHECK-NEXT: # %bb.1:3135; CHECK-NEXT: mv a0, a33136; CHECK-NEXT: .LBB47_2:3137; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma3138; CHECK-NEXT: vsrl.vi v24, v8, 83139; CHECK-NEXT: vsll.vi v8, v8, 83140; CHECK-NEXT: vor.vv v8, v8, v243141; CHECK-NEXT: vsrl.vi v24, v8, 43142; CHECK-NEXT: vand.vx v8, v8, a43143; CHECK-NEXT: vand.vx v24, v24, a43144; CHECK-NEXT: vsll.vi v8, v8, 43145; CHECK-NEXT: vor.vv v8, v24, v83146; CHECK-NEXT: vsrl.vi v24, v8, 23147; CHECK-NEXT: vand.vx v8, v8, a23148; CHECK-NEXT: vand.vx v24, v24, a23149; CHECK-NEXT: vsll.vi v8, v8, 23150; CHECK-NEXT: vor.vv v8, v24, v83151; CHECK-NEXT: vsrl.vi v24, v8, 13152; CHECK-NEXT: vand.vx v8, v8, a13153; CHECK-NEXT: vand.vx v24, v24, a13154; CHECK-NEXT: vadd.vv v8, v8, v83155; CHECK-NEXT: vor.vv v8, v24, v83156; CHECK-NEXT: ret3157;3158; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16_unmasked:3159; CHECK-ZVBB: # %bb.0:3160; CHECK-ZVBB-NEXT: csrr a1, vlenb3161; CHECK-ZVBB-NEXT: slli a1, a1, 23162; CHECK-ZVBB-NEXT: sub a2, a0, a13163; CHECK-ZVBB-NEXT: sltu a3, a0, a23164; CHECK-ZVBB-NEXT: addi a3, a3, -13165; CHECK-ZVBB-NEXT: and a2, a3, a23166; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma3167; CHECK-ZVBB-NEXT: vbrev.v v16, v163168; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_23169; CHECK-ZVBB-NEXT: # %bb.1:3170; CHECK-ZVBB-NEXT: mv a0, a13171; CHECK-ZVBB-NEXT: .LBB47_2:3172; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma3173; CHECK-ZVBB-NEXT: vbrev.v v8, v83174; CHECK-ZVBB-NEXT: ret3175 %v = call <vscale x 64 x i16> @llvm.vp.bitreverse.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)3176 ret <vscale x 64 x i16> %v3177}3178 3179; Test promotion.3180define <vscale x 1 x i9> @vp_bitreverse_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {3181; CHECK-LABEL: vp_bitreverse_nxv1i9:3182; CHECK: # %bb.0:3183; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3184; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t3185; CHECK-NEXT: lui a0, 13186; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t3187; CHECK-NEXT: addi a0, a0, -2413188; CHECK-NEXT: vor.vv v8, v8, v9, v0.t3189; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t3190; CHECK-NEXT: vand.vx v9, v9, a0, v0.t3191; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3192; CHECK-NEXT: lui a0, 33193; CHECK-NEXT: addi a0, a0, 8193194; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t3195; CHECK-NEXT: vor.vv v8, v9, v8, v0.t3196; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t3197; CHECK-NEXT: vand.vx v9, v9, a0, v0.t3198; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3199; CHECK-NEXT: lui a0, 53200; CHECK-NEXT: addi a0, a0, 13653201; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t3202; CHECK-NEXT: vor.vv v8, v9, v8, v0.t3203; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t3204; CHECK-NEXT: vand.vx v9, v9, a0, v0.t3205; CHECK-NEXT: vand.vx v8, v8, a0, v0.t3206; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t3207; CHECK-NEXT: vor.vv v8, v9, v8, v0.t3208; CHECK-NEXT: vsrl.vi v8, v8, 7, v0.t3209; CHECK-NEXT: ret3210;3211; CHECK-ZVBB-LABEL: vp_bitreverse_nxv1i9:3212; CHECK-ZVBB: # %bb.0:3213; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma3214; CHECK-ZVBB-NEXT: vbrev.v v8, v8, v0.t3215; CHECK-ZVBB-NEXT: vsrl.vi v8, v8, 7, v0.t3216; CHECK-ZVBB-NEXT: ret3217 %v = call <vscale x 1 x i9> @llvm.vp.bitreverse.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 %evl)3218 ret <vscale x 1 x i9> %v3219}3220