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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB6 7define <vscale x 1 x i16> @bswap_nxv1i16(<vscale x 1 x i16> %va) {8; CHECK-LABEL: bswap_nxv1i16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma11; CHECK-NEXT: vsrl.vi v9, v8, 812; CHECK-NEXT: vsll.vi v8, v8, 813; CHECK-NEXT: vor.vv v8, v8, v914; CHECK-NEXT: ret15;16; CHECK-ZVKB-LABEL: bswap_nxv1i16:17; CHECK-ZVKB: # %bb.0:18; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma19; CHECK-ZVKB-NEXT: vrev8.v v8, v820; CHECK-ZVKB-NEXT: ret21 %a = call <vscale x 1 x i16> @llvm.bswap.nxv1i16(<vscale x 1 x i16> %va)22 ret <vscale x 1 x i16> %a23}24 25define <vscale x 2 x i16> @bswap_nxv2i16(<vscale x 2 x i16> %va) {26; CHECK-LABEL: bswap_nxv2i16:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma29; CHECK-NEXT: vsrl.vi v9, v8, 830; CHECK-NEXT: vsll.vi v8, v8, 831; CHECK-NEXT: vor.vv v8, v8, v932; CHECK-NEXT: ret33;34; CHECK-ZVKB-LABEL: bswap_nxv2i16:35; CHECK-ZVKB: # %bb.0:36; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma37; CHECK-ZVKB-NEXT: vrev8.v v8, v838; CHECK-ZVKB-NEXT: ret39 %a = call <vscale x 2 x i16> @llvm.bswap.nxv2i16(<vscale x 2 x i16> %va)40 ret <vscale x 2 x i16> %a41}42 43define <vscale x 4 x i16> @bswap_nxv4i16(<vscale x 4 x i16> %va) {44; CHECK-LABEL: bswap_nxv4i16:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma47; CHECK-NEXT: vsrl.vi v9, v8, 848; CHECK-NEXT: vsll.vi v8, v8, 849; CHECK-NEXT: vor.vv v8, v8, v950; CHECK-NEXT: ret51;52; CHECK-ZVKB-LABEL: bswap_nxv4i16:53; CHECK-ZVKB: # %bb.0:54; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma55; CHECK-ZVKB-NEXT: vrev8.v v8, v856; CHECK-ZVKB-NEXT: ret57 %a = call <vscale x 4 x i16> @llvm.bswap.nxv4i16(<vscale x 4 x i16> %va)58 ret <vscale x 4 x i16> %a59}60 61define <vscale x 8 x i16> @bswap_nxv8i16(<vscale x 8 x i16> %va) {62; CHECK-LABEL: bswap_nxv8i16:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma65; CHECK-NEXT: vsrl.vi v10, v8, 866; CHECK-NEXT: vsll.vi v8, v8, 867; CHECK-NEXT: vor.vv v8, v8, v1068; CHECK-NEXT: ret69;70; CHECK-ZVKB-LABEL: bswap_nxv8i16:71; CHECK-ZVKB: # %bb.0:72; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma73; CHECK-ZVKB-NEXT: vrev8.v v8, v874; CHECK-ZVKB-NEXT: ret75 %a = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %va)76 ret <vscale x 8 x i16> %a77}78 79define <vscale x 16 x i16> @bswap_nxv16i16(<vscale x 16 x i16> %va) {80; CHECK-LABEL: bswap_nxv16i16:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma83; CHECK-NEXT: vsrl.vi v12, v8, 884; CHECK-NEXT: vsll.vi v8, v8, 885; CHECK-NEXT: vor.vv v8, v8, v1286; CHECK-NEXT: ret87;88; CHECK-ZVKB-LABEL: bswap_nxv16i16:89; CHECK-ZVKB: # %bb.0:90; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma91; CHECK-ZVKB-NEXT: vrev8.v v8, v892; CHECK-ZVKB-NEXT: ret93 %a = call <vscale x 16 x i16> @llvm.bswap.nxv16i16(<vscale x 16 x i16> %va)94 ret <vscale x 16 x i16> %a95}96 97define <vscale x 32 x i16> @bswap_nxv32i16(<vscale x 32 x i16> %va) {98; CHECK-LABEL: bswap_nxv32i16:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma101; CHECK-NEXT: vsrl.vi v16, v8, 8102; CHECK-NEXT: vsll.vi v8, v8, 8103; CHECK-NEXT: vor.vv v8, v8, v16104; CHECK-NEXT: ret105;106; CHECK-ZVKB-LABEL: bswap_nxv32i16:107; CHECK-ZVKB: # %bb.0:108; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma109; CHECK-ZVKB-NEXT: vrev8.v v8, v8110; CHECK-ZVKB-NEXT: ret111 %a = call <vscale x 32 x i16> @llvm.bswap.nxv32i16(<vscale x 32 x i16> %va)112 ret <vscale x 32 x i16> %a113}114 115define <vscale x 1 x i32> @bswap_nxv1i32(<vscale x 1 x i32> %va) {116; CHECK-LABEL: bswap_nxv1i32:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma119; CHECK-NEXT: vsrl.vi v9, v8, 8120; CHECK-NEXT: lui a0, 16121; CHECK-NEXT: vsrl.vi v10, v8, 24122; CHECK-NEXT: addi a0, a0, -256123; CHECK-NEXT: vand.vx v9, v9, a0124; CHECK-NEXT: vor.vv v9, v9, v10125; CHECK-NEXT: vand.vx v10, v8, a0126; CHECK-NEXT: vsll.vi v10, v10, 8127; CHECK-NEXT: vsll.vi v8, v8, 24128; CHECK-NEXT: vor.vv v8, v8, v10129; CHECK-NEXT: vor.vv v8, v8, v9130; CHECK-NEXT: ret131;132; CHECK-ZVKB-LABEL: bswap_nxv1i32:133; CHECK-ZVKB: # %bb.0:134; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma135; CHECK-ZVKB-NEXT: vrev8.v v8, v8136; CHECK-ZVKB-NEXT: ret137 %a = call <vscale x 1 x i32> @llvm.bswap.nxv1i32(<vscale x 1 x i32> %va)138 ret <vscale x 1 x i32> %a139}140 141define <vscale x 2 x i32> @bswap_nxv2i32(<vscale x 2 x i32> %va) {142; CHECK-LABEL: bswap_nxv2i32:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma145; CHECK-NEXT: vsrl.vi v9, v8, 8146; CHECK-NEXT: lui a0, 16147; CHECK-NEXT: vsrl.vi v10, v8, 24148; CHECK-NEXT: addi a0, a0, -256149; CHECK-NEXT: vand.vx v9, v9, a0150; CHECK-NEXT: vor.vv v9, v9, v10151; CHECK-NEXT: vand.vx v10, v8, a0152; CHECK-NEXT: vsll.vi v10, v10, 8153; CHECK-NEXT: vsll.vi v8, v8, 24154; CHECK-NEXT: vor.vv v8, v8, v10155; CHECK-NEXT: vor.vv v8, v8, v9156; CHECK-NEXT: ret157;158; CHECK-ZVKB-LABEL: bswap_nxv2i32:159; CHECK-ZVKB: # %bb.0:160; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma161; CHECK-ZVKB-NEXT: vrev8.v v8, v8162; CHECK-ZVKB-NEXT: ret163 %a = call <vscale x 2 x i32> @llvm.bswap.nxv2i32(<vscale x 2 x i32> %va)164 ret <vscale x 2 x i32> %a165}166 167define <vscale x 4 x i32> @bswap_nxv4i32(<vscale x 4 x i32> %va) {168; CHECK-LABEL: bswap_nxv4i32:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma171; CHECK-NEXT: vsrl.vi v10, v8, 8172; CHECK-NEXT: lui a0, 16173; CHECK-NEXT: vsrl.vi v12, v8, 24174; CHECK-NEXT: addi a0, a0, -256175; CHECK-NEXT: vand.vx v10, v10, a0176; CHECK-NEXT: vor.vv v10, v10, v12177; CHECK-NEXT: vand.vx v12, v8, a0178; CHECK-NEXT: vsll.vi v12, v12, 8179; CHECK-NEXT: vsll.vi v8, v8, 24180; CHECK-NEXT: vor.vv v8, v8, v12181; CHECK-NEXT: vor.vv v8, v8, v10182; CHECK-NEXT: ret183;184; CHECK-ZVKB-LABEL: bswap_nxv4i32:185; CHECK-ZVKB: # %bb.0:186; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma187; CHECK-ZVKB-NEXT: vrev8.v v8, v8188; CHECK-ZVKB-NEXT: ret189 %a = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %va)190 ret <vscale x 4 x i32> %a191}192 193define <vscale x 8 x i32> @bswap_nxv8i32(<vscale x 8 x i32> %va) {194; CHECK-LABEL: bswap_nxv8i32:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma197; CHECK-NEXT: vsrl.vi v12, v8, 8198; CHECK-NEXT: lui a0, 16199; CHECK-NEXT: vsrl.vi v16, v8, 24200; CHECK-NEXT: addi a0, a0, -256201; CHECK-NEXT: vand.vx v12, v12, a0202; CHECK-NEXT: vor.vv v12, v12, v16203; CHECK-NEXT: vand.vx v16, v8, a0204; CHECK-NEXT: vsll.vi v16, v16, 8205; CHECK-NEXT: vsll.vi v8, v8, 24206; CHECK-NEXT: vor.vv v8, v8, v16207; CHECK-NEXT: vor.vv v8, v8, v12208; CHECK-NEXT: ret209;210; CHECK-ZVKB-LABEL: bswap_nxv8i32:211; CHECK-ZVKB: # %bb.0:212; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma213; CHECK-ZVKB-NEXT: vrev8.v v8, v8214; CHECK-ZVKB-NEXT: ret215 %a = call <vscale x 8 x i32> @llvm.bswap.nxv8i32(<vscale x 8 x i32> %va)216 ret <vscale x 8 x i32> %a217}218 219define <vscale x 16 x i32> @bswap_nxv16i32(<vscale x 16 x i32> %va) {220; CHECK-LABEL: bswap_nxv16i32:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma223; CHECK-NEXT: vsrl.vi v16, v8, 8224; CHECK-NEXT: lui a0, 16225; CHECK-NEXT: vsrl.vi v24, v8, 24226; CHECK-NEXT: addi a0, a0, -256227; CHECK-NEXT: vand.vx v16, v16, a0228; CHECK-NEXT: vor.vv v16, v16, v24229; CHECK-NEXT: vand.vx v24, v8, a0230; CHECK-NEXT: vsll.vi v24, v24, 8231; CHECK-NEXT: vsll.vi v8, v8, 24232; CHECK-NEXT: vor.vv v8, v8, v24233; CHECK-NEXT: vor.vv v8, v8, v16234; CHECK-NEXT: ret235;236; CHECK-ZVKB-LABEL: bswap_nxv16i32:237; CHECK-ZVKB: # %bb.0:238; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma239; CHECK-ZVKB-NEXT: vrev8.v v8, v8240; CHECK-ZVKB-NEXT: ret241 %a = call <vscale x 16 x i32> @llvm.bswap.nxv16i32(<vscale x 16 x i32> %va)242 ret <vscale x 16 x i32> %a243}244 245define <vscale x 1 x i64> @bswap_nxv1i64(<vscale x 1 x i64> %va) {246; RV32-LABEL: bswap_nxv1i64:247; RV32: # %bb.0:248; RV32-NEXT: addi sp, sp, -16249; RV32-NEXT: .cfi_def_cfa_offset 16250; RV32-NEXT: lui a0, 1044480251; RV32-NEXT: li a1, 56252; RV32-NEXT: li a2, 40253; RV32-NEXT: lui a3, 16254; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma255; RV32-NEXT: vsrl.vi v9, v8, 24256; RV32-NEXT: lui a4, 4080257; RV32-NEXT: addi a5, sp, 8258; RV32-NEXT: sw a0, 8(sp)259; RV32-NEXT: sw zero, 12(sp)260; RV32-NEXT: vsrl.vx v10, v8, a1261; RV32-NEXT: vsrl.vx v11, v8, a2262; RV32-NEXT: addi a0, a3, -256263; RV32-NEXT: vsll.vx v12, v8, a1264; RV32-NEXT: vand.vx v11, v11, a0265; RV32-NEXT: vlse64.v v13, (a5), zero266; RV32-NEXT: vor.vv v10, v11, v10267; RV32-NEXT: vand.vx v11, v8, a0268; RV32-NEXT: vsll.vx v11, v11, a2269; RV32-NEXT: vor.vv v11, v12, v11270; RV32-NEXT: vsrl.vi v12, v8, 8271; RV32-NEXT: vand.vx v9, v9, a4272; RV32-NEXT: vand.vv v12, v12, v13273; RV32-NEXT: vor.vv v9, v12, v9274; RV32-NEXT: vand.vv v12, v8, v13275; RV32-NEXT: vand.vx v8, v8, a4276; RV32-NEXT: vsll.vi v8, v8, 24277; RV32-NEXT: vsll.vi v12, v12, 8278; RV32-NEXT: vor.vv v9, v9, v10279; RV32-NEXT: vor.vv v8, v8, v12280; RV32-NEXT: vor.vv v8, v11, v8281; RV32-NEXT: vor.vv v8, v8, v9282; RV32-NEXT: addi sp, sp, 16283; RV32-NEXT: .cfi_def_cfa_offset 0284; RV32-NEXT: ret285;286; RV64-LABEL: bswap_nxv1i64:287; RV64: # %bb.0:288; RV64-NEXT: li a0, 56289; RV64-NEXT: li a1, 40290; RV64-NEXT: lui a2, 16291; RV64-NEXT: vsetvli a3, zero, e64, m1, ta, ma292; RV64-NEXT: vsrl.vi v9, v8, 24293; RV64-NEXT: lui a3, 4080294; RV64-NEXT: vsrl.vx v10, v8, a0295; RV64-NEXT: vsrl.vx v11, v8, a1296; RV64-NEXT: addi a2, a2, -256297; RV64-NEXT: vand.vx v11, v11, a2298; RV64-NEXT: vor.vv v10, v11, v10299; RV64-NEXT: vsrl.vi v11, v8, 8300; RV64-NEXT: li a4, 255301; RV64-NEXT: vand.vx v9, v9, a3302; RV64-NEXT: slli a4, a4, 24303; RV64-NEXT: vand.vx v11, v11, a4304; RV64-NEXT: vor.vv v9, v11, v9305; RV64-NEXT: vand.vx v11, v8, a3306; RV64-NEXT: vsll.vi v11, v11, 24307; RV64-NEXT: vor.vv v9, v9, v10308; RV64-NEXT: vand.vx v10, v8, a4309; RV64-NEXT: vsll.vi v10, v10, 8310; RV64-NEXT: vor.vv v10, v11, v10311; RV64-NEXT: vsll.vx v11, v8, a0312; RV64-NEXT: vand.vx v8, v8, a2313; RV64-NEXT: vsll.vx v8, v8, a1314; RV64-NEXT: vor.vv v8, v11, v8315; RV64-NEXT: vor.vv v8, v8, v10316; RV64-NEXT: vor.vv v8, v8, v9317; RV64-NEXT: ret318;319; CHECK-ZVKB-LABEL: bswap_nxv1i64:320; CHECK-ZVKB: # %bb.0:321; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma322; CHECK-ZVKB-NEXT: vrev8.v v8, v8323; CHECK-ZVKB-NEXT: ret324 %a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va)325 ret <vscale x 1 x i64> %a326}327 328define <vscale x 2 x i64> @bswap_nxv2i64(<vscale x 2 x i64> %va) {329; RV32-LABEL: bswap_nxv2i64:330; RV32: # %bb.0:331; RV32-NEXT: addi sp, sp, -16332; RV32-NEXT: .cfi_def_cfa_offset 16333; RV32-NEXT: lui a0, 1044480334; RV32-NEXT: li a1, 56335; RV32-NEXT: li a2, 40336; RV32-NEXT: lui a3, 16337; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma338; RV32-NEXT: vsrl.vi v10, v8, 24339; RV32-NEXT: lui a4, 4080340; RV32-NEXT: addi a5, sp, 8341; RV32-NEXT: sw a0, 8(sp)342; RV32-NEXT: sw zero, 12(sp)343; RV32-NEXT: vsrl.vx v12, v8, a1344; RV32-NEXT: vsrl.vx v14, v8, a2345; RV32-NEXT: addi a0, a3, -256346; RV32-NEXT: vsll.vx v16, v8, a1347; RV32-NEXT: vand.vx v14, v14, a0348; RV32-NEXT: vlse64.v v18, (a5), zero349; RV32-NEXT: vor.vv v12, v14, v12350; RV32-NEXT: vand.vx v14, v8, a0351; RV32-NEXT: vsll.vx v14, v14, a2352; RV32-NEXT: vor.vv v14, v16, v14353; RV32-NEXT: vsrl.vi v16, v8, 8354; RV32-NEXT: vand.vx v10, v10, a4355; RV32-NEXT: vand.vv v16, v16, v18356; RV32-NEXT: vor.vv v10, v16, v10357; RV32-NEXT: vand.vv v16, v8, v18358; RV32-NEXT: vand.vx v8, v8, a4359; RV32-NEXT: vsll.vi v8, v8, 24360; RV32-NEXT: vsll.vi v16, v16, 8361; RV32-NEXT: vor.vv v10, v10, v12362; RV32-NEXT: vor.vv v8, v8, v16363; RV32-NEXT: vor.vv v8, v14, v8364; RV32-NEXT: vor.vv v8, v8, v10365; RV32-NEXT: addi sp, sp, 16366; RV32-NEXT: .cfi_def_cfa_offset 0367; RV32-NEXT: ret368;369; RV64-LABEL: bswap_nxv2i64:370; RV64: # %bb.0:371; RV64-NEXT: li a0, 56372; RV64-NEXT: li a1, 40373; RV64-NEXT: lui a2, 16374; RV64-NEXT: vsetvli a3, zero, e64, m2, ta, ma375; RV64-NEXT: vsrl.vi v10, v8, 24376; RV64-NEXT: lui a3, 4080377; RV64-NEXT: vsrl.vx v12, v8, a0378; RV64-NEXT: vsrl.vx v14, v8, a1379; RV64-NEXT: addi a2, a2, -256380; RV64-NEXT: vand.vx v14, v14, a2381; RV64-NEXT: vor.vv v12, v14, v12382; RV64-NEXT: vsrl.vi v14, v8, 8383; RV64-NEXT: li a4, 255384; RV64-NEXT: vand.vx v10, v10, a3385; RV64-NEXT: slli a4, a4, 24386; RV64-NEXT: vand.vx v14, v14, a4387; RV64-NEXT: vor.vv v10, v14, v10388; RV64-NEXT: vand.vx v14, v8, a3389; RV64-NEXT: vsll.vi v14, v14, 24390; RV64-NEXT: vor.vv v10, v10, v12391; RV64-NEXT: vand.vx v12, v8, a4392; RV64-NEXT: vsll.vi v12, v12, 8393; RV64-NEXT: vor.vv v12, v14, v12394; RV64-NEXT: vsll.vx v14, v8, a0395; RV64-NEXT: vand.vx v8, v8, a2396; RV64-NEXT: vsll.vx v8, v8, a1397; RV64-NEXT: vor.vv v8, v14, v8398; RV64-NEXT: vor.vv v8, v8, v12399; RV64-NEXT: vor.vv v8, v8, v10400; RV64-NEXT: ret401;402; CHECK-ZVKB-LABEL: bswap_nxv2i64:403; CHECK-ZVKB: # %bb.0:404; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma405; CHECK-ZVKB-NEXT: vrev8.v v8, v8406; CHECK-ZVKB-NEXT: ret407 %a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va)408 ret <vscale x 2 x i64> %a409}410 411define <vscale x 4 x i64> @bswap_nxv4i64(<vscale x 4 x i64> %va) {412; RV32-LABEL: bswap_nxv4i64:413; RV32: # %bb.0:414; RV32-NEXT: addi sp, sp, -16415; RV32-NEXT: .cfi_def_cfa_offset 16416; RV32-NEXT: lui a0, 1044480417; RV32-NEXT: li a1, 56418; RV32-NEXT: li a2, 40419; RV32-NEXT: lui a3, 16420; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma421; RV32-NEXT: vsrl.vi v12, v8, 24422; RV32-NEXT: lui a4, 4080423; RV32-NEXT: addi a5, sp, 8424; RV32-NEXT: sw a0, 8(sp)425; RV32-NEXT: sw zero, 12(sp)426; RV32-NEXT: vsrl.vx v16, v8, a1427; RV32-NEXT: vsrl.vx v20, v8, a2428; RV32-NEXT: addi a0, a3, -256429; RV32-NEXT: vsll.vx v24, v8, a1430; RV32-NEXT: vand.vx v20, v20, a0431; RV32-NEXT: vlse64.v v28, (a5), zero432; RV32-NEXT: vor.vv v16, v20, v16433; RV32-NEXT: vand.vx v20, v8, a0434; RV32-NEXT: vsll.vx v20, v20, a2435; RV32-NEXT: vor.vv v20, v24, v20436; RV32-NEXT: vsrl.vi v24, v8, 8437; RV32-NEXT: vand.vx v12, v12, a4438; RV32-NEXT: vand.vv v24, v24, v28439; RV32-NEXT: vor.vv v12, v24, v12440; RV32-NEXT: vand.vv v24, v8, v28441; RV32-NEXT: vand.vx v8, v8, a4442; RV32-NEXT: vsll.vi v8, v8, 24443; RV32-NEXT: vsll.vi v24, v24, 8444; RV32-NEXT: vor.vv v12, v12, v16445; RV32-NEXT: vor.vv v8, v8, v24446; RV32-NEXT: vor.vv v8, v20, v8447; RV32-NEXT: vor.vv v8, v8, v12448; RV32-NEXT: addi sp, sp, 16449; RV32-NEXT: .cfi_def_cfa_offset 0450; RV32-NEXT: ret451;452; RV64-LABEL: bswap_nxv4i64:453; RV64: # %bb.0:454; RV64-NEXT: li a0, 56455; RV64-NEXT: li a1, 40456; RV64-NEXT: lui a2, 16457; RV64-NEXT: vsetvli a3, zero, e64, m4, ta, ma458; RV64-NEXT: vsrl.vi v12, v8, 24459; RV64-NEXT: lui a3, 4080460; RV64-NEXT: vsrl.vx v16, v8, a0461; RV64-NEXT: vsrl.vx v20, v8, a1462; RV64-NEXT: addi a2, a2, -256463; RV64-NEXT: vand.vx v20, v20, a2464; RV64-NEXT: vor.vv v16, v20, v16465; RV64-NEXT: vsrl.vi v20, v8, 8466; RV64-NEXT: li a4, 255467; RV64-NEXT: vand.vx v12, v12, a3468; RV64-NEXT: slli a4, a4, 24469; RV64-NEXT: vand.vx v20, v20, a4470; RV64-NEXT: vor.vv v12, v20, v12471; RV64-NEXT: vand.vx v20, v8, a3472; RV64-NEXT: vsll.vi v20, v20, 24473; RV64-NEXT: vor.vv v12, v12, v16474; RV64-NEXT: vand.vx v16, v8, a4475; RV64-NEXT: vsll.vi v16, v16, 8476; RV64-NEXT: vor.vv v16, v20, v16477; RV64-NEXT: vsll.vx v20, v8, a0478; RV64-NEXT: vand.vx v8, v8, a2479; RV64-NEXT: vsll.vx v8, v8, a1480; RV64-NEXT: vor.vv v8, v20, v8481; RV64-NEXT: vor.vv v8, v8, v16482; RV64-NEXT: vor.vv v8, v8, v12483; RV64-NEXT: ret484;485; CHECK-ZVKB-LABEL: bswap_nxv4i64:486; CHECK-ZVKB: # %bb.0:487; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma488; CHECK-ZVKB-NEXT: vrev8.v v8, v8489; CHECK-ZVKB-NEXT: ret490 %a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va)491 ret <vscale x 4 x i64> %a492}493 494define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {495; RV32-LABEL: bswap_nxv8i64:496; RV32: # %bb.0:497; RV32-NEXT: addi sp, sp, -16498; RV32-NEXT: .cfi_def_cfa_offset 16499; RV32-NEXT: csrr a0, vlenb500; RV32-NEXT: slli a0, a0, 4501; RV32-NEXT: sub sp, sp, a0502; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb503; RV32-NEXT: lui a0, 1044480504; RV32-NEXT: li a1, 56505; RV32-NEXT: li a2, 40506; RV32-NEXT: lui a3, 16507; RV32-NEXT: lui a4, 4080508; RV32-NEXT: addi a5, sp, 8509; RV32-NEXT: sw a0, 8(sp)510; RV32-NEXT: sw zero, 12(sp)511; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma512; RV32-NEXT: vsrl.vx v16, v8, a1513; RV32-NEXT: vsrl.vx v24, v8, a2514; RV32-NEXT: addi a0, a3, -256515; RV32-NEXT: vsll.vx v0, v8, a1516; RV32-NEXT: vand.vx v24, v24, a0517; RV32-NEXT: vor.vv v16, v24, v16518; RV32-NEXT: addi a1, sp, 16519; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill520; RV32-NEXT: vand.vx v16, v8, a0521; RV32-NEXT: vsll.vx v16, v16, a2522; RV32-NEXT: vor.vv v16, v0, v16523; RV32-NEXT: csrr a0, vlenb524; RV32-NEXT: slli a0, a0, 3525; RV32-NEXT: add a0, sp, a0526; RV32-NEXT: addi a0, a0, 16527; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill528; RV32-NEXT: vlse64.v v0, (a5), zero529; RV32-NEXT: vsrl.vi v16, v8, 24530; RV32-NEXT: vand.vx v16, v16, a4531; RV32-NEXT: vsrl.vi v24, v8, 8532; RV32-NEXT: vand.vv v24, v24, v0533; RV32-NEXT: vor.vv v16, v24, v16534; RV32-NEXT: addi a0, sp, 16535; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload536; RV32-NEXT: vor.vv v24, v16, v24537; RV32-NEXT: vand.vv v16, v8, v0538; RV32-NEXT: vand.vx v8, v8, a4539; RV32-NEXT: vsll.vi v8, v8, 24540; RV32-NEXT: vsll.vi v16, v16, 8541; RV32-NEXT: vor.vv v8, v8, v16542; RV32-NEXT: csrr a0, vlenb543; RV32-NEXT: slli a0, a0, 3544; RV32-NEXT: add a0, sp, a0545; RV32-NEXT: addi a0, a0, 16546; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload547; RV32-NEXT: vor.vv v8, v16, v8548; RV32-NEXT: vor.vv v8, v8, v24549; RV32-NEXT: csrr a0, vlenb550; RV32-NEXT: slli a0, a0, 4551; RV32-NEXT: add sp, sp, a0552; RV32-NEXT: .cfi_def_cfa sp, 16553; RV32-NEXT: addi sp, sp, 16554; RV32-NEXT: .cfi_def_cfa_offset 0555; RV32-NEXT: ret556;557; RV64-LABEL: bswap_nxv8i64:558; RV64: # %bb.0:559; RV64-NEXT: li a0, 56560; RV64-NEXT: li a1, 40561; RV64-NEXT: lui a2, 16562; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma563; RV64-NEXT: vsrl.vi v24, v8, 24564; RV64-NEXT: lui a3, 4080565; RV64-NEXT: vsrl.vx v16, v8, a0566; RV64-NEXT: vsrl.vx v0, v8, a1567; RV64-NEXT: addi a2, a2, -256568; RV64-NEXT: vand.vx v0, v0, a2569; RV64-NEXT: vor.vv v16, v0, v16570; RV64-NEXT: vsrl.vi v0, v8, 8571; RV64-NEXT: li a4, 255572; RV64-NEXT: vand.vx v24, v24, a3573; RV64-NEXT: slli a4, a4, 24574; RV64-NEXT: vand.vx v0, v0, a4575; RV64-NEXT: vor.vv v24, v0, v24576; RV64-NEXT: vand.vx v0, v8, a3577; RV64-NEXT: vsll.vi v0, v0, 24578; RV64-NEXT: vor.vv v16, v24, v16579; RV64-NEXT: vand.vx v24, v8, a4580; RV64-NEXT: vsll.vi v24, v24, 8581; RV64-NEXT: vor.vv v24, v0, v24582; RV64-NEXT: vsll.vx v0, v8, a0583; RV64-NEXT: vand.vx v8, v8, a2584; RV64-NEXT: vsll.vx v8, v8, a1585; RV64-NEXT: vor.vv v8, v0, v8586; RV64-NEXT: vor.vv v8, v8, v24587; RV64-NEXT: vor.vv v8, v8, v16588; RV64-NEXT: ret589;590; CHECK-ZVKB-LABEL: bswap_nxv8i64:591; CHECK-ZVKB: # %bb.0:592; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma593; CHECK-ZVKB-NEXT: vrev8.v v8, v8594; CHECK-ZVKB-NEXT: ret595 %a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va)596 ret <vscale x 8 x i64> %a597}598