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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb,+m -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB8; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb,+m -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB10 11define <vscale x 1 x i16> @vp_bswap_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {12; CHECK-LABEL: vp_bswap_nxv1i16:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma15; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t16; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t17; CHECK-NEXT: vor.vv v8, v8, v9, v0.t18; CHECK-NEXT: ret19;20; CHECK-ZVKB-LABEL: vp_bswap_nxv1i16:21; CHECK-ZVKB: # %bb.0:22; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma23; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t24; CHECK-ZVKB-NEXT: ret25 %v = call <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)26 ret <vscale x 1 x i16> %v27}28 29define <vscale x 1 x i16> @vp_bswap_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {30; CHECK-LABEL: vp_bswap_nxv1i16_unmasked:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma33; CHECK-NEXT: vsrl.vi v9, v8, 834; CHECK-NEXT: vsll.vi v8, v8, 835; CHECK-NEXT: vor.vv v8, v8, v936; CHECK-NEXT: ret37;38; CHECK-ZVKB-LABEL: vp_bswap_nxv1i16_unmasked:39; CHECK-ZVKB: # %bb.0:40; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma41; CHECK-ZVKB-NEXT: vrev8.v v8, v842; CHECK-ZVKB-NEXT: ret43 %v = call <vscale x 1 x i16> @llvm.vp.bswap.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)44 ret <vscale x 1 x i16> %v45}46 47define <vscale x 2 x i16> @vp_bswap_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vp_bswap_nxv2i16:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma51; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t52; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t53; CHECK-NEXT: vor.vv v8, v8, v9, v0.t54; CHECK-NEXT: ret55;56; CHECK-ZVKB-LABEL: vp_bswap_nxv2i16:57; CHECK-ZVKB: # %bb.0:58; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma59; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t60; CHECK-ZVKB-NEXT: ret61 %v = call <vscale x 2 x i16> @llvm.vp.bswap.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 %evl)62 ret <vscale x 2 x i16> %v63}64 65define <vscale x 2 x i16> @vp_bswap_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {66; CHECK-LABEL: vp_bswap_nxv2i16_unmasked:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma69; CHECK-NEXT: vsrl.vi v9, v8, 870; CHECK-NEXT: vsll.vi v8, v8, 871; CHECK-NEXT: vor.vv v8, v8, v972; CHECK-NEXT: ret73;74; CHECK-ZVKB-LABEL: vp_bswap_nxv2i16_unmasked:75; CHECK-ZVKB: # %bb.0:76; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma77; CHECK-ZVKB-NEXT: vrev8.v v8, v878; CHECK-ZVKB-NEXT: ret79 %v = call <vscale x 2 x i16> @llvm.vp.bswap.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)80 ret <vscale x 2 x i16> %v81}82 83define <vscale x 4 x i16> @vp_bswap_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {84; CHECK-LABEL: vp_bswap_nxv4i16:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma87; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t88; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t89; CHECK-NEXT: vor.vv v8, v8, v9, v0.t90; CHECK-NEXT: ret91;92; CHECK-ZVKB-LABEL: vp_bswap_nxv4i16:93; CHECK-ZVKB: # %bb.0:94; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma95; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t96; CHECK-ZVKB-NEXT: ret97 %v = call <vscale x 4 x i16> @llvm.vp.bswap.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 %evl)98 ret <vscale x 4 x i16> %v99}100 101define <vscale x 4 x i16> @vp_bswap_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {102; CHECK-LABEL: vp_bswap_nxv4i16_unmasked:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma105; CHECK-NEXT: vsrl.vi v9, v8, 8106; CHECK-NEXT: vsll.vi v8, v8, 8107; CHECK-NEXT: vor.vv v8, v8, v9108; CHECK-NEXT: ret109;110; CHECK-ZVKB-LABEL: vp_bswap_nxv4i16_unmasked:111; CHECK-ZVKB: # %bb.0:112; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma113; CHECK-ZVKB-NEXT: vrev8.v v8, v8114; CHECK-ZVKB-NEXT: ret115 %v = call <vscale x 4 x i16> @llvm.vp.bswap.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)116 ret <vscale x 4 x i16> %v117}118 119define <vscale x 8 x i16> @vp_bswap_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vp_bswap_nxv8i16:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma123; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t124; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t125; CHECK-NEXT: vor.vv v8, v8, v10, v0.t126; CHECK-NEXT: ret127;128; CHECK-ZVKB-LABEL: vp_bswap_nxv8i16:129; CHECK-ZVKB: # %bb.0:130; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma131; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t132; CHECK-ZVKB-NEXT: ret133 %v = call <vscale x 8 x i16> @llvm.vp.bswap.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 %evl)134 ret <vscale x 8 x i16> %v135}136 137define <vscale x 8 x i16> @vp_bswap_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {138; CHECK-LABEL: vp_bswap_nxv8i16_unmasked:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma141; CHECK-NEXT: vsrl.vi v10, v8, 8142; CHECK-NEXT: vsll.vi v8, v8, 8143; CHECK-NEXT: vor.vv v8, v8, v10144; CHECK-NEXT: ret145;146; CHECK-ZVKB-LABEL: vp_bswap_nxv8i16_unmasked:147; CHECK-ZVKB: # %bb.0:148; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma149; CHECK-ZVKB-NEXT: vrev8.v v8, v8150; CHECK-ZVKB-NEXT: ret151 %v = call <vscale x 8 x i16> @llvm.vp.bswap.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)152 ret <vscale x 8 x i16> %v153}154 155define <vscale x 16 x i16> @vp_bswap_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {156; CHECK-LABEL: vp_bswap_nxv16i16:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma159; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t160; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t161; CHECK-NEXT: vor.vv v8, v8, v12, v0.t162; CHECK-NEXT: ret163;164; CHECK-ZVKB-LABEL: vp_bswap_nxv16i16:165; CHECK-ZVKB: # %bb.0:166; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma167; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t168; CHECK-ZVKB-NEXT: ret169 %v = call <vscale x 16 x i16> @llvm.vp.bswap.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 %evl)170 ret <vscale x 16 x i16> %v171}172 173define <vscale x 16 x i16> @vp_bswap_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {174; CHECK-LABEL: vp_bswap_nxv16i16_unmasked:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma177; CHECK-NEXT: vsrl.vi v12, v8, 8178; CHECK-NEXT: vsll.vi v8, v8, 8179; CHECK-NEXT: vor.vv v8, v8, v12180; CHECK-NEXT: ret181;182; CHECK-ZVKB-LABEL: vp_bswap_nxv16i16_unmasked:183; CHECK-ZVKB: # %bb.0:184; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma185; CHECK-ZVKB-NEXT: vrev8.v v8, v8186; CHECK-ZVKB-NEXT: ret187 %v = call <vscale x 16 x i16> @llvm.vp.bswap.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)188 ret <vscale x 16 x i16> %v189}190 191define <vscale x 32 x i16> @vp_bswap_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: vp_bswap_nxv32i16:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma195; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t196; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t197; CHECK-NEXT: vor.vv v8, v8, v16, v0.t198; CHECK-NEXT: ret199;200; CHECK-ZVKB-LABEL: vp_bswap_nxv32i16:201; CHECK-ZVKB: # %bb.0:202; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma203; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t204; CHECK-ZVKB-NEXT: ret205 %v = call <vscale x 32 x i16> @llvm.vp.bswap.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 %evl)206 ret <vscale x 32 x i16> %v207}208 209define <vscale x 32 x i16> @vp_bswap_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {210; CHECK-LABEL: vp_bswap_nxv32i16_unmasked:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma213; CHECK-NEXT: vsrl.vi v16, v8, 8214; CHECK-NEXT: vsll.vi v8, v8, 8215; CHECK-NEXT: vor.vv v8, v8, v16216; CHECK-NEXT: ret217;218; CHECK-ZVKB-LABEL: vp_bswap_nxv32i16_unmasked:219; CHECK-ZVKB: # %bb.0:220; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma221; CHECK-ZVKB-NEXT: vrev8.v v8, v8222; CHECK-ZVKB-NEXT: ret223 %v = call <vscale x 32 x i16> @llvm.vp.bswap.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)224 ret <vscale x 32 x i16> %v225}226 227define <vscale x 1 x i32> @vp_bswap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {228; CHECK-LABEL: vp_bswap_nxv1i32:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma231; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t232; CHECK-NEXT: lui a0, 16233; CHECK-NEXT: addi a0, a0, -256234; CHECK-NEXT: vand.vx v9, v9, a0, v0.t235; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t236; CHECK-NEXT: vor.vv v9, v9, v10, v0.t237; CHECK-NEXT: vand.vx v10, v8, a0, v0.t238; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t239; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t240; CHECK-NEXT: vor.vv v8, v8, v10, v0.t241; CHECK-NEXT: vor.vv v8, v8, v9, v0.t242; CHECK-NEXT: ret243;244; CHECK-ZVKB-LABEL: vp_bswap_nxv1i32:245; CHECK-ZVKB: # %bb.0:246; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma247; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t248; CHECK-ZVKB-NEXT: ret249 %v = call <vscale x 1 x i32> @llvm.vp.bswap.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 %evl)250 ret <vscale x 1 x i32> %v251}252 253define <vscale x 1 x i32> @vp_bswap_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {254; CHECK-LABEL: vp_bswap_nxv1i32_unmasked:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma257; CHECK-NEXT: vsrl.vi v9, v8, 8258; CHECK-NEXT: lui a0, 16259; CHECK-NEXT: vsrl.vi v10, v8, 24260; CHECK-NEXT: addi a0, a0, -256261; CHECK-NEXT: vand.vx v9, v9, a0262; CHECK-NEXT: vor.vv v9, v9, v10263; CHECK-NEXT: vand.vx v10, v8, a0264; CHECK-NEXT: vsll.vi v10, v10, 8265; CHECK-NEXT: vsll.vi v8, v8, 24266; CHECK-NEXT: vor.vv v8, v8, v10267; CHECK-NEXT: vor.vv v8, v8, v9268; CHECK-NEXT: ret269;270; CHECK-ZVKB-LABEL: vp_bswap_nxv1i32_unmasked:271; CHECK-ZVKB: # %bb.0:272; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma273; CHECK-ZVKB-NEXT: vrev8.v v8, v8274; CHECK-ZVKB-NEXT: ret275 %v = call <vscale x 1 x i32> @llvm.vp.bswap.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)276 ret <vscale x 1 x i32> %v277}278 279define <vscale x 2 x i32> @vp_bswap_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {280; CHECK-LABEL: vp_bswap_nxv2i32:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma283; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t284; CHECK-NEXT: lui a0, 16285; CHECK-NEXT: addi a0, a0, -256286; CHECK-NEXT: vand.vx v9, v9, a0, v0.t287; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t288; CHECK-NEXT: vor.vv v9, v9, v10, v0.t289; CHECK-NEXT: vand.vx v10, v8, a0, v0.t290; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t291; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t292; CHECK-NEXT: vor.vv v8, v8, v10, v0.t293; CHECK-NEXT: vor.vv v8, v8, v9, v0.t294; CHECK-NEXT: ret295;296; CHECK-ZVKB-LABEL: vp_bswap_nxv2i32:297; CHECK-ZVKB: # %bb.0:298; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma299; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t300; CHECK-ZVKB-NEXT: ret301 %v = call <vscale x 2 x i32> @llvm.vp.bswap.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 %evl)302 ret <vscale x 2 x i32> %v303}304 305define <vscale x 2 x i32> @vp_bswap_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {306; CHECK-LABEL: vp_bswap_nxv2i32_unmasked:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma309; CHECK-NEXT: vsrl.vi v9, v8, 8310; CHECK-NEXT: lui a0, 16311; CHECK-NEXT: vsrl.vi v10, v8, 24312; CHECK-NEXT: addi a0, a0, -256313; CHECK-NEXT: vand.vx v9, v9, a0314; CHECK-NEXT: vor.vv v9, v9, v10315; CHECK-NEXT: vand.vx v10, v8, a0316; CHECK-NEXT: vsll.vi v10, v10, 8317; CHECK-NEXT: vsll.vi v8, v8, 24318; CHECK-NEXT: vor.vv v8, v8, v10319; CHECK-NEXT: vor.vv v8, v8, v9320; CHECK-NEXT: ret321;322; CHECK-ZVKB-LABEL: vp_bswap_nxv2i32_unmasked:323; CHECK-ZVKB: # %bb.0:324; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma325; CHECK-ZVKB-NEXT: vrev8.v v8, v8326; CHECK-ZVKB-NEXT: ret327 %v = call <vscale x 2 x i32> @llvm.vp.bswap.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)328 ret <vscale x 2 x i32> %v329}330 331define <vscale x 4 x i32> @vp_bswap_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vp_bswap_nxv4i32:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma335; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t336; CHECK-NEXT: lui a0, 16337; CHECK-NEXT: addi a0, a0, -256338; CHECK-NEXT: vand.vx v10, v10, a0, v0.t339; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t340; CHECK-NEXT: vor.vv v10, v10, v12, v0.t341; CHECK-NEXT: vand.vx v12, v8, a0, v0.t342; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t343; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t344; CHECK-NEXT: vor.vv v8, v8, v12, v0.t345; CHECK-NEXT: vor.vv v8, v8, v10, v0.t346; CHECK-NEXT: ret347;348; CHECK-ZVKB-LABEL: vp_bswap_nxv4i32:349; CHECK-ZVKB: # %bb.0:350; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma351; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t352; CHECK-ZVKB-NEXT: ret353 %v = call <vscale x 4 x i32> @llvm.vp.bswap.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 %evl)354 ret <vscale x 4 x i32> %v355}356 357define <vscale x 4 x i32> @vp_bswap_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {358; CHECK-LABEL: vp_bswap_nxv4i32_unmasked:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma361; CHECK-NEXT: vsrl.vi v10, v8, 8362; CHECK-NEXT: lui a0, 16363; CHECK-NEXT: vsrl.vi v12, v8, 24364; CHECK-NEXT: addi a0, a0, -256365; CHECK-NEXT: vand.vx v10, v10, a0366; CHECK-NEXT: vor.vv v10, v10, v12367; CHECK-NEXT: vand.vx v12, v8, a0368; CHECK-NEXT: vsll.vi v12, v12, 8369; CHECK-NEXT: vsll.vi v8, v8, 24370; CHECK-NEXT: vor.vv v8, v8, v12371; CHECK-NEXT: vor.vv v8, v8, v10372; CHECK-NEXT: ret373;374; CHECK-ZVKB-LABEL: vp_bswap_nxv4i32_unmasked:375; CHECK-ZVKB: # %bb.0:376; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma377; CHECK-ZVKB-NEXT: vrev8.v v8, v8378; CHECK-ZVKB-NEXT: ret379 %v = call <vscale x 4 x i32> @llvm.vp.bswap.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)380 ret <vscale x 4 x i32> %v381}382 383define <vscale x 8 x i32> @vp_bswap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {384; CHECK-LABEL: vp_bswap_nxv8i32:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma387; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t388; CHECK-NEXT: lui a0, 16389; CHECK-NEXT: addi a0, a0, -256390; CHECK-NEXT: vand.vx v12, v12, a0, v0.t391; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t392; CHECK-NEXT: vor.vv v12, v12, v16, v0.t393; CHECK-NEXT: vand.vx v16, v8, a0, v0.t394; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t395; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t396; CHECK-NEXT: vor.vv v8, v8, v16, v0.t397; CHECK-NEXT: vor.vv v8, v8, v12, v0.t398; CHECK-NEXT: ret399;400; CHECK-ZVKB-LABEL: vp_bswap_nxv8i32:401; CHECK-ZVKB: # %bb.0:402; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma403; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t404; CHECK-ZVKB-NEXT: ret405 %v = call <vscale x 8 x i32> @llvm.vp.bswap.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 %evl)406 ret <vscale x 8 x i32> %v407}408 409define <vscale x 8 x i32> @vp_bswap_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {410; CHECK-LABEL: vp_bswap_nxv8i32_unmasked:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma413; CHECK-NEXT: vsrl.vi v12, v8, 8414; CHECK-NEXT: lui a0, 16415; CHECK-NEXT: vsrl.vi v16, v8, 24416; CHECK-NEXT: addi a0, a0, -256417; CHECK-NEXT: vand.vx v12, v12, a0418; CHECK-NEXT: vor.vv v12, v12, v16419; CHECK-NEXT: vand.vx v16, v8, a0420; CHECK-NEXT: vsll.vi v16, v16, 8421; CHECK-NEXT: vsll.vi v8, v8, 24422; CHECK-NEXT: vor.vv v8, v8, v16423; CHECK-NEXT: vor.vv v8, v8, v12424; CHECK-NEXT: ret425;426; CHECK-ZVKB-LABEL: vp_bswap_nxv8i32_unmasked:427; CHECK-ZVKB: # %bb.0:428; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma429; CHECK-ZVKB-NEXT: vrev8.v v8, v8430; CHECK-ZVKB-NEXT: ret431 %v = call <vscale x 8 x i32> @llvm.vp.bswap.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)432 ret <vscale x 8 x i32> %v433}434 435define <vscale x 16 x i32> @vp_bswap_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {436; CHECK-LABEL: vp_bswap_nxv16i32:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma439; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t440; CHECK-NEXT: lui a0, 16441; CHECK-NEXT: addi a0, a0, -256442; CHECK-NEXT: vand.vx v16, v16, a0, v0.t443; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t444; CHECK-NEXT: vor.vv v16, v16, v24, v0.t445; CHECK-NEXT: vand.vx v24, v8, a0, v0.t446; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t447; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t448; CHECK-NEXT: vor.vv v8, v8, v24, v0.t449; CHECK-NEXT: vor.vv v8, v8, v16, v0.t450; CHECK-NEXT: ret451;452; CHECK-ZVKB-LABEL: vp_bswap_nxv16i32:453; CHECK-ZVKB: # %bb.0:454; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma455; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t456; CHECK-ZVKB-NEXT: ret457 %v = call <vscale x 16 x i32> @llvm.vp.bswap.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 %evl)458 ret <vscale x 16 x i32> %v459}460 461define <vscale x 16 x i32> @vp_bswap_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {462; CHECK-LABEL: vp_bswap_nxv16i32_unmasked:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma465; CHECK-NEXT: vsrl.vi v16, v8, 8466; CHECK-NEXT: lui a0, 16467; CHECK-NEXT: vsrl.vi v24, v8, 24468; CHECK-NEXT: addi a0, a0, -256469; CHECK-NEXT: vand.vx v16, v16, a0470; CHECK-NEXT: vor.vv v16, v16, v24471; CHECK-NEXT: vand.vx v24, v8, a0472; CHECK-NEXT: vsll.vi v24, v24, 8473; CHECK-NEXT: vsll.vi v8, v8, 24474; CHECK-NEXT: vor.vv v8, v8, v24475; CHECK-NEXT: vor.vv v8, v8, v16476; CHECK-NEXT: ret477;478; CHECK-ZVKB-LABEL: vp_bswap_nxv16i32_unmasked:479; CHECK-ZVKB: # %bb.0:480; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma481; CHECK-ZVKB-NEXT: vrev8.v v8, v8482; CHECK-ZVKB-NEXT: ret483 %v = call <vscale x 16 x i32> @llvm.vp.bswap.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)484 ret <vscale x 16 x i32> %v485}486 487define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {488; RV32-LABEL: vp_bswap_nxv1i64:489; RV32: # %bb.0:490; RV32-NEXT: addi sp, sp, -16491; RV32-NEXT: .cfi_def_cfa_offset 16492; RV32-NEXT: lui a1, 1044480493; RV32-NEXT: li a2, 56494; RV32-NEXT: lui a3, 16495; RV32-NEXT: li a4, 40496; RV32-NEXT: lui a5, 4080497; RV32-NEXT: addi a6, sp, 8498; RV32-NEXT: sw a1, 8(sp)499; RV32-NEXT: sw zero, 12(sp)500; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma501; RV32-NEXT: vsll.vx v9, v8, a2, v0.t502; RV32-NEXT: addi a0, a3, -256503; RV32-NEXT: vand.vx v10, v8, a0, v0.t504; RV32-NEXT: vlse64.v v11, (a6), zero505; RV32-NEXT: vsll.vx v10, v10, a4, v0.t506; RV32-NEXT: vor.vv v9, v9, v10, v0.t507; RV32-NEXT: vand.vx v10, v8, a5, v0.t508; RV32-NEXT: vsll.vi v10, v10, 24, v0.t509; RV32-NEXT: vand.vv v12, v8, v11, v0.t510; RV32-NEXT: vsll.vi v12, v12, 8, v0.t511; RV32-NEXT: vor.vv v10, v10, v12, v0.t512; RV32-NEXT: vor.vv v9, v9, v10, v0.t513; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t514; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t515; RV32-NEXT: vand.vx v12, v12, a0, v0.t516; RV32-NEXT: vor.vv v10, v12, v10, v0.t517; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t518; RV32-NEXT: vand.vx v12, v12, a5, v0.t519; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t520; RV32-NEXT: vand.vv v8, v8, v11, v0.t521; RV32-NEXT: vor.vv v8, v8, v12, v0.t522; RV32-NEXT: vor.vv v8, v8, v10, v0.t523; RV32-NEXT: vor.vv v8, v9, v8, v0.t524; RV32-NEXT: addi sp, sp, 16525; RV32-NEXT: .cfi_def_cfa_offset 0526; RV32-NEXT: ret527;528; RV64-LABEL: vp_bswap_nxv1i64:529; RV64: # %bb.0:530; RV64-NEXT: lui a1, 4080531; RV64-NEXT: li a2, 255532; RV64-NEXT: li a3, 56533; RV64-NEXT: lui a4, 16534; RV64-NEXT: li a5, 40535; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma536; RV64-NEXT: vand.vx v9, v8, a1, v0.t537; RV64-NEXT: slli a2, a2, 24538; RV64-NEXT: addi a0, a4, -256539; RV64-NEXT: vsll.vi v9, v9, 24, v0.t540; RV64-NEXT: vand.vx v10, v8, a2, v0.t541; RV64-NEXT: vsll.vi v10, v10, 8, v0.t542; RV64-NEXT: vor.vv v9, v9, v10, v0.t543; RV64-NEXT: vsll.vx v10, v8, a3, v0.t544; RV64-NEXT: vand.vx v11, v8, a0, v0.t545; RV64-NEXT: vsll.vx v11, v11, a5, v0.t546; RV64-NEXT: vor.vv v10, v10, v11, v0.t547; RV64-NEXT: vor.vv v9, v10, v9, v0.t548; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t549; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t550; RV64-NEXT: vand.vx v11, v11, a0, v0.t551; RV64-NEXT: vor.vv v10, v11, v10, v0.t552; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t553; RV64-NEXT: vand.vx v11, v11, a1, v0.t554; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t555; RV64-NEXT: vand.vx v8, v8, a2, v0.t556; RV64-NEXT: vor.vv v8, v8, v11, v0.t557; RV64-NEXT: vor.vv v8, v8, v10, v0.t558; RV64-NEXT: vor.vv v8, v9, v8, v0.t559; RV64-NEXT: ret560;561; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64:562; CHECK-ZVKB: # %bb.0:563; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma564; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t565; CHECK-ZVKB-NEXT: ret566 %v = call <vscale x 1 x i64> @llvm.vp.bswap.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 %evl)567 ret <vscale x 1 x i64> %v568}569 570define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {571; RV32-LABEL: vp_bswap_nxv1i64_unmasked:572; RV32: # %bb.0:573; RV32-NEXT: addi sp, sp, -16574; RV32-NEXT: .cfi_def_cfa_offset 16575; RV32-NEXT: lui a1, 1044480576; RV32-NEXT: li a2, 56577; RV32-NEXT: lui a3, 16578; RV32-NEXT: li a4, 40579; RV32-NEXT: lui a5, 4080580; RV32-NEXT: addi a6, sp, 8581; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma582; RV32-NEXT: vsrl.vi v9, v8, 24583; RV32-NEXT: sw a1, 8(sp)584; RV32-NEXT: sw zero, 12(sp)585; RV32-NEXT: vsll.vx v10, v8, a2586; RV32-NEXT: addi a0, a3, -256587; RV32-NEXT: vsrl.vx v11, v8, a2588; RV32-NEXT: vsrl.vx v12, v8, a4589; RV32-NEXT: vand.vx v13, v8, a0590; RV32-NEXT: vand.vx v12, v12, a0591; RV32-NEXT: vor.vv v11, v12, v11592; RV32-NEXT: vlse64.v v12, (a6), zero593; RV32-NEXT: vsll.vx v13, v13, a4594; RV32-NEXT: vor.vv v10, v10, v13595; RV32-NEXT: vsrl.vi v13, v8, 8596; RV32-NEXT: vand.vx v9, v9, a5597; RV32-NEXT: vand.vv v13, v13, v12598; RV32-NEXT: vor.vv v9, v13, v9599; RV32-NEXT: vand.vv v12, v8, v12600; RV32-NEXT: vand.vx v8, v8, a5601; RV32-NEXT: vsll.vi v8, v8, 24602; RV32-NEXT: vsll.vi v12, v12, 8603; RV32-NEXT: vor.vv v8, v8, v12604; RV32-NEXT: vor.vv v8, v10, v8605; RV32-NEXT: vor.vv v9, v9, v11606; RV32-NEXT: vor.vv v8, v8, v9607; RV32-NEXT: addi sp, sp, 16608; RV32-NEXT: .cfi_def_cfa_offset 0609; RV32-NEXT: ret610;611; RV64-LABEL: vp_bswap_nxv1i64_unmasked:612; RV64: # %bb.0:613; RV64-NEXT: lui a1, 4080614; RV64-NEXT: li a2, 255615; RV64-NEXT: li a3, 56616; RV64-NEXT: lui a4, 16617; RV64-NEXT: li a5, 40618; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma619; RV64-NEXT: vsrl.vi v9, v8, 24620; RV64-NEXT: vsrl.vi v10, v8, 8621; RV64-NEXT: addi a0, a4, -256622; RV64-NEXT: vsrl.vx v11, v8, a3623; RV64-NEXT: vsrl.vx v12, v8, a5624; RV64-NEXT: vand.vx v12, v12, a0625; RV64-NEXT: vor.vv v11, v12, v11626; RV64-NEXT: vand.vx v12, v8, a1627; RV64-NEXT: slli a2, a2, 24628; RV64-NEXT: vand.vx v9, v9, a1629; RV64-NEXT: vsll.vi v12, v12, 24630; RV64-NEXT: vand.vx v10, v10, a2631; RV64-NEXT: vor.vv v9, v10, v9632; RV64-NEXT: vand.vx v10, v8, a2633; RV64-NEXT: vsll.vi v10, v10, 8634; RV64-NEXT: vor.vv v10, v12, v10635; RV64-NEXT: vsll.vx v12, v8, a3636; RV64-NEXT: vand.vx v8, v8, a0637; RV64-NEXT: vsll.vx v8, v8, a5638; RV64-NEXT: vor.vv v8, v12, v8639; RV64-NEXT: vor.vv v8, v8, v10640; RV64-NEXT: vor.vv v9, v9, v11641; RV64-NEXT: vor.vv v8, v8, v9642; RV64-NEXT: ret643;644; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64_unmasked:645; CHECK-ZVKB: # %bb.0:646; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma647; CHECK-ZVKB-NEXT: vrev8.v v8, v8648; CHECK-ZVKB-NEXT: ret649 %v = call <vscale x 1 x i64> @llvm.vp.bswap.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)650 ret <vscale x 1 x i64> %v651}652 653define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {654; RV32-LABEL: vp_bswap_nxv2i64:655; RV32: # %bb.0:656; RV32-NEXT: addi sp, sp, -16657; RV32-NEXT: .cfi_def_cfa_offset 16658; RV32-NEXT: lui a1, 1044480659; RV32-NEXT: li a2, 56660; RV32-NEXT: lui a3, 16661; RV32-NEXT: li a4, 40662; RV32-NEXT: lui a5, 4080663; RV32-NEXT: addi a6, sp, 8664; RV32-NEXT: sw a1, 8(sp)665; RV32-NEXT: sw zero, 12(sp)666; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma667; RV32-NEXT: vsll.vx v10, v8, a2, v0.t668; RV32-NEXT: addi a0, a3, -256669; RV32-NEXT: vand.vx v12, v8, a0, v0.t670; RV32-NEXT: vlse64.v v14, (a6), zero671; RV32-NEXT: vsll.vx v12, v12, a4, v0.t672; RV32-NEXT: vor.vv v10, v10, v12, v0.t673; RV32-NEXT: vand.vx v12, v8, a5, v0.t674; RV32-NEXT: vsll.vi v12, v12, 24, v0.t675; RV32-NEXT: vand.vv v16, v8, v14, v0.t676; RV32-NEXT: vsll.vi v16, v16, 8, v0.t677; RV32-NEXT: vor.vv v12, v12, v16, v0.t678; RV32-NEXT: vor.vv v10, v10, v12, v0.t679; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t680; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t681; RV32-NEXT: vand.vx v16, v16, a0, v0.t682; RV32-NEXT: vor.vv v12, v16, v12, v0.t683; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t684; RV32-NEXT: vand.vx v16, v16, a5, v0.t685; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t686; RV32-NEXT: vand.vv v8, v8, v14, v0.t687; RV32-NEXT: vor.vv v8, v8, v16, v0.t688; RV32-NEXT: vor.vv v8, v8, v12, v0.t689; RV32-NEXT: vor.vv v8, v10, v8, v0.t690; RV32-NEXT: addi sp, sp, 16691; RV32-NEXT: .cfi_def_cfa_offset 0692; RV32-NEXT: ret693;694; RV64-LABEL: vp_bswap_nxv2i64:695; RV64: # %bb.0:696; RV64-NEXT: lui a1, 4080697; RV64-NEXT: li a2, 255698; RV64-NEXT: li a3, 56699; RV64-NEXT: lui a4, 16700; RV64-NEXT: li a5, 40701; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma702; RV64-NEXT: vand.vx v10, v8, a1, v0.t703; RV64-NEXT: slli a2, a2, 24704; RV64-NEXT: addi a0, a4, -256705; RV64-NEXT: vsll.vi v10, v10, 24, v0.t706; RV64-NEXT: vand.vx v12, v8, a2, v0.t707; RV64-NEXT: vsll.vi v12, v12, 8, v0.t708; RV64-NEXT: vor.vv v10, v10, v12, v0.t709; RV64-NEXT: vsll.vx v12, v8, a3, v0.t710; RV64-NEXT: vand.vx v14, v8, a0, v0.t711; RV64-NEXT: vsll.vx v14, v14, a5, v0.t712; RV64-NEXT: vor.vv v12, v12, v14, v0.t713; RV64-NEXT: vor.vv v10, v12, v10, v0.t714; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t715; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t716; RV64-NEXT: vand.vx v14, v14, a0, v0.t717; RV64-NEXT: vor.vv v12, v14, v12, v0.t718; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t719; RV64-NEXT: vand.vx v14, v14, a1, v0.t720; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t721; RV64-NEXT: vand.vx v8, v8, a2, v0.t722; RV64-NEXT: vor.vv v8, v8, v14, v0.t723; RV64-NEXT: vor.vv v8, v8, v12, v0.t724; RV64-NEXT: vor.vv v8, v10, v8, v0.t725; RV64-NEXT: ret726;727; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64:728; CHECK-ZVKB: # %bb.0:729; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma730; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t731; CHECK-ZVKB-NEXT: ret732 %v = call <vscale x 2 x i64> @llvm.vp.bswap.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 %evl)733 ret <vscale x 2 x i64> %v734}735 736define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {737; RV32-LABEL: vp_bswap_nxv2i64_unmasked:738; RV32: # %bb.0:739; RV32-NEXT: addi sp, sp, -16740; RV32-NEXT: .cfi_def_cfa_offset 16741; RV32-NEXT: lui a1, 1044480742; RV32-NEXT: li a2, 56743; RV32-NEXT: lui a3, 16744; RV32-NEXT: li a4, 40745; RV32-NEXT: lui a5, 4080746; RV32-NEXT: addi a6, sp, 8747; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma748; RV32-NEXT: vsrl.vi v10, v8, 24749; RV32-NEXT: sw a1, 8(sp)750; RV32-NEXT: sw zero, 12(sp)751; RV32-NEXT: vsll.vx v12, v8, a2752; RV32-NEXT: addi a0, a3, -256753; RV32-NEXT: vsrl.vx v14, v8, a2754; RV32-NEXT: vsrl.vx v16, v8, a4755; RV32-NEXT: vand.vx v18, v8, a0756; RV32-NEXT: vand.vx v16, v16, a0757; RV32-NEXT: vor.vv v14, v16, v14758; RV32-NEXT: vlse64.v v16, (a6), zero759; RV32-NEXT: vsll.vx v18, v18, a4760; RV32-NEXT: vor.vv v12, v12, v18761; RV32-NEXT: vsrl.vi v18, v8, 8762; RV32-NEXT: vand.vx v10, v10, a5763; RV32-NEXT: vand.vv v18, v18, v16764; RV32-NEXT: vor.vv v10, v18, v10765; RV32-NEXT: vand.vv v16, v8, v16766; RV32-NEXT: vand.vx v8, v8, a5767; RV32-NEXT: vsll.vi v8, v8, 24768; RV32-NEXT: vsll.vi v16, v16, 8769; RV32-NEXT: vor.vv v8, v8, v16770; RV32-NEXT: vor.vv v8, v12, v8771; RV32-NEXT: vor.vv v10, v10, v14772; RV32-NEXT: vor.vv v8, v8, v10773; RV32-NEXT: addi sp, sp, 16774; RV32-NEXT: .cfi_def_cfa_offset 0775; RV32-NEXT: ret776;777; RV64-LABEL: vp_bswap_nxv2i64_unmasked:778; RV64: # %bb.0:779; RV64-NEXT: lui a1, 4080780; RV64-NEXT: li a2, 255781; RV64-NEXT: li a3, 56782; RV64-NEXT: lui a4, 16783; RV64-NEXT: li a5, 40784; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma785; RV64-NEXT: vsrl.vi v10, v8, 24786; RV64-NEXT: vsrl.vi v12, v8, 8787; RV64-NEXT: addi a0, a4, -256788; RV64-NEXT: vsrl.vx v14, v8, a3789; RV64-NEXT: vsrl.vx v16, v8, a5790; RV64-NEXT: vand.vx v16, v16, a0791; RV64-NEXT: vor.vv v14, v16, v14792; RV64-NEXT: vand.vx v16, v8, a1793; RV64-NEXT: slli a2, a2, 24794; RV64-NEXT: vand.vx v10, v10, a1795; RV64-NEXT: vsll.vi v16, v16, 24796; RV64-NEXT: vand.vx v12, v12, a2797; RV64-NEXT: vor.vv v10, v12, v10798; RV64-NEXT: vand.vx v12, v8, a2799; RV64-NEXT: vsll.vi v12, v12, 8800; RV64-NEXT: vor.vv v12, v16, v12801; RV64-NEXT: vsll.vx v16, v8, a3802; RV64-NEXT: vand.vx v8, v8, a0803; RV64-NEXT: vsll.vx v8, v8, a5804; RV64-NEXT: vor.vv v8, v16, v8805; RV64-NEXT: vor.vv v8, v8, v12806; RV64-NEXT: vor.vv v10, v10, v14807; RV64-NEXT: vor.vv v8, v8, v10808; RV64-NEXT: ret809;810; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64_unmasked:811; CHECK-ZVKB: # %bb.0:812; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma813; CHECK-ZVKB-NEXT: vrev8.v v8, v8814; CHECK-ZVKB-NEXT: ret815 %v = call <vscale x 2 x i64> @llvm.vp.bswap.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)816 ret <vscale x 2 x i64> %v817}818 819define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {820; RV32-LABEL: vp_bswap_nxv4i64:821; RV32: # %bb.0:822; RV32-NEXT: addi sp, sp, -16823; RV32-NEXT: .cfi_def_cfa_offset 16824; RV32-NEXT: lui a1, 1044480825; RV32-NEXT: li a2, 56826; RV32-NEXT: lui a3, 16827; RV32-NEXT: li a4, 40828; RV32-NEXT: lui a5, 4080829; RV32-NEXT: addi a6, sp, 8830; RV32-NEXT: sw a1, 8(sp)831; RV32-NEXT: sw zero, 12(sp)832; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma833; RV32-NEXT: vsll.vx v16, v8, a2, v0.t834; RV32-NEXT: addi a0, a3, -256835; RV32-NEXT: vand.vx v20, v8, a0, v0.t836; RV32-NEXT: vlse64.v v12, (a6), zero837; RV32-NEXT: vsll.vx v20, v20, a4, v0.t838; RV32-NEXT: vor.vv v16, v16, v20, v0.t839; RV32-NEXT: vand.vx v20, v8, a5, v0.t840; RV32-NEXT: vsll.vi v20, v20, 24, v0.t841; RV32-NEXT: vand.vv v24, v8, v12, v0.t842; RV32-NEXT: vsll.vi v24, v24, 8, v0.t843; RV32-NEXT: vor.vv v20, v20, v24, v0.t844; RV32-NEXT: vor.vv v16, v16, v20, v0.t845; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t846; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t847; RV32-NEXT: vand.vx v24, v24, a0, v0.t848; RV32-NEXT: vor.vv v20, v24, v20, v0.t849; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t850; RV32-NEXT: vand.vx v24, v24, a5, v0.t851; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t852; RV32-NEXT: vand.vv v8, v8, v12, v0.t853; RV32-NEXT: vor.vv v8, v8, v24, v0.t854; RV32-NEXT: vor.vv v8, v8, v20, v0.t855; RV32-NEXT: vor.vv v8, v16, v8, v0.t856; RV32-NEXT: addi sp, sp, 16857; RV32-NEXT: .cfi_def_cfa_offset 0858; RV32-NEXT: ret859;860; RV64-LABEL: vp_bswap_nxv4i64:861; RV64: # %bb.0:862; RV64-NEXT: lui a1, 4080863; RV64-NEXT: li a2, 255864; RV64-NEXT: li a3, 56865; RV64-NEXT: lui a4, 16866; RV64-NEXT: li a5, 40867; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma868; RV64-NEXT: vand.vx v12, v8, a1, v0.t869; RV64-NEXT: slli a2, a2, 24870; RV64-NEXT: addi a0, a4, -256871; RV64-NEXT: vsll.vi v12, v12, 24, v0.t872; RV64-NEXT: vand.vx v16, v8, a2, v0.t873; RV64-NEXT: vsll.vi v16, v16, 8, v0.t874; RV64-NEXT: vor.vv v12, v12, v16, v0.t875; RV64-NEXT: vsll.vx v16, v8, a3, v0.t876; RV64-NEXT: vand.vx v20, v8, a0, v0.t877; RV64-NEXT: vsll.vx v20, v20, a5, v0.t878; RV64-NEXT: vor.vv v16, v16, v20, v0.t879; RV64-NEXT: vor.vv v12, v16, v12, v0.t880; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t881; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t882; RV64-NEXT: vand.vx v20, v20, a0, v0.t883; RV64-NEXT: vor.vv v16, v20, v16, v0.t884; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t885; RV64-NEXT: vand.vx v20, v20, a1, v0.t886; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t887; RV64-NEXT: vand.vx v8, v8, a2, v0.t888; RV64-NEXT: vor.vv v8, v8, v20, v0.t889; RV64-NEXT: vor.vv v8, v8, v16, v0.t890; RV64-NEXT: vor.vv v8, v12, v8, v0.t891; RV64-NEXT: ret892;893; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64:894; CHECK-ZVKB: # %bb.0:895; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma896; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t897; CHECK-ZVKB-NEXT: ret898 %v = call <vscale x 4 x i64> @llvm.vp.bswap.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 %evl)899 ret <vscale x 4 x i64> %v900}901 902define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {903; RV32-LABEL: vp_bswap_nxv4i64_unmasked:904; RV32: # %bb.0:905; RV32-NEXT: addi sp, sp, -16906; RV32-NEXT: .cfi_def_cfa_offset 16907; RV32-NEXT: lui a1, 1044480908; RV32-NEXT: li a2, 56909; RV32-NEXT: lui a3, 16910; RV32-NEXT: li a4, 40911; RV32-NEXT: lui a5, 4080912; RV32-NEXT: addi a6, sp, 8913; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma914; RV32-NEXT: vsrl.vi v12, v8, 24915; RV32-NEXT: sw a1, 8(sp)916; RV32-NEXT: sw zero, 12(sp)917; RV32-NEXT: vsll.vx v16, v8, a2918; RV32-NEXT: addi a0, a3, -256919; RV32-NEXT: vsrl.vx v20, v8, a2920; RV32-NEXT: vsrl.vx v24, v8, a4921; RV32-NEXT: vand.vx v28, v8, a0922; RV32-NEXT: vand.vx v24, v24, a0923; RV32-NEXT: vor.vv v20, v24, v20924; RV32-NEXT: vlse64.v v24, (a6), zero925; RV32-NEXT: vsll.vx v28, v28, a4926; RV32-NEXT: vor.vv v16, v16, v28927; RV32-NEXT: vsrl.vi v28, v8, 8928; RV32-NEXT: vand.vx v12, v12, a5929; RV32-NEXT: vand.vv v28, v28, v24930; RV32-NEXT: vor.vv v12, v28, v12931; RV32-NEXT: vand.vv v24, v8, v24932; RV32-NEXT: vand.vx v8, v8, a5933; RV32-NEXT: vsll.vi v8, v8, 24934; RV32-NEXT: vsll.vi v24, v24, 8935; RV32-NEXT: vor.vv v8, v8, v24936; RV32-NEXT: vor.vv v8, v16, v8937; RV32-NEXT: vor.vv v12, v12, v20938; RV32-NEXT: vor.vv v8, v8, v12939; RV32-NEXT: addi sp, sp, 16940; RV32-NEXT: .cfi_def_cfa_offset 0941; RV32-NEXT: ret942;943; RV64-LABEL: vp_bswap_nxv4i64_unmasked:944; RV64: # %bb.0:945; RV64-NEXT: lui a1, 4080946; RV64-NEXT: li a2, 255947; RV64-NEXT: li a3, 56948; RV64-NEXT: lui a4, 16949; RV64-NEXT: li a5, 40950; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma951; RV64-NEXT: vsrl.vi v12, v8, 24952; RV64-NEXT: vsrl.vi v16, v8, 8953; RV64-NEXT: addi a0, a4, -256954; RV64-NEXT: vsrl.vx v20, v8, a3955; RV64-NEXT: vsrl.vx v24, v8, a5956; RV64-NEXT: vand.vx v24, v24, a0957; RV64-NEXT: vor.vv v20, v24, v20958; RV64-NEXT: vand.vx v24, v8, a1959; RV64-NEXT: slli a2, a2, 24960; RV64-NEXT: vand.vx v12, v12, a1961; RV64-NEXT: vsll.vi v24, v24, 24962; RV64-NEXT: vand.vx v16, v16, a2963; RV64-NEXT: vor.vv v12, v16, v12964; RV64-NEXT: vand.vx v16, v8, a2965; RV64-NEXT: vsll.vi v16, v16, 8966; RV64-NEXT: vor.vv v16, v24, v16967; RV64-NEXT: vsll.vx v24, v8, a3968; RV64-NEXT: vand.vx v8, v8, a0969; RV64-NEXT: vsll.vx v8, v8, a5970; RV64-NEXT: vor.vv v8, v24, v8971; RV64-NEXT: vor.vv v8, v8, v16972; RV64-NEXT: vor.vv v12, v12, v20973; RV64-NEXT: vor.vv v8, v8, v12974; RV64-NEXT: ret975;976; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64_unmasked:977; CHECK-ZVKB: # %bb.0:978; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma979; CHECK-ZVKB-NEXT: vrev8.v v8, v8980; CHECK-ZVKB-NEXT: ret981 %v = call <vscale x 4 x i64> @llvm.vp.bswap.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)982 ret <vscale x 4 x i64> %v983}984 985define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {986; RV32-LABEL: vp_bswap_nxv7i64:987; RV32: # %bb.0:988; RV32-NEXT: addi sp, sp, -16989; RV32-NEXT: .cfi_def_cfa_offset 16990; RV32-NEXT: csrr a1, vlenb991; RV32-NEXT: li a2, 24992; RV32-NEXT: mul a1, a1, a2993; RV32-NEXT: sub sp, sp, a1994; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb995; RV32-NEXT: lui a1, 1044480996; RV32-NEXT: li a2, 56997; RV32-NEXT: lui a3, 16998; RV32-NEXT: li a4, 40999; RV32-NEXT: addi a5, sp, 81000; RV32-NEXT: sw a1, 8(sp)1001; RV32-NEXT: sw zero, 12(sp)1002; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1003; RV32-NEXT: vsll.vx v16, v8, a2, v0.t1004; RV32-NEXT: addi a0, a3, -2561005; RV32-NEXT: vand.vx v24, v8, a0, v0.t1006; RV32-NEXT: vsll.vx v24, v24, a4, v0.t1007; RV32-NEXT: vor.vv v16, v16, v24, v0.t1008; RV32-NEXT: csrr a1, vlenb1009; RV32-NEXT: slli a1, a1, 31010; RV32-NEXT: add a1, sp, a11011; RV32-NEXT: addi a1, a1, 161012; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1013; RV32-NEXT: vlse64.v v16, (a5), zero1014; RV32-NEXT: csrr a1, vlenb1015; RV32-NEXT: slli a1, a1, 41016; RV32-NEXT: add a1, sp, a11017; RV32-NEXT: addi a1, a1, 161018; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1019; RV32-NEXT: lui a1, 40801020; RV32-NEXT: vand.vx v16, v8, a1, v0.t1021; RV32-NEXT: vsll.vi v24, v16, 24, v0.t1022; RV32-NEXT: csrr a3, vlenb1023; RV32-NEXT: slli a3, a3, 41024; RV32-NEXT: add a3, sp, a31025; RV32-NEXT: addi a3, a3, 161026; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1027; RV32-NEXT: vand.vv v16, v8, v16, v0.t1028; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1029; RV32-NEXT: vor.vv v16, v24, v16, v0.t1030; RV32-NEXT: csrr a3, vlenb1031; RV32-NEXT: slli a3, a3, 31032; RV32-NEXT: add a3, sp, a31033; RV32-NEXT: addi a3, a3, 161034; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload1035; RV32-NEXT: vor.vv v16, v24, v16, v0.t1036; RV32-NEXT: csrr a3, vlenb1037; RV32-NEXT: slli a3, a3, 31038; RV32-NEXT: add a3, sp, a31039; RV32-NEXT: addi a3, a3, 161040; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1041; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1042; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t1043; RV32-NEXT: vand.vx v24, v24, a0, v0.t1044; RV32-NEXT: vor.vv v16, v24, v16, v0.t1045; RV32-NEXT: addi a0, sp, 161046; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1047; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1048; RV32-NEXT: vand.vx v24, v24, a1, v0.t1049; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1050; RV32-NEXT: csrr a0, vlenb1051; RV32-NEXT: slli a0, a0, 41052; RV32-NEXT: add a0, sp, a01053; RV32-NEXT: addi a0, a0, 161054; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1055; RV32-NEXT: vand.vv v8, v8, v16, v0.t1056; RV32-NEXT: vor.vv v8, v8, v24, v0.t1057; RV32-NEXT: addi a0, sp, 161058; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1059; RV32-NEXT: vor.vv v8, v8, v16, v0.t1060; RV32-NEXT: csrr a0, vlenb1061; RV32-NEXT: slli a0, a0, 31062; RV32-NEXT: add a0, sp, a01063; RV32-NEXT: addi a0, a0, 161064; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1065; RV32-NEXT: vor.vv v8, v16, v8, v0.t1066; RV32-NEXT: csrr a0, vlenb1067; RV32-NEXT: li a1, 241068; RV32-NEXT: mul a0, a0, a11069; RV32-NEXT: add sp, sp, a01070; RV32-NEXT: .cfi_def_cfa sp, 161071; RV32-NEXT: addi sp, sp, 161072; RV32-NEXT: .cfi_def_cfa_offset 01073; RV32-NEXT: ret1074;1075; RV64-LABEL: vp_bswap_nxv7i64:1076; RV64: # %bb.0:1077; RV64-NEXT: addi sp, sp, -161078; RV64-NEXT: .cfi_def_cfa_offset 161079; RV64-NEXT: csrr a1, vlenb1080; RV64-NEXT: slli a1, a1, 31081; RV64-NEXT: sub sp, sp, a11082; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1083; RV64-NEXT: lui a1, 40801084; RV64-NEXT: li a2, 2551085; RV64-NEXT: li a3, 561086; RV64-NEXT: lui a4, 161087; RV64-NEXT: li a5, 401088; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1089; RV64-NEXT: vand.vx v16, v8, a1, v0.t1090; RV64-NEXT: slli a2, a2, 241091; RV64-NEXT: addi a0, a4, -2561092; RV64-NEXT: vsll.vi v16, v16, 24, v0.t1093; RV64-NEXT: vand.vx v24, v8, a2, v0.t1094; RV64-NEXT: vsll.vi v24, v24, 8, v0.t1095; RV64-NEXT: vor.vv v16, v16, v24, v0.t1096; RV64-NEXT: addi a4, sp, 161097; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1098; RV64-NEXT: vsll.vx v24, v8, a3, v0.t1099; RV64-NEXT: vand.vx v16, v8, a0, v0.t1100; RV64-NEXT: vsll.vx v16, v16, a5, v0.t1101; RV64-NEXT: vor.vv v16, v24, v16, v0.t1102; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload1103; RV64-NEXT: vor.vv v16, v16, v24, v0.t1104; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1105; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t1106; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t1107; RV64-NEXT: vand.vx v16, v16, a0, v0.t1108; RV64-NEXT: vor.vv v24, v16, v24, v0.t1109; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t1110; RV64-NEXT: vand.vx v16, v16, a1, v0.t1111; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1112; RV64-NEXT: vand.vx v8, v8, a2, v0.t1113; RV64-NEXT: vor.vv v8, v8, v16, v0.t1114; RV64-NEXT: vor.vv v8, v8, v24, v0.t1115; RV64-NEXT: addi a0, sp, 161116; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1117; RV64-NEXT: vor.vv v8, v16, v8, v0.t1118; RV64-NEXT: csrr a0, vlenb1119; RV64-NEXT: slli a0, a0, 31120; RV64-NEXT: add sp, sp, a01121; RV64-NEXT: .cfi_def_cfa sp, 161122; RV64-NEXT: addi sp, sp, 161123; RV64-NEXT: .cfi_def_cfa_offset 01124; RV64-NEXT: ret1125;1126; CHECK-ZVKB-LABEL: vp_bswap_nxv7i64:1127; CHECK-ZVKB: # %bb.0:1128; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1129; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t1130; CHECK-ZVKB-NEXT: ret1131 %v = call <vscale x 7 x i64> @llvm.vp.bswap.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 %evl)1132 ret <vscale x 7 x i64> %v1133}1134 1135define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {1136; RV32-LABEL: vp_bswap_nxv7i64_unmasked:1137; RV32: # %bb.0:1138; RV32-NEXT: addi sp, sp, -161139; RV32-NEXT: .cfi_def_cfa_offset 161140; RV32-NEXT: csrr a1, vlenb1141; RV32-NEXT: slli a1, a1, 41142; RV32-NEXT: sub sp, sp, a11143; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1144; RV32-NEXT: lui a1, 10444801145; RV32-NEXT: li a2, 561146; RV32-NEXT: lui a3, 161147; RV32-NEXT: li a4, 401148; RV32-NEXT: lui a5, 40801149; RV32-NEXT: addi a6, sp, 81150; RV32-NEXT: sw a1, 8(sp)1151; RV32-NEXT: sw zero, 12(sp)1152; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1153; RV32-NEXT: vsll.vx v24, v8, a21154; RV32-NEXT: addi a0, a3, -2561155; RV32-NEXT: vsrl.vx v16, v8, a21156; RV32-NEXT: vsrl.vx v0, v8, a41157; RV32-NEXT: vand.vx v0, v0, a01158; RV32-NEXT: vor.vv v16, v0, v161159; RV32-NEXT: csrr a1, vlenb1160; RV32-NEXT: slli a1, a1, 31161; RV32-NEXT: add a1, sp, a11162; RV32-NEXT: addi a1, a1, 161163; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1164; RV32-NEXT: vand.vx v0, v8, a01165; RV32-NEXT: vsll.vx v0, v0, a41166; RV32-NEXT: vor.vv v16, v24, v01167; RV32-NEXT: addi a0, sp, 161168; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1169; RV32-NEXT: vlse64.v v0, (a6), zero1170; RV32-NEXT: vsrl.vi v16, v8, 241171; RV32-NEXT: vand.vx v16, v16, a51172; RV32-NEXT: vsrl.vi v24, v8, 81173; RV32-NEXT: vand.vv v24, v24, v01174; RV32-NEXT: vor.vv v16, v24, v161175; RV32-NEXT: vand.vv v24, v8, v01176; RV32-NEXT: vand.vx v8, v8, a51177; RV32-NEXT: vsll.vi v8, v8, 241178; RV32-NEXT: vsll.vi v24, v24, 81179; RV32-NEXT: vor.vv v8, v8, v241180; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1181; RV32-NEXT: vor.vv v8, v24, v81182; RV32-NEXT: csrr a0, vlenb1183; RV32-NEXT: slli a0, a0, 31184; RV32-NEXT: add a0, sp, a01185; RV32-NEXT: addi a0, a0, 161186; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1187; RV32-NEXT: vor.vv v16, v16, v241188; RV32-NEXT: vor.vv v8, v8, v161189; RV32-NEXT: csrr a0, vlenb1190; RV32-NEXT: slli a0, a0, 41191; RV32-NEXT: add sp, sp, a01192; RV32-NEXT: .cfi_def_cfa sp, 161193; RV32-NEXT: addi sp, sp, 161194; RV32-NEXT: .cfi_def_cfa_offset 01195; RV32-NEXT: ret1196;1197; RV64-LABEL: vp_bswap_nxv7i64_unmasked:1198; RV64: # %bb.0:1199; RV64-NEXT: addi sp, sp, -161200; RV64-NEXT: .cfi_def_cfa_offset 161201; RV64-NEXT: csrr a1, vlenb1202; RV64-NEXT: slli a1, a1, 31203; RV64-NEXT: sub sp, sp, a11204; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1205; RV64-NEXT: lui a1, 40801206; RV64-NEXT: li a2, 2551207; RV64-NEXT: li a3, 561208; RV64-NEXT: lui a4, 161209; RV64-NEXT: li a5, 401210; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1211; RV64-NEXT: vsrl.vi v24, v8, 241212; RV64-NEXT: addi a0, a4, -2561213; RV64-NEXT: vsrl.vx v16, v8, a31214; RV64-NEXT: vsrl.vx v0, v8, a51215; RV64-NEXT: vand.vx v0, v0, a01216; RV64-NEXT: vor.vv v16, v0, v161217; RV64-NEXT: addi a4, sp, 161218; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1219; RV64-NEXT: vsrl.vi v0, v8, 81220; RV64-NEXT: slli a2, a2, 241221; RV64-NEXT: vand.vx v24, v24, a11222; RV64-NEXT: vand.vx v0, v0, a21223; RV64-NEXT: vor.vv v24, v0, v241224; RV64-NEXT: vand.vx v0, v8, a11225; RV64-NEXT: vsll.vi v0, v0, 241226; RV64-NEXT: vand.vx v16, v8, a21227; RV64-NEXT: vsll.vi v16, v16, 81228; RV64-NEXT: vor.vv v16, v0, v161229; RV64-NEXT: vsll.vx v0, v8, a31230; RV64-NEXT: vand.vx v8, v8, a01231; RV64-NEXT: vsll.vx v8, v8, a51232; RV64-NEXT: vor.vv v8, v0, v81233; RV64-NEXT: vor.vv v8, v8, v161234; RV64-NEXT: addi a0, sp, 161235; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1236; RV64-NEXT: vor.vv v16, v24, v161237; RV64-NEXT: vor.vv v8, v8, v161238; RV64-NEXT: csrr a0, vlenb1239; RV64-NEXT: slli a0, a0, 31240; RV64-NEXT: add sp, sp, a01241; RV64-NEXT: .cfi_def_cfa sp, 161242; RV64-NEXT: addi sp, sp, 161243; RV64-NEXT: .cfi_def_cfa_offset 01244; RV64-NEXT: ret1245;1246; CHECK-ZVKB-LABEL: vp_bswap_nxv7i64_unmasked:1247; CHECK-ZVKB: # %bb.0:1248; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1249; CHECK-ZVKB-NEXT: vrev8.v v8, v81250; CHECK-ZVKB-NEXT: ret1251 %v = call <vscale x 7 x i64> @llvm.vp.bswap.nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)1252 ret <vscale x 7 x i64> %v1253}1254 1255define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1256; RV32-LABEL: vp_bswap_nxv8i64:1257; RV32: # %bb.0:1258; RV32-NEXT: addi sp, sp, -161259; RV32-NEXT: .cfi_def_cfa_offset 161260; RV32-NEXT: csrr a1, vlenb1261; RV32-NEXT: li a2, 241262; RV32-NEXT: mul a1, a1, a21263; RV32-NEXT: sub sp, sp, a11264; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb1265; RV32-NEXT: lui a1, 10444801266; RV32-NEXT: li a2, 561267; RV32-NEXT: lui a3, 161268; RV32-NEXT: li a4, 401269; RV32-NEXT: addi a5, sp, 81270; RV32-NEXT: sw a1, 8(sp)1271; RV32-NEXT: sw zero, 12(sp)1272; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1273; RV32-NEXT: vsll.vx v16, v8, a2, v0.t1274; RV32-NEXT: addi a0, a3, -2561275; RV32-NEXT: vand.vx v24, v8, a0, v0.t1276; RV32-NEXT: vsll.vx v24, v24, a4, v0.t1277; RV32-NEXT: vor.vv v16, v16, v24, v0.t1278; RV32-NEXT: csrr a1, vlenb1279; RV32-NEXT: slli a1, a1, 31280; RV32-NEXT: add a1, sp, a11281; RV32-NEXT: addi a1, a1, 161282; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1283; RV32-NEXT: vlse64.v v16, (a5), zero1284; RV32-NEXT: csrr a1, vlenb1285; RV32-NEXT: slli a1, a1, 41286; RV32-NEXT: add a1, sp, a11287; RV32-NEXT: addi a1, a1, 161288; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1289; RV32-NEXT: lui a1, 40801290; RV32-NEXT: vand.vx v16, v8, a1, v0.t1291; RV32-NEXT: vsll.vi v24, v16, 24, v0.t1292; RV32-NEXT: csrr a3, vlenb1293; RV32-NEXT: slli a3, a3, 41294; RV32-NEXT: add a3, sp, a31295; RV32-NEXT: addi a3, a3, 161296; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload1297; RV32-NEXT: vand.vv v16, v8, v16, v0.t1298; RV32-NEXT: vsll.vi v16, v16, 8, v0.t1299; RV32-NEXT: vor.vv v16, v24, v16, v0.t1300; RV32-NEXT: csrr a3, vlenb1301; RV32-NEXT: slli a3, a3, 31302; RV32-NEXT: add a3, sp, a31303; RV32-NEXT: addi a3, a3, 161304; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload1305; RV32-NEXT: vor.vv v16, v24, v16, v0.t1306; RV32-NEXT: csrr a3, vlenb1307; RV32-NEXT: slli a3, a3, 31308; RV32-NEXT: add a3, sp, a31309; RV32-NEXT: addi a3, a3, 161310; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill1311; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t1312; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t1313; RV32-NEXT: vand.vx v24, v24, a0, v0.t1314; RV32-NEXT: vor.vv v16, v24, v16, v0.t1315; RV32-NEXT: addi a0, sp, 161316; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1317; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t1318; RV32-NEXT: vand.vx v24, v24, a1, v0.t1319; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1320; RV32-NEXT: csrr a0, vlenb1321; RV32-NEXT: slli a0, a0, 41322; RV32-NEXT: add a0, sp, a01323; RV32-NEXT: addi a0, a0, 161324; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1325; RV32-NEXT: vand.vv v8, v8, v16, v0.t1326; RV32-NEXT: vor.vv v8, v8, v24, v0.t1327; RV32-NEXT: addi a0, sp, 161328; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1329; RV32-NEXT: vor.vv v8, v8, v16, v0.t1330; RV32-NEXT: csrr a0, vlenb1331; RV32-NEXT: slli a0, a0, 31332; RV32-NEXT: add a0, sp, a01333; RV32-NEXT: addi a0, a0, 161334; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1335; RV32-NEXT: vor.vv v8, v16, v8, v0.t1336; RV32-NEXT: csrr a0, vlenb1337; RV32-NEXT: li a1, 241338; RV32-NEXT: mul a0, a0, a11339; RV32-NEXT: add sp, sp, a01340; RV32-NEXT: .cfi_def_cfa sp, 161341; RV32-NEXT: addi sp, sp, 161342; RV32-NEXT: .cfi_def_cfa_offset 01343; RV32-NEXT: ret1344;1345; RV64-LABEL: vp_bswap_nxv8i64:1346; RV64: # %bb.0:1347; RV64-NEXT: addi sp, sp, -161348; RV64-NEXT: .cfi_def_cfa_offset 161349; RV64-NEXT: csrr a1, vlenb1350; RV64-NEXT: slli a1, a1, 31351; RV64-NEXT: sub sp, sp, a11352; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1353; RV64-NEXT: lui a1, 40801354; RV64-NEXT: li a2, 2551355; RV64-NEXT: li a3, 561356; RV64-NEXT: lui a4, 161357; RV64-NEXT: li a5, 401358; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1359; RV64-NEXT: vand.vx v16, v8, a1, v0.t1360; RV64-NEXT: slli a2, a2, 241361; RV64-NEXT: addi a0, a4, -2561362; RV64-NEXT: vsll.vi v16, v16, 24, v0.t1363; RV64-NEXT: vand.vx v24, v8, a2, v0.t1364; RV64-NEXT: vsll.vi v24, v24, 8, v0.t1365; RV64-NEXT: vor.vv v16, v16, v24, v0.t1366; RV64-NEXT: addi a4, sp, 161367; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1368; RV64-NEXT: vsll.vx v24, v8, a3, v0.t1369; RV64-NEXT: vand.vx v16, v8, a0, v0.t1370; RV64-NEXT: vsll.vx v16, v16, a5, v0.t1371; RV64-NEXT: vor.vv v16, v24, v16, v0.t1372; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload1373; RV64-NEXT: vor.vv v16, v16, v24, v0.t1374; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1375; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t1376; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t1377; RV64-NEXT: vand.vx v16, v16, a0, v0.t1378; RV64-NEXT: vor.vv v24, v16, v24, v0.t1379; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t1380; RV64-NEXT: vand.vx v16, v16, a1, v0.t1381; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1382; RV64-NEXT: vand.vx v8, v8, a2, v0.t1383; RV64-NEXT: vor.vv v8, v8, v16, v0.t1384; RV64-NEXT: vor.vv v8, v8, v24, v0.t1385; RV64-NEXT: addi a0, sp, 161386; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1387; RV64-NEXT: vor.vv v8, v16, v8, v0.t1388; RV64-NEXT: csrr a0, vlenb1389; RV64-NEXT: slli a0, a0, 31390; RV64-NEXT: add sp, sp, a01391; RV64-NEXT: .cfi_def_cfa sp, 161392; RV64-NEXT: addi sp, sp, 161393; RV64-NEXT: .cfi_def_cfa_offset 01394; RV64-NEXT: ret1395;1396; CHECK-ZVKB-LABEL: vp_bswap_nxv8i64:1397; CHECK-ZVKB: # %bb.0:1398; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1399; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t1400; CHECK-ZVKB-NEXT: ret1401 %v = call <vscale x 8 x i64> @llvm.vp.bswap.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 %evl)1402 ret <vscale x 8 x i64> %v1403}1404 1405define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1406; RV32-LABEL: vp_bswap_nxv8i64_unmasked:1407; RV32: # %bb.0:1408; RV32-NEXT: addi sp, sp, -161409; RV32-NEXT: .cfi_def_cfa_offset 161410; RV32-NEXT: csrr a1, vlenb1411; RV32-NEXT: slli a1, a1, 41412; RV32-NEXT: sub sp, sp, a11413; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1414; RV32-NEXT: lui a1, 10444801415; RV32-NEXT: li a2, 561416; RV32-NEXT: lui a3, 161417; RV32-NEXT: li a4, 401418; RV32-NEXT: lui a5, 40801419; RV32-NEXT: addi a6, sp, 81420; RV32-NEXT: sw a1, 8(sp)1421; RV32-NEXT: sw zero, 12(sp)1422; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1423; RV32-NEXT: vsll.vx v24, v8, a21424; RV32-NEXT: addi a0, a3, -2561425; RV32-NEXT: vsrl.vx v16, v8, a21426; RV32-NEXT: vsrl.vx v0, v8, a41427; RV32-NEXT: vand.vx v0, v0, a01428; RV32-NEXT: vor.vv v16, v0, v161429; RV32-NEXT: csrr a1, vlenb1430; RV32-NEXT: slli a1, a1, 31431; RV32-NEXT: add a1, sp, a11432; RV32-NEXT: addi a1, a1, 161433; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1434; RV32-NEXT: vand.vx v0, v8, a01435; RV32-NEXT: vsll.vx v0, v0, a41436; RV32-NEXT: vor.vv v16, v24, v01437; RV32-NEXT: addi a0, sp, 161438; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill1439; RV32-NEXT: vlse64.v v0, (a6), zero1440; RV32-NEXT: vsrl.vi v16, v8, 241441; RV32-NEXT: vand.vx v16, v16, a51442; RV32-NEXT: vsrl.vi v24, v8, 81443; RV32-NEXT: vand.vv v24, v24, v01444; RV32-NEXT: vor.vv v16, v24, v161445; RV32-NEXT: vand.vv v24, v8, v01446; RV32-NEXT: vand.vx v8, v8, a51447; RV32-NEXT: vsll.vi v8, v8, 241448; RV32-NEXT: vsll.vi v24, v24, 81449; RV32-NEXT: vor.vv v8, v8, v241450; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1451; RV32-NEXT: vor.vv v8, v24, v81452; RV32-NEXT: csrr a0, vlenb1453; RV32-NEXT: slli a0, a0, 31454; RV32-NEXT: add a0, sp, a01455; RV32-NEXT: addi a0, a0, 161456; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload1457; RV32-NEXT: vor.vv v16, v16, v241458; RV32-NEXT: vor.vv v8, v8, v161459; RV32-NEXT: csrr a0, vlenb1460; RV32-NEXT: slli a0, a0, 41461; RV32-NEXT: add sp, sp, a01462; RV32-NEXT: .cfi_def_cfa sp, 161463; RV32-NEXT: addi sp, sp, 161464; RV32-NEXT: .cfi_def_cfa_offset 01465; RV32-NEXT: ret1466;1467; RV64-LABEL: vp_bswap_nxv8i64_unmasked:1468; RV64: # %bb.0:1469; RV64-NEXT: addi sp, sp, -161470; RV64-NEXT: .cfi_def_cfa_offset 161471; RV64-NEXT: csrr a1, vlenb1472; RV64-NEXT: slli a1, a1, 31473; RV64-NEXT: sub sp, sp, a11474; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb1475; RV64-NEXT: lui a1, 40801476; RV64-NEXT: li a2, 2551477; RV64-NEXT: li a3, 561478; RV64-NEXT: lui a4, 161479; RV64-NEXT: li a5, 401480; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma1481; RV64-NEXT: vsrl.vi v24, v8, 241482; RV64-NEXT: addi a0, a4, -2561483; RV64-NEXT: vsrl.vx v16, v8, a31484; RV64-NEXT: vsrl.vx v0, v8, a51485; RV64-NEXT: vand.vx v0, v0, a01486; RV64-NEXT: vor.vv v16, v0, v161487; RV64-NEXT: addi a4, sp, 161488; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill1489; RV64-NEXT: vsrl.vi v0, v8, 81490; RV64-NEXT: slli a2, a2, 241491; RV64-NEXT: vand.vx v24, v24, a11492; RV64-NEXT: vand.vx v0, v0, a21493; RV64-NEXT: vor.vv v24, v0, v241494; RV64-NEXT: vand.vx v0, v8, a11495; RV64-NEXT: vsll.vi v0, v0, 241496; RV64-NEXT: vand.vx v16, v8, a21497; RV64-NEXT: vsll.vi v16, v16, 81498; RV64-NEXT: vor.vv v16, v0, v161499; RV64-NEXT: vsll.vx v0, v8, a31500; RV64-NEXT: vand.vx v8, v8, a01501; RV64-NEXT: vsll.vx v8, v8, a51502; RV64-NEXT: vor.vv v8, v0, v81503; RV64-NEXT: vor.vv v8, v8, v161504; RV64-NEXT: addi a0, sp, 161505; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload1506; RV64-NEXT: vor.vv v16, v24, v161507; RV64-NEXT: vor.vv v8, v8, v161508; RV64-NEXT: csrr a0, vlenb1509; RV64-NEXT: slli a0, a0, 31510; RV64-NEXT: add sp, sp, a01511; RV64-NEXT: .cfi_def_cfa sp, 161512; RV64-NEXT: addi sp, sp, 161513; RV64-NEXT: .cfi_def_cfa_offset 01514; RV64-NEXT: ret1515;1516; CHECK-ZVKB-LABEL: vp_bswap_nxv8i64_unmasked:1517; CHECK-ZVKB: # %bb.0:1518; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma1519; CHECK-ZVKB-NEXT: vrev8.v v8, v81520; CHECK-ZVKB-NEXT: ret1521 %v = call <vscale x 8 x i64> @llvm.vp.bswap.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1522 ret <vscale x 8 x i64> %v1523}1524 1525; Test splitting. Use i16 version for easier check.1526 1527define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {1528; CHECK-LABEL: vp_bswap_nxv64i16:1529; CHECK: # %bb.0:1530; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1531; CHECK-NEXT: vmv1r.v v7, v01532; CHECK-NEXT: csrr a1, vlenb1533; CHECK-NEXT: srli a2, a1, 11534; CHECK-NEXT: slli a1, a1, 21535; CHECK-NEXT: vslidedown.vx v0, v0, a21536; CHECK-NEXT: sub a2, a0, a11537; CHECK-NEXT: sltu a3, a0, a21538; CHECK-NEXT: addi a3, a3, -11539; CHECK-NEXT: and a2, a3, a21540; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1541; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t1542; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t1543; CHECK-NEXT: vor.vv v16, v16, v24, v0.t1544; CHECK-NEXT: bltu a0, a1, .LBB32_21545; CHECK-NEXT: # %bb.1:1546; CHECK-NEXT: mv a0, a11547; CHECK-NEXT: .LBB32_2:1548; CHECK-NEXT: vmv1r.v v0, v71549; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1550; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t1551; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t1552; CHECK-NEXT: vor.vv v8, v8, v24, v0.t1553; CHECK-NEXT: ret1554;1555; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:1556; CHECK-ZVKB: # %bb.0:1557; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma1558; CHECK-ZVKB-NEXT: vmv1r.v v24, v01559; CHECK-ZVKB-NEXT: csrr a1, vlenb1560; CHECK-ZVKB-NEXT: srli a2, a1, 11561; CHECK-ZVKB-NEXT: slli a1, a1, 21562; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a21563; CHECK-ZVKB-NEXT: sub a2, a0, a11564; CHECK-ZVKB-NEXT: sltu a3, a0, a21565; CHECK-ZVKB-NEXT: addi a3, a3, -11566; CHECK-ZVKB-NEXT: and a2, a3, a21567; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma1568; CHECK-ZVKB-NEXT: vrev8.v v16, v16, v0.t1569; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB32_21570; CHECK-ZVKB-NEXT: # %bb.1:1571; CHECK-ZVKB-NEXT: mv a0, a11572; CHECK-ZVKB-NEXT: .LBB32_2:1573; CHECK-ZVKB-NEXT: vmv1r.v v0, v241574; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma1575; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t1576; CHECK-ZVKB-NEXT: ret1577 %v = call <vscale x 64 x i16> @llvm.vp.bswap.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 %evl)1578 ret <vscale x 64 x i16> %v1579}1580 1581define <vscale x 64 x i16> @vp_bswap_nxv64i16_unmasked(<vscale x 64 x i16> %va, i32 zeroext %evl) {1582; CHECK-LABEL: vp_bswap_nxv64i16_unmasked:1583; CHECK: # %bb.0:1584; CHECK-NEXT: csrr a1, vlenb1585; CHECK-NEXT: slli a1, a1, 21586; CHECK-NEXT: sub a2, a0, a11587; CHECK-NEXT: sltu a3, a0, a21588; CHECK-NEXT: addi a3, a3, -11589; CHECK-NEXT: and a2, a3, a21590; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1591; CHECK-NEXT: vsrl.vi v24, v16, 81592; CHECK-NEXT: vsll.vi v16, v16, 81593; CHECK-NEXT: vor.vv v16, v16, v241594; CHECK-NEXT: bltu a0, a1, .LBB33_21595; CHECK-NEXT: # %bb.1:1596; CHECK-NEXT: mv a0, a11597; CHECK-NEXT: .LBB33_2:1598; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1599; CHECK-NEXT: vsrl.vi v24, v8, 81600; CHECK-NEXT: vsll.vi v8, v8, 81601; CHECK-NEXT: vor.vv v8, v8, v241602; CHECK-NEXT: ret1603;1604; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16_unmasked:1605; CHECK-ZVKB: # %bb.0:1606; CHECK-ZVKB-NEXT: csrr a1, vlenb1607; CHECK-ZVKB-NEXT: slli a1, a1, 21608; CHECK-ZVKB-NEXT: sub a2, a0, a11609; CHECK-ZVKB-NEXT: sltu a3, a0, a21610; CHECK-ZVKB-NEXT: addi a3, a3, -11611; CHECK-ZVKB-NEXT: and a2, a3, a21612; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma1613; CHECK-ZVKB-NEXT: vrev8.v v16, v161614; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB33_21615; CHECK-ZVKB-NEXT: # %bb.1:1616; CHECK-ZVKB-NEXT: mv a0, a11617; CHECK-ZVKB-NEXT: .LBB33_2:1618; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma1619; CHECK-ZVKB-NEXT: vrev8.v v8, v81620; CHECK-ZVKB-NEXT: ret1621 %v = call <vscale x 64 x i16> @llvm.vp.bswap.nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> splat (i1 true), i32 %evl)1622 ret <vscale x 64 x i16> %v1623}1624 1625; Test promotion.1626define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1627; RV32-LABEL: vp_bswap_nxv1i48:1628; RV32: # %bb.0:1629; RV32-NEXT: addi sp, sp, -161630; RV32-NEXT: .cfi_def_cfa_offset 161631; RV32-NEXT: lui a1, 10444801632; RV32-NEXT: li a2, 561633; RV32-NEXT: lui a3, 161634; RV32-NEXT: li a4, 401635; RV32-NEXT: lui a5, 40801636; RV32-NEXT: addi a6, sp, 81637; RV32-NEXT: sw a1, 8(sp)1638; RV32-NEXT: sw zero, 12(sp)1639; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma1640; RV32-NEXT: vsll.vx v9, v8, a2, v0.t1641; RV32-NEXT: addi a0, a3, -2561642; RV32-NEXT: vand.vx v10, v8, a0, v0.t1643; RV32-NEXT: vlse64.v v11, (a6), zero1644; RV32-NEXT: vsll.vx v10, v10, a4, v0.t1645; RV32-NEXT: vor.vv v9, v9, v10, v0.t1646; RV32-NEXT: vand.vx v10, v8, a5, v0.t1647; RV32-NEXT: vsll.vi v10, v10, 24, v0.t1648; RV32-NEXT: vand.vv v12, v8, v11, v0.t1649; RV32-NEXT: vsll.vi v12, v12, 8, v0.t1650; RV32-NEXT: vor.vv v10, v10, v12, v0.t1651; RV32-NEXT: vor.vv v9, v9, v10, v0.t1652; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t1653; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t1654; RV32-NEXT: vand.vx v12, v12, a0, v0.t1655; RV32-NEXT: vor.vv v10, v12, v10, v0.t1656; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t1657; RV32-NEXT: vand.vx v12, v12, a5, v0.t1658; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t1659; RV32-NEXT: vand.vv v8, v8, v11, v0.t1660; RV32-NEXT: vor.vv v8, v8, v12, v0.t1661; RV32-NEXT: vor.vv v8, v8, v10, v0.t1662; RV32-NEXT: vor.vv v8, v9, v8, v0.t1663; RV32-NEXT: vsrl.vi v8, v8, 16, v0.t1664; RV32-NEXT: addi sp, sp, 161665; RV32-NEXT: .cfi_def_cfa_offset 01666; RV32-NEXT: ret1667;1668; RV64-LABEL: vp_bswap_nxv1i48:1669; RV64: # %bb.0:1670; RV64-NEXT: lui a1, 40801671; RV64-NEXT: li a2, 2551672; RV64-NEXT: li a3, 561673; RV64-NEXT: lui a4, 161674; RV64-NEXT: li a5, 401675; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma1676; RV64-NEXT: vand.vx v9, v8, a1, v0.t1677; RV64-NEXT: slli a2, a2, 241678; RV64-NEXT: addi a0, a4, -2561679; RV64-NEXT: vsll.vi v9, v9, 24, v0.t1680; RV64-NEXT: vand.vx v10, v8, a2, v0.t1681; RV64-NEXT: vsll.vi v10, v10, 8, v0.t1682; RV64-NEXT: vor.vv v9, v9, v10, v0.t1683; RV64-NEXT: vsll.vx v10, v8, a3, v0.t1684; RV64-NEXT: vand.vx v11, v8, a0, v0.t1685; RV64-NEXT: vsll.vx v11, v11, a5, v0.t1686; RV64-NEXT: vor.vv v10, v10, v11, v0.t1687; RV64-NEXT: vor.vv v9, v10, v9, v0.t1688; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t1689; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t1690; RV64-NEXT: vand.vx v11, v11, a0, v0.t1691; RV64-NEXT: vor.vv v10, v11, v10, v0.t1692; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t1693; RV64-NEXT: vand.vx v11, v11, a1, v0.t1694; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t1695; RV64-NEXT: vand.vx v8, v8, a2, v0.t1696; RV64-NEXT: vor.vv v8, v8, v11, v0.t1697; RV64-NEXT: vor.vv v8, v8, v10, v0.t1698; RV64-NEXT: vor.vv v8, v9, v8, v0.t1699; RV64-NEXT: vsrl.vi v8, v8, 16, v0.t1700; RV64-NEXT: ret1701;1702; CHECK-ZVKB-LABEL: vp_bswap_nxv1i48:1703; CHECK-ZVKB: # %bb.0:1704; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma1705; CHECK-ZVKB-NEXT: vrev8.v v8, v8, v0.t1706; CHECK-ZVKB-NEXT: vsrl.vi v8, v8, 16, v0.t1707; CHECK-ZVKB-NEXT: ret1708 %v = call <vscale x 1 x i48> @llvm.vp.bswap.nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 x i1> %m, i32 %evl)1709 ret <vscale x 1 x i48> %v1710}1711