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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+v -O2 < %s \3; RUN: | FileCheck --check-prefix=SPILL-O2 %s4 5define <vscale x 1 x i32> @test_vector_std(<vscale x 1 x i32> %va) nounwind {6; SPILL-O2-LABEL: test_vector_std:7; SPILL-O2: # %bb.0: # %entry8; SPILL-O2-NEXT: addi sp, sp, -169; SPILL-O2-NEXT: csrr a0, vlenb10; SPILL-O2-NEXT: sub sp, sp, a011; SPILL-O2-NEXT: addi a0, sp, 1612; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill13; SPILL-O2-NEXT: #APP14; SPILL-O2-NEXT: #NO_APP15; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload16; SPILL-O2-NEXT: csrr a0, vlenb17; SPILL-O2-NEXT: add sp, sp, a018; SPILL-O2-NEXT: addi sp, sp, 1619; SPILL-O2-NEXT: ret20entry:21 call void asm sideeffect "",22 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()23 24 ret <vscale x 1 x i32> %va25}26 27define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee(<vscale x 1 x i32> %va) nounwind {28; SPILL-O2-LABEL: test_vector_callee:29; SPILL-O2: # %bb.0: # %entry30; SPILL-O2-NEXT: addi sp, sp, -1631; SPILL-O2-NEXT: csrr a0, vlenb32; SPILL-O2-NEXT: slli a0, a0, 433; SPILL-O2-NEXT: sub sp, sp, a034; SPILL-O2-NEXT: csrr a0, vlenb35; SPILL-O2-NEXT: slli a1, a0, 436; SPILL-O2-NEXT: sub a0, a1, a037; SPILL-O2-NEXT: add a0, sp, a038; SPILL-O2-NEXT: addi a0, a0, 1639; SPILL-O2-NEXT: vs1r.v v1, (a0) # vscale x 8-byte Folded Spill40; SPILL-O2-NEXT: csrr a0, vlenb41; SPILL-O2-NEXT: li a1, 1342; SPILL-O2-NEXT: mul a0, a0, a143; SPILL-O2-NEXT: add a0, sp, a044; SPILL-O2-NEXT: addi a0, a0, 1645; SPILL-O2-NEXT: vs2r.v v2, (a0) # vscale x 16-byte Folded Spill46; SPILL-O2-NEXT: csrr a0, vlenb47; SPILL-O2-NEXT: slli a1, a0, 348; SPILL-O2-NEXT: add a0, a1, a049; SPILL-O2-NEXT: add a0, sp, a050; SPILL-O2-NEXT: addi a0, a0, 1651; SPILL-O2-NEXT: vs4r.v v4, (a0) # vscale x 32-byte Folded Spill52; SPILL-O2-NEXT: csrr a0, vlenb53; SPILL-O2-NEXT: add a0, sp, a054; SPILL-O2-NEXT: addi a0, a0, 1655; SPILL-O2-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill56; SPILL-O2-NEXT: addi a0, sp, 1657; SPILL-O2-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill58; SPILL-O2-NEXT: #APP59; SPILL-O2-NEXT: #NO_APP60; SPILL-O2-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload61; SPILL-O2-NEXT: csrr a0, vlenb62; SPILL-O2-NEXT: slli a1, a0, 463; SPILL-O2-NEXT: sub a0, a1, a064; SPILL-O2-NEXT: add a0, sp, a065; SPILL-O2-NEXT: addi a0, a0, 1666; SPILL-O2-NEXT: vl1r.v v1, (a0) # vscale x 8-byte Folded Reload67; SPILL-O2-NEXT: csrr a0, vlenb68; SPILL-O2-NEXT: li a1, 1369; SPILL-O2-NEXT: mul a0, a0, a170; SPILL-O2-NEXT: add a0, sp, a071; SPILL-O2-NEXT: addi a0, a0, 1672; SPILL-O2-NEXT: vl2r.v v2, (a0) # vscale x 16-byte Folded Reload73; SPILL-O2-NEXT: csrr a0, vlenb74; SPILL-O2-NEXT: slli a1, a0, 375; SPILL-O2-NEXT: add a0, a1, a076; SPILL-O2-NEXT: add a0, sp, a077; SPILL-O2-NEXT: addi a0, a0, 1678; SPILL-O2-NEXT: vl4r.v v4, (a0) # vscale x 32-byte Folded Reload79; SPILL-O2-NEXT: csrr a0, vlenb80; SPILL-O2-NEXT: add a0, sp, a081; SPILL-O2-NEXT: addi a0, a0, 1682; SPILL-O2-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload83; SPILL-O2-NEXT: csrr a0, vlenb84; SPILL-O2-NEXT: slli a0, a0, 485; SPILL-O2-NEXT: add sp, sp, a086; SPILL-O2-NEXT: addi sp, sp, 1687; SPILL-O2-NEXT: ret88entry:89 call void asm sideeffect "",90 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()91 92 ret <vscale x 1 x i32> %va93}94 95define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee2(<vscale x 1 x i32> %va) nounwind {96; SPILL-O2-LABEL: test_vector_callee2:97; SPILL-O2: # %bb.0: # %entry98; SPILL-O2-NEXT: addi sp, sp, -1699; SPILL-O2-NEXT: csrr a0, vlenb100; SPILL-O2-NEXT: li a1, 12101; SPILL-O2-NEXT: mul a0, a0, a1102; SPILL-O2-NEXT: sub sp, sp, a0103; SPILL-O2-NEXT: csrr a0, vlenb104; SPILL-O2-NEXT: li a1, 11105; SPILL-O2-NEXT: mul a0, a0, a1106; SPILL-O2-NEXT: add a0, sp, a0107; SPILL-O2-NEXT: addi a0, a0, 16108; SPILL-O2-NEXT: vs1r.v v1, (a0) # vscale x 8-byte Folded Spill109; SPILL-O2-NEXT: csrr a0, vlenb110; SPILL-O2-NEXT: li a1, 10111; SPILL-O2-NEXT: mul a0, a0, a1112; SPILL-O2-NEXT: add a0, sp, a0113; SPILL-O2-NEXT: addi a0, a0, 16114; SPILL-O2-NEXT: vs1r.v v3, (a0) # vscale x 8-byte Folded Spill115; SPILL-O2-NEXT: csrr a0, vlenb116; SPILL-O2-NEXT: slli a1, a0, 3117; SPILL-O2-NEXT: add a0, a1, a0118; SPILL-O2-NEXT: add a0, sp, a0119; SPILL-O2-NEXT: addi a0, a0, 16120; SPILL-O2-NEXT: vs1r.v v5, (a0) # vscale x 8-byte Folded Spill121; SPILL-O2-NEXT: csrr a0, vlenb122; SPILL-O2-NEXT: slli a0, a0, 3123; SPILL-O2-NEXT: add a0, sp, a0124; SPILL-O2-NEXT: addi a0, a0, 16125; SPILL-O2-NEXT: vs1r.v v7, (a0) # vscale x 8-byte Folded Spill126; SPILL-O2-NEXT: addi a0, sp, 16127; SPILL-O2-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill128; SPILL-O2-NEXT: #APP129; SPILL-O2-NEXT: #NO_APP130; SPILL-O2-NEXT: csrr a0, vlenb131; SPILL-O2-NEXT: li a1, 11132; SPILL-O2-NEXT: mul a0, a0, a1133; SPILL-O2-NEXT: add a0, sp, a0134; SPILL-O2-NEXT: addi a0, a0, 16135; SPILL-O2-NEXT: vl1r.v v1, (a0) # vscale x 8-byte Folded Reload136; SPILL-O2-NEXT: csrr a0, vlenb137; SPILL-O2-NEXT: li a1, 10138; SPILL-O2-NEXT: mul a0, a0, a1139; SPILL-O2-NEXT: add a0, sp, a0140; SPILL-O2-NEXT: addi a0, a0, 16141; SPILL-O2-NEXT: vl1r.v v3, (a0) # vscale x 8-byte Folded Reload142; SPILL-O2-NEXT: csrr a0, vlenb143; SPILL-O2-NEXT: slli a1, a0, 3144; SPILL-O2-NEXT: add a0, a1, a0145; SPILL-O2-NEXT: add a0, sp, a0146; SPILL-O2-NEXT: addi a0, a0, 16147; SPILL-O2-NEXT: vl1r.v v5, (a0) # vscale x 8-byte Folded Reload148; SPILL-O2-NEXT: csrr a0, vlenb149; SPILL-O2-NEXT: slli a0, a0, 3150; SPILL-O2-NEXT: add a0, sp, a0151; SPILL-O2-NEXT: addi a0, a0, 16152; SPILL-O2-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload153; SPILL-O2-NEXT: addi a0, sp, 16154; SPILL-O2-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload155; SPILL-O2-NEXT: csrr a0, vlenb156; SPILL-O2-NEXT: li a1, 12157; SPILL-O2-NEXT: mul a0, a0, a1158; SPILL-O2-NEXT: add sp, sp, a0159; SPILL-O2-NEXT: addi sp, sp, 16160; SPILL-O2-NEXT: ret161entry:162 call void asm sideeffect "",163 "~{v1},~{v3},~{v5},~{v7},~{v24m2},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()164 165 ret <vscale x 1 x i32> %va166}167 168define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee3(<vscale x 1 x i32> %va) nounwind {169; SPILL-O2-LABEL: test_vector_callee3:170; SPILL-O2: # %bb.0: # %entry171; SPILL-O2-NEXT: addi sp, sp, -16172; SPILL-O2-NEXT: csrr a0, vlenb173; SPILL-O2-NEXT: li a1, 10174; SPILL-O2-NEXT: mul a0, a0, a1175; SPILL-O2-NEXT: sub sp, sp, a0176; SPILL-O2-NEXT: csrr a0, vlenb177; SPILL-O2-NEXT: slli a1, a0, 3178; SPILL-O2-NEXT: add a0, a1, a0179; SPILL-O2-NEXT: add a0, sp, a0180; SPILL-O2-NEXT: addi a0, a0, 16181; SPILL-O2-NEXT: vs1r.v v1, (a0) # vscale x 8-byte Folded Spill182; SPILL-O2-NEXT: csrr a0, vlenb183; SPILL-O2-NEXT: slli a0, a0, 3184; SPILL-O2-NEXT: add a0, sp, a0185; SPILL-O2-NEXT: addi a0, a0, 16186; SPILL-O2-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill187; SPILL-O2-NEXT: csrr a0, vlenb188; SPILL-O2-NEXT: li a1, 6189; SPILL-O2-NEXT: mul a0, a0, a1190; SPILL-O2-NEXT: add a0, sp, a0191; SPILL-O2-NEXT: addi a0, a0, 16192; SPILL-O2-NEXT: vs2r.v v2, (a0) # vscale x 16-byte Folded Spill193; SPILL-O2-NEXT: csrr a0, vlenb194; SPILL-O2-NEXT: slli a0, a0, 2195; SPILL-O2-NEXT: add a0, sp, a0196; SPILL-O2-NEXT: addi a0, a0, 16197; SPILL-O2-NEXT: vs2r.v v26, (a0) # vscale x 16-byte Folded Spill198; SPILL-O2-NEXT: addi a0, sp, 16199; SPILL-O2-NEXT: vs4r.v v28, (a0) # vscale x 32-byte Folded Spill200; SPILL-O2-NEXT: #APP201; SPILL-O2-NEXT: #NO_APP202; SPILL-O2-NEXT: csrr a0, vlenb203; SPILL-O2-NEXT: slli a1, a0, 3204; SPILL-O2-NEXT: add a0, a1, a0205; SPILL-O2-NEXT: add a0, sp, a0206; SPILL-O2-NEXT: addi a0, a0, 16207; SPILL-O2-NEXT: vl1r.v v1, (a0) # vscale x 8-byte Folded Reload208; SPILL-O2-NEXT: csrr a0, vlenb209; SPILL-O2-NEXT: slli a0, a0, 3210; SPILL-O2-NEXT: add a0, sp, a0211; SPILL-O2-NEXT: addi a0, a0, 16212; SPILL-O2-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload213; SPILL-O2-NEXT: csrr a0, vlenb214; SPILL-O2-NEXT: li a1, 6215; SPILL-O2-NEXT: mul a0, a0, a1216; SPILL-O2-NEXT: add a0, sp, a0217; SPILL-O2-NEXT: addi a0, a0, 16218; SPILL-O2-NEXT: vl2r.v v2, (a0) # vscale x 16-byte Folded Reload219; SPILL-O2-NEXT: csrr a0, vlenb220; SPILL-O2-NEXT: slli a0, a0, 2221; SPILL-O2-NEXT: add a0, sp, a0222; SPILL-O2-NEXT: addi a0, a0, 16223; SPILL-O2-NEXT: vl2r.v v26, (a0) # vscale x 16-byte Folded Reload224; SPILL-O2-NEXT: addi a0, sp, 16225; SPILL-O2-NEXT: vl4r.v v28, (a0) # vscale x 32-byte Folded Reload226; SPILL-O2-NEXT: csrr a0, vlenb227; SPILL-O2-NEXT: li a1, 10228; SPILL-O2-NEXT: mul a0, a0, a1229; SPILL-O2-NEXT: add sp, sp, a0230; SPILL-O2-NEXT: addi sp, sp, 16231; SPILL-O2-NEXT: ret232entry:233 call void asm sideeffect "",234 "~{v1},~{v2},~{v3},~{v24},~{v26m2},~{v28m2},~{v29},~{v30},~{v31}"()235 236 ret <vscale x 1 x i32> %va237}238 239; Make sure the local stack allocation pass doesn't count vector registers. The240; sizes are chosen to be on the edge of what RISCVRegister::needsFrameBaseReg241; considers to need a virtual base register.242define riscv_vector_cc void @local_stack_allocation_frame_pointer() "frame-pointer"="all" {243; SPILL-O2-LABEL: local_stack_allocation_frame_pointer:244; SPILL-O2: # %bb.0:245; SPILL-O2-NEXT: addi sp, sp, -2032246; SPILL-O2-NEXT: .cfi_def_cfa_offset 2032247; SPILL-O2-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill248; SPILL-O2-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill249; SPILL-O2-NEXT: .cfi_offset ra, -4250; SPILL-O2-NEXT: .cfi_offset s0, -8251; SPILL-O2-NEXT: addi s0, sp, 2032252; SPILL-O2-NEXT: .cfi_def_cfa s0, 0253; SPILL-O2-NEXT: addi sp, sp, -480254; SPILL-O2-NEXT: lbu a0, -1912(s0)255; SPILL-O2-NEXT: sb a0, -1912(s0)256; SPILL-O2-NEXT: addi sp, s0, -2032257; SPILL-O2-NEXT: .cfi_def_cfa sp, 2032258; SPILL-O2-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload259; SPILL-O2-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload260; SPILL-O2-NEXT: .cfi_restore ra261; SPILL-O2-NEXT: .cfi_restore s0262; SPILL-O2-NEXT: addi sp, sp, 2032263; SPILL-O2-NEXT: .cfi_def_cfa_offset 0264; SPILL-O2-NEXT: ret265 %va = alloca [2500 x i8], align 4266 %va_gep = getelementptr [2000 x i8], ptr %va, i64 0, i64 600267 %load = load volatile i8, ptr %va_gep, align 4268 store volatile i8 %load, ptr %va_gep, align 4269 ret void270}271