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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define fastcc <vscale x 4 x i8> @ret_nxv4i8(ptr %p) {8; CHECK-LABEL: ret_nxv4i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma11; CHECK-NEXT: vle8.v v8, (a0)12; CHECK-NEXT: ret13 %v = load <vscale x 4 x i8>, ptr %p14 ret <vscale x 4 x i8> %v15}16 17define fastcc <vscale x 4 x i32> @ret_nxv4i32(ptr %p) {18; CHECK-LABEL: ret_nxv4i32:19; CHECK: # %bb.0:20; CHECK-NEXT: vl2re32.v v8, (a0)21; CHECK-NEXT: ret22 %v = load <vscale x 4 x i32>, ptr %p23 ret <vscale x 4 x i32> %v24}25 26define fastcc <vscale x 8 x i32> @ret_nxv8i32(ptr %p) {27; CHECK-LABEL: ret_nxv8i32:28; CHECK: # %bb.0:29; CHECK-NEXT: vl4re32.v v8, (a0)30; CHECK-NEXT: ret31 %v = load <vscale x 8 x i32>, ptr %p32 ret <vscale x 8 x i32> %v33}34 35define fastcc <vscale x 16 x i64> @ret_nxv16i64(ptr %p) {36; CHECK-LABEL: ret_nxv16i64:37; CHECK: # %bb.0:38; CHECK-NEXT: csrr a1, vlenb39; CHECK-NEXT: slli a1, a1, 340; CHECK-NEXT: add a1, a0, a141; CHECK-NEXT: vl8re64.v v16, (a1)42; CHECK-NEXT: vl8re64.v v8, (a0)43; CHECK-NEXT: ret44 %v = load <vscale x 16 x i64>, ptr %p45 ret <vscale x 16 x i64> %v46}47 48define fastcc <vscale x 8 x i1> @ret_mask_nxv8i1(ptr %p) {49; CHECK-LABEL: ret_mask_nxv8i1:50; CHECK: # %bb.0:51; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma52; CHECK-NEXT: vlm.v v0, (a0)53; CHECK-NEXT: ret54 %v = load <vscale x 8 x i1>, ptr %p55 ret <vscale x 8 x i1> %v56}57 58define fastcc <vscale x 32 x i1> @ret_mask_nxv32i1(ptr %p) {59; CHECK-LABEL: ret_mask_nxv32i1:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma62; CHECK-NEXT: vlm.v v0, (a0)63; CHECK-NEXT: ret64 %v = load <vscale x 32 x i1>, ptr %p65 ret <vscale x 32 x i1> %v66}67 68; Return the vector via registers v8-v2369define fastcc <vscale x 64 x i32> @ret_split_nxv64i32(ptr %x) {70; CHECK-LABEL: ret_split_nxv64i32:71; CHECK: # %bb.0:72; CHECK-NEXT: csrr a2, vlenb73; CHECK-NEXT: vl8re32.v v8, (a1)74; CHECK-NEXT: slli a3, a2, 375; CHECK-NEXT: slli a2, a2, 476; CHECK-NEXT: add a4, a2, a377; CHECK-NEXT: add a5, a1, a278; CHECK-NEXT: vl8re32.v v16, (a5)79; CHECK-NEXT: add a5, a1, a380; CHECK-NEXT: add a2, a0, a281; CHECK-NEXT: add a3, a0, a382; CHECK-NEXT: add a1, a1, a483; CHECK-NEXT: vl8re32.v v24, (a5)84; CHECK-NEXT: vl8re32.v v0, (a1)85; CHECK-NEXT: vs8r.v v8, (a0)86; CHECK-NEXT: vs8r.v v16, (a2)87; CHECK-NEXT: vs8r.v v24, (a3)88; CHECK-NEXT: add a0, a0, a489; CHECK-NEXT: vs8r.v v0, (a0)90; CHECK-NEXT: ret91 %v = load <vscale x 64 x i32>, ptr %x92 ret <vscale x 64 x i32> %v93}94 95; Return the vector fully via the stack96define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(ptr %x) {97; CHECK-LABEL: ret_split_nxv128i32:98; CHECK: # %bb.0:99; CHECK-NEXT: addi sp, sp, -16100; CHECK-NEXT: .cfi_def_cfa_offset 16101; CHECK-NEXT: csrr a2, vlenb102; CHECK-NEXT: li a3, 40103; CHECK-NEXT: mul a2, a2, a3104; CHECK-NEXT: sub sp, sp, a2105; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb106; CHECK-NEXT: csrr a2, vlenb107; CHECK-NEXT: vl8re32.v v8, (a1)108; CHECK-NEXT: csrr a3, vlenb109; CHECK-NEXT: slli a3, a3, 5110; CHECK-NEXT: add a3, sp, a3111; CHECK-NEXT: addi a3, a3, 16112; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill113; CHECK-NEXT: slli a3, a2, 3114; CHECK-NEXT: slli a4, a2, 4115; CHECK-NEXT: slli a5, a2, 5116; CHECK-NEXT: slli a2, a2, 6117; CHECK-NEXT: add a6, a4, a3118; CHECK-NEXT: add a7, a5, a3119; CHECK-NEXT: add t0, a5, a4120; CHECK-NEXT: sub a2, a2, a3121; CHECK-NEXT: add t1, a1, a3122; CHECK-NEXT: add t2, a1, a4123; CHECK-NEXT: add t3, a1, a5124; CHECK-NEXT: vl8re32.v v8, (t1)125; CHECK-NEXT: csrr t1, vlenb126; CHECK-NEXT: slli t1, t1, 4127; CHECK-NEXT: add t1, sp, t1128; CHECK-NEXT: addi t1, t1, 16129; CHECK-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill130; CHECK-NEXT: add t1, a1, a6131; CHECK-NEXT: vl8re32.v v8, (t2)132; CHECK-NEXT: addi t2, sp, 16133; CHECK-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill134; CHECK-NEXT: add t2, a1, a7135; CHECK-NEXT: vl8re32.v v16, (t3)136; CHECK-NEXT: add t3, a1, t0137; CHECK-NEXT: add a1, a1, a2138; CHECK-NEXT: vl8re32.v v8, (t1)139; CHECK-NEXT: csrr t1, vlenb140; CHECK-NEXT: li t4, 24141; CHECK-NEXT: mul t1, t1, t4142; CHECK-NEXT: add t1, sp, t1143; CHECK-NEXT: addi t1, t1, 16144; CHECK-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill145; CHECK-NEXT: vl8re32.v v8, (t2)146; CHECK-NEXT: csrr t1, vlenb147; CHECK-NEXT: slli t1, t1, 3148; CHECK-NEXT: add t1, sp, t1149; CHECK-NEXT: addi t1, t1, 16150; CHECK-NEXT: vs8r.v v8, (t1) # vscale x 64-byte Folded Spill151; CHECK-NEXT: vl8re32.v v24, (t3)152; CHECK-NEXT: vl8re32.v v8, (a1)153; CHECK-NEXT: csrr a1, vlenb154; CHECK-NEXT: slli a1, a1, 5155; CHECK-NEXT: add a1, sp, a1156; CHECK-NEXT: addi a1, a1, 16157; CHECK-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload158; CHECK-NEXT: vs8r.v v0, (a0)159; CHECK-NEXT: add a5, a0, a5160; CHECK-NEXT: vs8r.v v16, (a5)161; CHECK-NEXT: add a4, a0, a4162; CHECK-NEXT: addi a1, sp, 16163; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload164; CHECK-NEXT: vs8r.v v16, (a4)165; CHECK-NEXT: add a3, a0, a3166; CHECK-NEXT: csrr a1, vlenb167; CHECK-NEXT: slli a1, a1, 4168; CHECK-NEXT: add a1, sp, a1169; CHECK-NEXT: addi a1, a1, 16170; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload171; CHECK-NEXT: vs8r.v v16, (a3)172; CHECK-NEXT: add a2, a0, a2173; CHECK-NEXT: vs8r.v v8, (a2)174; CHECK-NEXT: add t0, a0, t0175; CHECK-NEXT: vs8r.v v24, (t0)176; CHECK-NEXT: add a7, a0, a7177; CHECK-NEXT: csrr a1, vlenb178; CHECK-NEXT: slli a1, a1, 3179; CHECK-NEXT: add a1, sp, a1180; CHECK-NEXT: addi a1, a1, 16181; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload182; CHECK-NEXT: vs8r.v v8, (a7)183; CHECK-NEXT: add a0, a0, a6184; CHECK-NEXT: csrr a1, vlenb185; CHECK-NEXT: li a2, 24186; CHECK-NEXT: mul a1, a1, a2187; CHECK-NEXT: add a1, sp, a1188; CHECK-NEXT: addi a1, a1, 16189; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload190; CHECK-NEXT: vs8r.v v8, (a0)191; CHECK-NEXT: csrr a0, vlenb192; CHECK-NEXT: li a1, 40193; CHECK-NEXT: mul a0, a0, a1194; CHECK-NEXT: add sp, sp, a0195; CHECK-NEXT: .cfi_def_cfa sp, 16196; CHECK-NEXT: addi sp, sp, 16197; CHECK-NEXT: .cfi_def_cfa_offset 0198; CHECK-NEXT: ret199 %v = load <vscale x 128 x i32>, ptr %x200 ret <vscale x 128 x i32> %v201}202 203define fastcc <vscale x 4 x i8> @ret_nxv4i8_param_nxv4i8_nxv4i8(<vscale x 4 x i8> %v, <vscale x 4 x i8> %w) {204; CHECK-LABEL: ret_nxv4i8_param_nxv4i8_nxv4i8:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma207; CHECK-NEXT: vadd.vv v8, v8, v9208; CHECK-NEXT: ret209 %r = add <vscale x 4 x i8> %v, %w210 ret <vscale x 4 x i8> %r211}212 213define fastcc <vscale x 4 x i64> @ret_nxv4i64_param_nxv4i64_nxv4i64(<vscale x 4 x i64> %v, <vscale x 4 x i64> %w) {214; CHECK-LABEL: ret_nxv4i64_param_nxv4i64_nxv4i64:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma217; CHECK-NEXT: vadd.vv v8, v8, v12218; CHECK-NEXT: ret219 %r = add <vscale x 4 x i64> %v, %w220 ret <vscale x 4 x i64> %r221}222 223define fastcc <vscale x 8 x i1> @ret_nxv8i1_param_nxv8i1_nxv8i1(<vscale x 8 x i1> %v, <vscale x 8 x i1> %w) {224; CHECK-LABEL: ret_nxv8i1_param_nxv8i1_nxv8i1:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma227; CHECK-NEXT: vmxor.mm v0, v0, v8228; CHECK-NEXT: ret229 %r = xor <vscale x 8 x i1> %v, %w230 ret <vscale x 8 x i1> %r231}232 233define fastcc <vscale x 32 x i1> @ret_nxv32i1_param_nxv32i1_nxv32i1(<vscale x 32 x i1> %v, <vscale x 32 x i1> %w) {234; CHECK-LABEL: ret_nxv32i1_param_nxv32i1_nxv32i1:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma237; CHECK-NEXT: vmand.mm v0, v0, v8238; CHECK-NEXT: ret239 %r = and <vscale x 32 x i1> %v, %w240 ret <vscale x 32 x i1> %r241}242 243define fastcc <vscale x 32 x i32> @ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %w) {244; CHECK-LABEL: ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32:245; CHECK: # %bb.0:246; CHECK-NEXT: addi sp, sp, -16247; CHECK-NEXT: .cfi_def_cfa_offset 16248; CHECK-NEXT: csrr a1, vlenb249; CHECK-NEXT: li a3, 24250; CHECK-NEXT: mul a1, a1, a3251; CHECK-NEXT: sub sp, sp, a1252; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb253; CHECK-NEXT: csrr a1, vlenb254; CHECK-NEXT: slli a1, a1, 4255; CHECK-NEXT: add a1, sp, a1256; CHECK-NEXT: addi a1, a1, 16257; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill258; CHECK-NEXT: csrr a1, vlenb259; CHECK-NEXT: slli a1, a1, 3260; CHECK-NEXT: add a1, sp, a1261; CHECK-NEXT: addi a1, a1, 16262; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill263; CHECK-NEXT: csrr a1, vlenb264; CHECK-NEXT: vl8re32.v v8, (a2)265; CHECK-NEXT: addi a3, sp, 16266; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill267; CHECK-NEXT: vl8re32.v v0, (a0)268; CHECK-NEXT: slli a1, a1, 3269; CHECK-NEXT: add a2, a2, a1270; CHECK-NEXT: add a0, a0, a1271; CHECK-NEXT: vl8re32.v v8, (a0)272; CHECK-NEXT: vl8re32.v v16, (a2)273; CHECK-NEXT: csrr a0, vlenb274; CHECK-NEXT: slli a0, a0, 3275; CHECK-NEXT: add a0, sp, a0276; CHECK-NEXT: addi a0, a0, 16277; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload278; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma279; CHECK-NEXT: vadd.vv v0, v24, v0280; CHECK-NEXT: addi a0, sp, 16281; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload282; CHECK-NEXT: vadd.vv v24, v0, v24283; CHECK-NEXT: csrr a0, vlenb284; CHECK-NEXT: slli a0, a0, 4285; CHECK-NEXT: add a0, sp, a0286; CHECK-NEXT: addi a0, a0, 16287; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload288; CHECK-NEXT: vadd.vv v8, v0, v8289; CHECK-NEXT: vadd.vv v8, v8, v16290; CHECK-NEXT: vadd.vx v16, v8, a4291; CHECK-NEXT: vadd.vx v8, v24, a4292; CHECK-NEXT: csrr a0, vlenb293; CHECK-NEXT: li a1, 24294; CHECK-NEXT: mul a0, a0, a1295; CHECK-NEXT: add sp, sp, a0296; CHECK-NEXT: .cfi_def_cfa sp, 16297; CHECK-NEXT: addi sp, sp, 16298; CHECK-NEXT: .cfi_def_cfa_offset 0299; CHECK-NEXT: ret300 %r = add <vscale x 32 x i32> %x, %y301 %s = add <vscale x 32 x i32> %r, %z302 %head = insertelement <vscale x 32 x i32> poison, i32 %w, i32 0303 %splat = shufflevector <vscale x 32 x i32> %head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer304 %t = add <vscale x 32 x i32> %s, %splat305 ret <vscale x 32 x i32> %t306}307 308declare <vscale x 32 x i32> @ext2(<vscale x 32 x i32>, <vscale x 32 x i32>, i32, i32)309declare <vscale x 32 x i32> @ext3(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i32>, i32, i32)310 311define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, i32 %w) {312; RV32-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_i32:313; RV32: # %bb.0:314; RV32-NEXT: addi sp, sp, -144315; RV32-NEXT: .cfi_def_cfa_offset 144316; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill317; RV32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill318; RV32-NEXT: .cfi_offset ra, -4319; RV32-NEXT: .cfi_offset s0, -8320; RV32-NEXT: addi s0, sp, 144321; RV32-NEXT: .cfi_def_cfa s0, 0322; RV32-NEXT: csrr a1, vlenb323; RV32-NEXT: slli a1, a1, 4324; RV32-NEXT: sub sp, sp, a1325; RV32-NEXT: andi sp, sp, -128326; RV32-NEXT: csrr a1, vlenb327; RV32-NEXT: slli a1, a1, 3328; RV32-NEXT: add a3, a0, a1329; RV32-NEXT: vl8re32.v v24, (a3)330; RV32-NEXT: vl8re32.v v0, (a0)331; RV32-NEXT: addi a3, sp, 128332; RV32-NEXT: addi a0, sp, 128333; RV32-NEXT: vs8r.v v8, (a3)334; RV32-NEXT: add a1, a3, a1335; RV32-NEXT: li a3, 2336; RV32-NEXT: vs8r.v v16, (a1)337; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma338; RV32-NEXT: vmv8r.v v8, v0339; RV32-NEXT: vmv8r.v v16, v24340; RV32-NEXT: call ext2341; RV32-NEXT: addi sp, s0, -144342; RV32-NEXT: .cfi_def_cfa sp, 144343; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload344; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload345; RV32-NEXT: .cfi_restore ra346; RV32-NEXT: .cfi_restore s0347; RV32-NEXT: addi sp, sp, 144348; RV32-NEXT: .cfi_def_cfa_offset 0349; RV32-NEXT: ret350;351; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_i32:352; RV64: # %bb.0:353; RV64-NEXT: addi sp, sp, -144354; RV64-NEXT: .cfi_def_cfa_offset 144355; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill356; RV64-NEXT: sd s0, 128(sp) # 8-byte Folded Spill357; RV64-NEXT: .cfi_offset ra, -8358; RV64-NEXT: .cfi_offset s0, -16359; RV64-NEXT: addi s0, sp, 144360; RV64-NEXT: .cfi_def_cfa s0, 0361; RV64-NEXT: csrr a1, vlenb362; RV64-NEXT: slli a1, a1, 4363; RV64-NEXT: sub sp, sp, a1364; RV64-NEXT: andi sp, sp, -128365; RV64-NEXT: csrr a1, vlenb366; RV64-NEXT: slli a1, a1, 3367; RV64-NEXT: add a3, a0, a1368; RV64-NEXT: vl8re32.v v24, (a3)369; RV64-NEXT: vl8re32.v v0, (a0)370; RV64-NEXT: addi a3, sp, 128371; RV64-NEXT: addi a0, sp, 128372; RV64-NEXT: vs8r.v v8, (a3)373; RV64-NEXT: add a1, a3, a1374; RV64-NEXT: li a3, 2375; RV64-NEXT: vs8r.v v16, (a1)376; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma377; RV64-NEXT: vmv8r.v v8, v0378; RV64-NEXT: vmv8r.v v16, v24379; RV64-NEXT: call ext2380; RV64-NEXT: addi sp, s0, -144381; RV64-NEXT: .cfi_def_cfa sp, 144382; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload383; RV64-NEXT: ld s0, 128(sp) # 8-byte Folded Reload384; RV64-NEXT: .cfi_restore ra385; RV64-NEXT: .cfi_restore s0386; RV64-NEXT: addi sp, sp, 144387; RV64-NEXT: .cfi_def_cfa_offset 0388; RV64-NEXT: ret389 %t = call fastcc <vscale x 32 x i32> @ext2(<vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 2)390 ret <vscale x 32 x i32> %t391}392 393define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %w) {394; RV32-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32:395; RV32: # %bb.0:396; RV32-NEXT: addi sp, sp, -144397; RV32-NEXT: .cfi_def_cfa_offset 144398; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill399; RV32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill400; RV32-NEXT: .cfi_offset ra, -4401; RV32-NEXT: .cfi_offset s0, -8402; RV32-NEXT: addi s0, sp, 144403; RV32-NEXT: .cfi_def_cfa s0, 0404; RV32-NEXT: csrr a1, vlenb405; RV32-NEXT: li a3, 48406; RV32-NEXT: mul a1, a1, a3407; RV32-NEXT: sub sp, sp, a1408; RV32-NEXT: andi sp, sp, -128409; RV32-NEXT: addi a1, sp, 128410; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill411; RV32-NEXT: csrr a1, vlenb412; RV32-NEXT: vl8re32.v v16, (a2)413; RV32-NEXT: csrr a3, vlenb414; RV32-NEXT: slli a3, a3, 3415; RV32-NEXT: add a3, sp, a3416; RV32-NEXT: addi a3, a3, 128417; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill418; RV32-NEXT: slli a1, a1, 3419; RV32-NEXT: add a2, a2, a1420; RV32-NEXT: add a3, a0, a1421; RV32-NEXT: vl8re32.v v0, (a2)422; RV32-NEXT: vl8re32.v v24, (a3)423; RV32-NEXT: vl8re32.v v16, (a0)424; RV32-NEXT: csrr a0, vlenb425; RV32-NEXT: slli a0, a0, 4426; RV32-NEXT: add a0, sp, a0427; RV32-NEXT: addi a0, a0, 128428; RV32-NEXT: vs8r.v v8, (a0)429; RV32-NEXT: csrr a3, vlenb430; RV32-NEXT: slli a3, a3, 5431; RV32-NEXT: add a3, sp, a3432; RV32-NEXT: addi a3, a3, 128433; RV32-NEXT: vs8r.v v16, (a3)434; RV32-NEXT: add a0, a0, a1435; RV32-NEXT: addi a2, sp, 128436; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload437; RV32-NEXT: vs8r.v v8, (a0)438; RV32-NEXT: csrr a0, vlenb439; RV32-NEXT: slli a0, a0, 5440; RV32-NEXT: add a0, sp, a0441; RV32-NEXT: addi a0, a0, 128442; RV32-NEXT: csrr a2, vlenb443; RV32-NEXT: slli a2, a2, 4444; RV32-NEXT: add a2, sp, a2445; RV32-NEXT: addi a2, a2, 128446; RV32-NEXT: add a1, a3, a1447; RV32-NEXT: li a5, 42448; RV32-NEXT: vs8r.v v24, (a1)449; RV32-NEXT: csrr a1, vlenb450; RV32-NEXT: slli a1, a1, 3451; RV32-NEXT: add a1, sp, a1452; RV32-NEXT: addi a1, a1, 128453; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload454; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma455; RV32-NEXT: vmv8r.v v16, v0456; RV32-NEXT: call ext3457; RV32-NEXT: addi sp, s0, -144458; RV32-NEXT: .cfi_def_cfa sp, 144459; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload460; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload461; RV32-NEXT: .cfi_restore ra462; RV32-NEXT: .cfi_restore s0463; RV32-NEXT: addi sp, sp, 144464; RV32-NEXT: .cfi_def_cfa_offset 0465; RV32-NEXT: ret466;467; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32:468; RV64: # %bb.0:469; RV64-NEXT: addi sp, sp, -144470; RV64-NEXT: .cfi_def_cfa_offset 144471; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill472; RV64-NEXT: sd s0, 128(sp) # 8-byte Folded Spill473; RV64-NEXT: .cfi_offset ra, -8474; RV64-NEXT: .cfi_offset s0, -16475; RV64-NEXT: addi s0, sp, 144476; RV64-NEXT: .cfi_def_cfa s0, 0477; RV64-NEXT: csrr a1, vlenb478; RV64-NEXT: li a3, 48479; RV64-NEXT: mul a1, a1, a3480; RV64-NEXT: sub sp, sp, a1481; RV64-NEXT: andi sp, sp, -128482; RV64-NEXT: addi a1, sp, 128483; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill484; RV64-NEXT: csrr a1, vlenb485; RV64-NEXT: vl8re32.v v16, (a2)486; RV64-NEXT: csrr a3, vlenb487; RV64-NEXT: slli a3, a3, 3488; RV64-NEXT: add a3, sp, a3489; RV64-NEXT: addi a3, a3, 128490; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill491; RV64-NEXT: slli a1, a1, 3492; RV64-NEXT: add a2, a2, a1493; RV64-NEXT: add a3, a0, a1494; RV64-NEXT: vl8re32.v v0, (a2)495; RV64-NEXT: vl8re32.v v24, (a3)496; RV64-NEXT: vl8re32.v v16, (a0)497; RV64-NEXT: csrr a0, vlenb498; RV64-NEXT: slli a0, a0, 4499; RV64-NEXT: add a0, sp, a0500; RV64-NEXT: addi a0, a0, 128501; RV64-NEXT: vs8r.v v8, (a0)502; RV64-NEXT: csrr a3, vlenb503; RV64-NEXT: slli a3, a3, 5504; RV64-NEXT: add a3, sp, a3505; RV64-NEXT: addi a3, a3, 128506; RV64-NEXT: vs8r.v v16, (a3)507; RV64-NEXT: add a0, a0, a1508; RV64-NEXT: addi a2, sp, 128509; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload510; RV64-NEXT: vs8r.v v8, (a0)511; RV64-NEXT: csrr a0, vlenb512; RV64-NEXT: slli a0, a0, 5513; RV64-NEXT: add a0, sp, a0514; RV64-NEXT: addi a0, a0, 128515; RV64-NEXT: csrr a2, vlenb516; RV64-NEXT: slli a2, a2, 4517; RV64-NEXT: add a2, sp, a2518; RV64-NEXT: addi a2, a2, 128519; RV64-NEXT: add a1, a3, a1520; RV64-NEXT: li a5, 42521; RV64-NEXT: vs8r.v v24, (a1)522; RV64-NEXT: csrr a1, vlenb523; RV64-NEXT: slli a1, a1, 3524; RV64-NEXT: add a1, sp, a1525; RV64-NEXT: addi a1, a1, 128526; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload527; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma528; RV64-NEXT: vmv8r.v v16, v0529; RV64-NEXT: call ext3530; RV64-NEXT: addi sp, s0, -144531; RV64-NEXT: .cfi_def_cfa sp, 144532; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload533; RV64-NEXT: ld s0, 128(sp) # 8-byte Folded Reload534; RV64-NEXT: .cfi_restore ra535; RV64-NEXT: .cfi_restore s0536; RV64-NEXT: addi sp, sp, 144537; RV64-NEXT: .cfi_def_cfa_offset 0538; RV64-NEXT: ret539 %t = call fastcc <vscale x 32 x i32> @ext3(<vscale x 32 x i32> %z, <vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 42)540 ret <vscale x 32 x i32> %t541}542 543; A test case where the normal calling convention would pass directly via the544; stack, but with fastcc can pass indirectly with the extra GPR registers545; allowed.546define fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %8) {547; CHECK-LABEL: vector_arg_indirect_stack:548; CHECK: # %bb.0:549; CHECK-NEXT: csrr a0, vlenb550; CHECK-NEXT: slli a0, a0, 3551; CHECK-NEXT: add a0, t5, a0552; CHECK-NEXT: vl8re32.v v24, (t5)553; CHECK-NEXT: vl8re32.v v0, (a0)554; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma555; CHECK-NEXT: vadd.vv v8, v8, v24556; CHECK-NEXT: vadd.vv v16, v16, v0557; CHECK-NEXT: ret558 %s = add <vscale x 32 x i32> %x, %z559 ret <vscale x 32 x i32> %s560}561 562; Calling the function above. Ensure we pass the arguments correctly.563define fastcc <vscale x 32 x i32> @pass_vector_arg_indirect_stack(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z) {564; RV32-LABEL: pass_vector_arg_indirect_stack:565; RV32: # %bb.0:566; RV32-NEXT: addi sp, sp, -144567; RV32-NEXT: .cfi_def_cfa_offset 144568; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill569; RV32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill570; RV32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill571; RV32-NEXT: .cfi_offset ra, -4572; RV32-NEXT: .cfi_offset s0, -8573; RV32-NEXT: .cfi_offset s1, -12574; RV32-NEXT: addi s0, sp, 144575; RV32-NEXT: .cfi_def_cfa s0, 0576; RV32-NEXT: csrr a0, vlenb577; RV32-NEXT: slli a0, a0, 5578; RV32-NEXT: sub sp, sp, a0579; RV32-NEXT: andi sp, sp, -128580; RV32-NEXT: mv s1, sp581; RV32-NEXT: csrr a0, vlenb582; RV32-NEXT: slli a0, a0, 3583; RV32-NEXT: addi sp, sp, -16584; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma585; RV32-NEXT: vmv.v.i v8, 0586; RV32-NEXT: addi t0, s1, 128587; RV32-NEXT: csrr t1, vlenb588; RV32-NEXT: slli t1, t1, 4589; RV32-NEXT: add t1, s1, t1590; RV32-NEXT: addi t1, t1, 128591; RV32-NEXT: li a7, 8592; RV32-NEXT: li a1, 1593; RV32-NEXT: li a2, 2594; RV32-NEXT: li a3, 3595; RV32-NEXT: li a4, 4596; RV32-NEXT: li a5, 5597; RV32-NEXT: li a6, 6598; RV32-NEXT: vs8r.v v8, (t0)599; RV32-NEXT: vs8r.v v8, (t1)600; RV32-NEXT: sw a7, 0(sp)601; RV32-NEXT: li a7, 7602; RV32-NEXT: add t0, t0, a0603; RV32-NEXT: add a0, t1, a0604; RV32-NEXT: csrr t3, vlenb605; RV32-NEXT: slli t3, t3, 4606; RV32-NEXT: add t3, s1, t3607; RV32-NEXT: addi t3, t3, 128608; RV32-NEXT: vs8r.v v8, (t0)609; RV32-NEXT: addi t5, s1, 128610; RV32-NEXT: vs8r.v v8, (a0)611; RV32-NEXT: li a0, 0612; RV32-NEXT: vmv.v.i v16, 0613; RV32-NEXT: call vector_arg_indirect_stack614; RV32-NEXT: addi sp, sp, 16615; RV32-NEXT: addi sp, s0, -144616; RV32-NEXT: .cfi_def_cfa sp, 144617; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload618; RV32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload619; RV32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload620; RV32-NEXT: .cfi_restore ra621; RV32-NEXT: .cfi_restore s0622; RV32-NEXT: .cfi_restore s1623; RV32-NEXT: addi sp, sp, 144624; RV32-NEXT: .cfi_def_cfa_offset 0625; RV32-NEXT: ret626;627; RV64-LABEL: pass_vector_arg_indirect_stack:628; RV64: # %bb.0:629; RV64-NEXT: addi sp, sp, -160630; RV64-NEXT: .cfi_def_cfa_offset 160631; RV64-NEXT: sd ra, 152(sp) # 8-byte Folded Spill632; RV64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill633; RV64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill634; RV64-NEXT: .cfi_offset ra, -8635; RV64-NEXT: .cfi_offset s0, -16636; RV64-NEXT: .cfi_offset s1, -24637; RV64-NEXT: addi s0, sp, 160638; RV64-NEXT: .cfi_def_cfa s0, 0639; RV64-NEXT: csrr a0, vlenb640; RV64-NEXT: slli a0, a0, 5641; RV64-NEXT: sub sp, sp, a0642; RV64-NEXT: andi sp, sp, -128643; RV64-NEXT: mv s1, sp644; RV64-NEXT: csrr a0, vlenb645; RV64-NEXT: slli a0, a0, 3646; RV64-NEXT: addi sp, sp, -16647; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma648; RV64-NEXT: vmv.v.i v8, 0649; RV64-NEXT: addi t0, s1, 128650; RV64-NEXT: csrr t1, vlenb651; RV64-NEXT: slli t1, t1, 4652; RV64-NEXT: add t1, s1, t1653; RV64-NEXT: addi t1, t1, 128654; RV64-NEXT: li a7, 8655; RV64-NEXT: li a1, 1656; RV64-NEXT: li a2, 2657; RV64-NEXT: li a3, 3658; RV64-NEXT: li a4, 4659; RV64-NEXT: li a5, 5660; RV64-NEXT: li a6, 6661; RV64-NEXT: vs8r.v v8, (t0)662; RV64-NEXT: vs8r.v v8, (t1)663; RV64-NEXT: sd a7, 0(sp)664; RV64-NEXT: li a7, 7665; RV64-NEXT: add t0, t0, a0666; RV64-NEXT: add a0, t1, a0667; RV64-NEXT: csrr t3, vlenb668; RV64-NEXT: slli t3, t3, 4669; RV64-NEXT: add t3, s1, t3670; RV64-NEXT: addi t3, t3, 128671; RV64-NEXT: vs8r.v v8, (t0)672; RV64-NEXT: addi t5, s1, 128673; RV64-NEXT: vs8r.v v8, (a0)674; RV64-NEXT: li a0, 0675; RV64-NEXT: vmv.v.i v16, 0676; RV64-NEXT: call vector_arg_indirect_stack677; RV64-NEXT: addi sp, sp, 16678; RV64-NEXT: addi sp, s0, -160679; RV64-NEXT: .cfi_def_cfa sp, 160680; RV64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload681; RV64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload682; RV64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload683; RV64-NEXT: .cfi_restore ra684; RV64-NEXT: .cfi_restore s0685; RV64-NEXT: .cfi_restore s1686; RV64-NEXT: addi sp, sp, 160687; RV64-NEXT: .cfi_def_cfa_offset 0688; RV64-NEXT: ret689 %s = call fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, i32 8)690 ret <vscale x 32 x i32> %s691}692 693; Test case where we are out of registers for the vector and all GPRs are used.694define fastcc <vscale x 16 x i32> @vector_arg_indirect_stack_no_gpr(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, <vscale x 16 x i32> %x, <vscale x 16 x i32> %y, <vscale x 16 x i32> %z) {695; RV32-LABEL: vector_arg_indirect_stack_no_gpr:696; RV32: # %bb.0:697; RV32-NEXT: lw a0, 0(sp)698; RV32-NEXT: vl8re32.v v16, (a0)699; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma700; RV32-NEXT: vadd.vv v8, v8, v16701; RV32-NEXT: ret702;703; RV64-LABEL: vector_arg_indirect_stack_no_gpr:704; RV64: # %bb.0:705; RV64-NEXT: ld a0, 0(sp)706; RV64-NEXT: vl8re32.v v16, (a0)707; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma708; RV64-NEXT: vadd.vv v8, v8, v16709; RV64-NEXT: ret710 %s = add <vscale x 16 x i32> %x, %z711 ret <vscale x 16 x i32> %s712}713 714; Calling the function above. Ensure we pass the arguments correctly.715define fastcc <vscale x 16 x i32> @pass_vector_arg_indirect_stack_no_gpr(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y, <vscale x 16 x i32> %z) {716; RV32-LABEL: pass_vector_arg_indirect_stack_no_gpr:717; RV32: # %bb.0:718; RV32-NEXT: addi sp, sp, -80719; RV32-NEXT: .cfi_def_cfa_offset 80720; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill721; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill722; RV32-NEXT: sw s1, 68(sp) # 4-byte Folded Spill723; RV32-NEXT: .cfi_offset ra, -4724; RV32-NEXT: .cfi_offset s0, -8725; RV32-NEXT: .cfi_offset s1, -12726; RV32-NEXT: addi s0, sp, 80727; RV32-NEXT: .cfi_def_cfa s0, 0728; RV32-NEXT: csrr a0, vlenb729; RV32-NEXT: slli a0, a0, 3730; RV32-NEXT: sub sp, sp, a0731; RV32-NEXT: andi sp, sp, -64732; RV32-NEXT: mv s1, sp733; RV32-NEXT: addi sp, sp, -16734; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma735; RV32-NEXT: vmv.v.i v8, 0736; RV32-NEXT: addi a0, s1, 64737; RV32-NEXT: li a1, 1738; RV32-NEXT: li a2, 2739; RV32-NEXT: li a3, 3740; RV32-NEXT: li a4, 4741; RV32-NEXT: li a5, 5742; RV32-NEXT: li a6, 6743; RV32-NEXT: li a7, 7744; RV32-NEXT: li t3, 8745; RV32-NEXT: li t4, 9746; RV32-NEXT: li t5, 10747; RV32-NEXT: li t6, 11748; RV32-NEXT: vs8r.v v8, (a0)749; RV32-NEXT: sw a0, 0(sp)750; RV32-NEXT: li a0, 0751; RV32-NEXT: vmv.v.i v16, 0752; RV32-NEXT: call vector_arg_indirect_stack_no_gpr753; RV32-NEXT: addi sp, sp, 16754; RV32-NEXT: addi sp, s0, -80755; RV32-NEXT: .cfi_def_cfa sp, 80756; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload757; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload758; RV32-NEXT: lw s1, 68(sp) # 4-byte Folded Reload759; RV32-NEXT: .cfi_restore ra760; RV32-NEXT: .cfi_restore s0761; RV32-NEXT: .cfi_restore s1762; RV32-NEXT: addi sp, sp, 80763; RV32-NEXT: .cfi_def_cfa_offset 0764; RV32-NEXT: ret765;766; RV64-LABEL: pass_vector_arg_indirect_stack_no_gpr:767; RV64: # %bb.0:768; RV64-NEXT: addi sp, sp, -96769; RV64-NEXT: .cfi_def_cfa_offset 96770; RV64-NEXT: sd ra, 88(sp) # 8-byte Folded Spill771; RV64-NEXT: sd s0, 80(sp) # 8-byte Folded Spill772; RV64-NEXT: sd s1, 72(sp) # 8-byte Folded Spill773; RV64-NEXT: .cfi_offset ra, -8774; RV64-NEXT: .cfi_offset s0, -16775; RV64-NEXT: .cfi_offset s1, -24776; RV64-NEXT: addi s0, sp, 96777; RV64-NEXT: .cfi_def_cfa s0, 0778; RV64-NEXT: csrr a0, vlenb779; RV64-NEXT: slli a0, a0, 3780; RV64-NEXT: sub sp, sp, a0781; RV64-NEXT: andi sp, sp, -64782; RV64-NEXT: mv s1, sp783; RV64-NEXT: addi sp, sp, -16784; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma785; RV64-NEXT: vmv.v.i v8, 0786; RV64-NEXT: addi a0, s1, 64787; RV64-NEXT: li a1, 1788; RV64-NEXT: li a2, 2789; RV64-NEXT: li a3, 3790; RV64-NEXT: li a4, 4791; RV64-NEXT: li a5, 5792; RV64-NEXT: li a6, 6793; RV64-NEXT: li a7, 7794; RV64-NEXT: li t3, 8795; RV64-NEXT: li t4, 9796; RV64-NEXT: li t5, 10797; RV64-NEXT: li t6, 11798; RV64-NEXT: vs8r.v v8, (a0)799; RV64-NEXT: sd a0, 0(sp)800; RV64-NEXT: li a0, 0801; RV64-NEXT: vmv.v.i v16, 0802; RV64-NEXT: call vector_arg_indirect_stack_no_gpr803; RV64-NEXT: addi sp, sp, 16804; RV64-NEXT: addi sp, s0, -96805; RV64-NEXT: .cfi_def_cfa sp, 96806; RV64-NEXT: ld ra, 88(sp) # 8-byte Folded Reload807; RV64-NEXT: ld s0, 80(sp) # 8-byte Folded Reload808; RV64-NEXT: ld s1, 72(sp) # 8-byte Folded Reload809; RV64-NEXT: .cfi_restore ra810; RV64-NEXT: .cfi_restore s0811; RV64-NEXT: .cfi_restore s1812; RV64-NEXT: addi sp, sp, 96813; RV64-NEXT: .cfi_def_cfa_offset 0814; RV64-NEXT: ret815 %s = call fastcc <vscale x 16 x i32> @vector_arg_indirect_stack_no_gpr(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> zeroinitializer)816 ret <vscale x 16 x i32> %s817}818