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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH,RV32ZFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH,RV64ZFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN,RV32ZFH11; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN,RV64ZFH14 15define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: vp_ceil_vv_nxv1bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma19; CHECK-NEXT: vmv1r.v v9, v020; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t21; CHECK-NEXT: lui a0, 30720022; CHECK-NEXT: vmv1r.v v8, v023; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma24; CHECK-NEXT: vfabs.v v11, v10, v0.t25; CHECK-NEXT: fmv.w.x fa5, a026; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu27; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t28; CHECK-NEXT: fsrmi a0, 329; CHECK-NEXT: vmv1r.v v0, v830; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma31; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t32; CHECK-NEXT: fsrm a033; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t34; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu35; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t36; CHECK-NEXT: vmv1r.v v0, v937; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma38; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t39; CHECK-NEXT: ret40 %v = call <vscale x 1 x bfloat> @llvm.vp.ceil.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)41 ret <vscale x 1 x bfloat> %v42}43 44define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {45; CHECK-LABEL: vp_ceil_vv_nxv1bf16_unmasked:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma48; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v849; CHECK-NEXT: lui a0, 30720050; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma51; CHECK-NEXT: vfabs.v v8, v952; CHECK-NEXT: fmv.w.x fa5, a053; CHECK-NEXT: vmflt.vf v0, v8, fa554; CHECK-NEXT: fsrmi a0, 355; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t56; CHECK-NEXT: fsrm a057; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t58; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu59; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t60; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma61; CHECK-NEXT: vfncvtbf16.f.f.w v8, v962; CHECK-NEXT: ret63 %v = call <vscale x 1 x bfloat> @llvm.vp.ceil.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)64 ret <vscale x 1 x bfloat> %v65}66 67define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {68; CHECK-LABEL: vp_ceil_vv_nxv2bf16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma71; CHECK-NEXT: vmv1r.v v9, v072; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t73; CHECK-NEXT: lui a0, 30720074; CHECK-NEXT: vmv1r.v v8, v075; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma76; CHECK-NEXT: vfabs.v v11, v10, v0.t77; CHECK-NEXT: fmv.w.x fa5, a078; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu79; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t80; CHECK-NEXT: fsrmi a0, 381; CHECK-NEXT: vmv.v.v v0, v882; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma83; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t84; CHECK-NEXT: fsrm a085; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t86; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu87; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t88; CHECK-NEXT: vmv1r.v v0, v989; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma90; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t91; CHECK-NEXT: ret92 %v = call <vscale x 2 x bfloat> @llvm.vp.ceil.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)93 ret <vscale x 2 x bfloat> %v94}95 96define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {97; CHECK-LABEL: vp_ceil_vv_nxv2bf16_unmasked:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma100; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8101; CHECK-NEXT: lui a0, 307200102; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma103; CHECK-NEXT: vfabs.v v8, v9104; CHECK-NEXT: fmv.w.x fa5, a0105; CHECK-NEXT: vmflt.vf v0, v8, fa5106; CHECK-NEXT: fsrmi a0, 3107; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t108; CHECK-NEXT: fsrm a0109; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t110; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu111; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t112; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma113; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9114; CHECK-NEXT: ret115 %v = call <vscale x 2 x bfloat> @llvm.vp.ceil.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)116 ret <vscale x 2 x bfloat> %v117}118 119define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: vp_ceil_vv_nxv4bf16:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma123; CHECK-NEXT: vmv1r.v v9, v0124; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t125; CHECK-NEXT: lui a0, 307200126; CHECK-NEXT: vmv1r.v v8, v0127; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma128; CHECK-NEXT: vfabs.v v12, v10, v0.t129; CHECK-NEXT: fmv.w.x fa5, a0130; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu131; CHECK-NEXT: vmflt.vf v8, v12, fa5, v0.t132; CHECK-NEXT: fsrmi a0, 3133; CHECK-NEXT: vmv1r.v v0, v8134; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma135; CHECK-NEXT: vfcvt.x.f.v v12, v10, v0.t136; CHECK-NEXT: fsrm a0137; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t138; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu139; CHECK-NEXT: vfsgnj.vv v10, v12, v10, v0.t140; CHECK-NEXT: vmv1r.v v0, v9141; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma142; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t143; CHECK-NEXT: ret144 %v = call <vscale x 4 x bfloat> @llvm.vp.ceil.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)145 ret <vscale x 4 x bfloat> %v146}147 148define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {149; CHECK-LABEL: vp_ceil_vv_nxv4bf16_unmasked:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma152; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8153; CHECK-NEXT: lui a0, 307200154; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma155; CHECK-NEXT: vfabs.v v8, v10156; CHECK-NEXT: fmv.w.x fa5, a0157; CHECK-NEXT: vmflt.vf v0, v8, fa5158; CHECK-NEXT: fsrmi a0, 3159; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t160; CHECK-NEXT: fsrm a0161; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t162; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu163; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t164; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma165; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10166; CHECK-NEXT: ret167 %v = call <vscale x 4 x bfloat> @llvm.vp.ceil.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)168 ret <vscale x 4 x bfloat> %v169}170 171define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: vp_ceil_vv_nxv8bf16:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma175; CHECK-NEXT: vmv1r.v v10, v0176; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t177; CHECK-NEXT: lui a0, 307200178; CHECK-NEXT: vmv1r.v v8, v0179; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma180; CHECK-NEXT: vfabs.v v16, v12, v0.t181; CHECK-NEXT: fmv.w.x fa5, a0182; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu183; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t184; CHECK-NEXT: fsrmi a0, 3185; CHECK-NEXT: vmv1r.v v0, v8186; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma187; CHECK-NEXT: vfcvt.x.f.v v16, v12, v0.t188; CHECK-NEXT: fsrm a0189; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t190; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu191; CHECK-NEXT: vfsgnj.vv v12, v16, v12, v0.t192; CHECK-NEXT: vmv1r.v v0, v10193; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma194; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t195; CHECK-NEXT: ret196 %v = call <vscale x 8 x bfloat> @llvm.vp.ceil.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)197 ret <vscale x 8 x bfloat> %v198}199 200define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {201; CHECK-LABEL: vp_ceil_vv_nxv8bf16_unmasked:202; CHECK: # %bb.0:203; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma204; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8205; CHECK-NEXT: lui a0, 307200206; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma207; CHECK-NEXT: vfabs.v v8, v12208; CHECK-NEXT: fmv.w.x fa5, a0209; CHECK-NEXT: vmflt.vf v0, v8, fa5210; CHECK-NEXT: fsrmi a0, 3211; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t212; CHECK-NEXT: fsrm a0213; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t214; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu215; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t216; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma217; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12218; CHECK-NEXT: ret219 %v = call <vscale x 8 x bfloat> @llvm.vp.ceil.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)220 ret <vscale x 8 x bfloat> %v221}222 223define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: vp_ceil_vv_nxv16bf16:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma227; CHECK-NEXT: vmv1r.v v12, v0228; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t229; CHECK-NEXT: lui a0, 307200230; CHECK-NEXT: vmv1r.v v8, v0231; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma232; CHECK-NEXT: vfabs.v v24, v16, v0.t233; CHECK-NEXT: fmv.w.x fa5, a0234; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu235; CHECK-NEXT: vmflt.vf v8, v24, fa5, v0.t236; CHECK-NEXT: fsrmi a0, 3237; CHECK-NEXT: vmv1r.v v0, v8238; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma239; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t240; CHECK-NEXT: fsrm a0241; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t242; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu243; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t244; CHECK-NEXT: vmv1r.v v0, v12245; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma246; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t247; CHECK-NEXT: ret248 %v = call <vscale x 16 x bfloat> @llvm.vp.ceil.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)249 ret <vscale x 16 x bfloat> %v250}251 252define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {253; CHECK-LABEL: vp_ceil_vv_nxv16bf16_unmasked:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma256; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8257; CHECK-NEXT: lui a0, 307200258; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma259; CHECK-NEXT: vfabs.v v8, v16260; CHECK-NEXT: fmv.w.x fa5, a0261; CHECK-NEXT: vmflt.vf v0, v8, fa5262; CHECK-NEXT: fsrmi a0, 3263; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t264; CHECK-NEXT: fsrm a0265; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t266; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu267; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t268; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma269; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16270; CHECK-NEXT: ret271 %v = call <vscale x 16 x bfloat> @llvm.vp.ceil.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)272 ret <vscale x 16 x bfloat> %v273}274 275define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {276; CHECK-LABEL: vp_ceil_vv_nxv32bf16:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma279; CHECK-NEXT: vmv1r.v v7, v0280; CHECK-NEXT: csrr a2, vlenb281; CHECK-NEXT: lui a3, 307200282; CHECK-NEXT: slli a1, a2, 1283; CHECK-NEXT: srli a2, a2, 2284; CHECK-NEXT: fmv.w.x fa5, a3285; CHECK-NEXT: sub a3, a0, a1286; CHECK-NEXT: vslidedown.vx v6, v0, a2287; CHECK-NEXT: sltu a2, a0, a3288; CHECK-NEXT: vmv1r.v v5, v6289; CHECK-NEXT: addi a2, a2, -1290; CHECK-NEXT: and a2, a2, a3291; CHECK-NEXT: vmv1r.v v0, v6292; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma293; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t294; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma295; CHECK-NEXT: vfabs.v v16, v24, v0.t296; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu297; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t298; CHECK-NEXT: fsrmi a2, 3299; CHECK-NEXT: vmv1r.v v0, v5300; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma301; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t302; CHECK-NEXT: fsrm a2303; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t304; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu305; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t306; CHECK-NEXT: vmv1r.v v0, v6307; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma308; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t309; CHECK-NEXT: bltu a0, a1, .LBB10_2310; CHECK-NEXT: # %bb.1:311; CHECK-NEXT: mv a0, a1312; CHECK-NEXT: .LBB10_2:313; CHECK-NEXT: vmv1r.v v0, v7314; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma315; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t316; CHECK-NEXT: vmv1r.v v8, v7317; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma318; CHECK-NEXT: vfabs.v v16, v24, v0.t319; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu320; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t321; CHECK-NEXT: fsrmi a0, 3322; CHECK-NEXT: vmv1r.v v0, v8323; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma324; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t325; CHECK-NEXT: fsrm a0326; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t327; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu328; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t329; CHECK-NEXT: vmv1r.v v0, v7330; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma331; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t332; CHECK-NEXT: ret333 %v = call <vscale x 32 x bfloat> @llvm.vp.ceil.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)334 ret <vscale x 32 x bfloat> %v335}336 337define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {338; CHECK-LABEL: vp_ceil_vv_nxv32bf16_unmasked:339; CHECK: # %bb.0:340; CHECK-NEXT: csrr a2, vlenb341; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma342; CHECK-NEXT: vmset.m v16343; CHECK-NEXT: lui a3, 307200344; CHECK-NEXT: slli a1, a2, 1345; CHECK-NEXT: srli a2, a2, 2346; CHECK-NEXT: fmv.w.x fa5, a3347; CHECK-NEXT: sub a3, a0, a1348; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma349; CHECK-NEXT: vslidedown.vx v7, v16, a2350; CHECK-NEXT: sltu a2, a0, a3351; CHECK-NEXT: vmv1r.v v6, v7352; CHECK-NEXT: addi a2, a2, -1353; CHECK-NEXT: and a2, a2, a3354; CHECK-NEXT: vmv1r.v v0, v7355; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma356; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t357; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma358; CHECK-NEXT: vfabs.v v16, v24, v0.t359; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu360; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t361; CHECK-NEXT: fsrmi a2, 3362; CHECK-NEXT: vmv1r.v v0, v6363; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma364; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t365; CHECK-NEXT: fsrm a2366; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t367; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu368; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t369; CHECK-NEXT: vmv1r.v v0, v7370; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma371; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t372; CHECK-NEXT: bltu a0, a1, .LBB11_2373; CHECK-NEXT: # %bb.1:374; CHECK-NEXT: mv a0, a1375; CHECK-NEXT: .LBB11_2:376; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma377; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8378; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma379; CHECK-NEXT: vfabs.v v24, v16380; CHECK-NEXT: vmflt.vf v0, v24, fa5381; CHECK-NEXT: fsrmi a0, 3382; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t383; CHECK-NEXT: fsrm a0384; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t385; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu386; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t387; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma388; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16389; CHECK-NEXT: ret390 %v = call <vscale x 32 x bfloat> @llvm.vp.ceil.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)391 ret <vscale x 32 x bfloat> %v392}393 394define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {395; ZVFH-LABEL: vp_ceil_vv_nxv1f16:396; ZVFH: # %bb.0:397; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma398; ZVFH-NEXT: vfabs.v v9, v8, v0.t399; ZVFH-NEXT: li a0, 25400; ZVFH-NEXT: slli a0, a0, 10401; ZVFH-NEXT: fmv.h.x fa5, a0402; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu403; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t404; ZVFH-NEXT: fsrmi a0, 3405; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma406; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t407; ZVFH-NEXT: fsrm a0408; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t409; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu410; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t411; ZVFH-NEXT: ret412;413; ZVFHMIN-LABEL: vp_ceil_vv_nxv1f16:414; ZVFHMIN: # %bb.0:415; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma416; ZVFHMIN-NEXT: vmv1r.v v9, v0417; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t418; ZVFHMIN-NEXT: lui a0, 307200419; ZVFHMIN-NEXT: vmv1r.v v8, v0420; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma421; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t422; ZVFHMIN-NEXT: fmv.w.x fa5, a0423; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu424; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t425; ZVFHMIN-NEXT: fsrmi a0, 3426; ZVFHMIN-NEXT: vmv1r.v v0, v8427; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma428; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t429; ZVFHMIN-NEXT: fsrm a0430; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t431; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu432; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t433; ZVFHMIN-NEXT: vmv1r.v v0, v9434; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma435; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t436; ZVFHMIN-NEXT: ret437 %v = call <vscale x 1 x half> @llvm.vp.ceil.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)438 ret <vscale x 1 x half> %v439}440 441define <vscale x 1 x half> @vp_ceil_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {442; ZVFH-LABEL: vp_ceil_vv_nxv1f16_unmasked:443; ZVFH: # %bb.0:444; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma445; ZVFH-NEXT: vfabs.v v9, v8446; ZVFH-NEXT: li a0, 25447; ZVFH-NEXT: slli a0, a0, 10448; ZVFH-NEXT: fmv.h.x fa5, a0449; ZVFH-NEXT: vmflt.vf v0, v9, fa5450; ZVFH-NEXT: fsrmi a0, 3451; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t452; ZVFH-NEXT: fsrm a0453; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t454; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu455; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t456; ZVFH-NEXT: ret457;458; ZVFHMIN-LABEL: vp_ceil_vv_nxv1f16_unmasked:459; ZVFHMIN: # %bb.0:460; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma461; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8462; ZVFHMIN-NEXT: lui a0, 307200463; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma464; ZVFHMIN-NEXT: vfabs.v v8, v9465; ZVFHMIN-NEXT: fmv.w.x fa5, a0466; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5467; ZVFHMIN-NEXT: fsrmi a0, 3468; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t469; ZVFHMIN-NEXT: fsrm a0470; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t471; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu472; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t473; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma474; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9475; ZVFHMIN-NEXT: ret476 %v = call <vscale x 1 x half> @llvm.vp.ceil.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)477 ret <vscale x 1 x half> %v478}479 480define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {481; ZVFH-LABEL: vp_ceil_vv_nxv2f16:482; ZVFH: # %bb.0:483; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma484; ZVFH-NEXT: vfabs.v v9, v8, v0.t485; ZVFH-NEXT: li a0, 25486; ZVFH-NEXT: slli a0, a0, 10487; ZVFH-NEXT: fmv.h.x fa5, a0488; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu489; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t490; ZVFH-NEXT: fsrmi a0, 3491; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma492; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t493; ZVFH-NEXT: fsrm a0494; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t495; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu496; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t497; ZVFH-NEXT: ret498;499; ZVFHMIN-LABEL: vp_ceil_vv_nxv2f16:500; ZVFHMIN: # %bb.0:501; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma502; ZVFHMIN-NEXT: vmv1r.v v9, v0503; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t504; ZVFHMIN-NEXT: lui a0, 307200505; ZVFHMIN-NEXT: vmv1r.v v8, v0506; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma507; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t508; ZVFHMIN-NEXT: fmv.w.x fa5, a0509; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu510; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t511; ZVFHMIN-NEXT: fsrmi a0, 3512; ZVFHMIN-NEXT: vmv.v.v v0, v8513; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma514; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t515; ZVFHMIN-NEXT: fsrm a0516; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t517; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu518; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t519; ZVFHMIN-NEXT: vmv1r.v v0, v9520; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma521; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t522; ZVFHMIN-NEXT: ret523 %v = call <vscale x 2 x half> @llvm.vp.ceil.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)524 ret <vscale x 2 x half> %v525}526 527define <vscale x 2 x half> @vp_ceil_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {528; ZVFH-LABEL: vp_ceil_vv_nxv2f16_unmasked:529; ZVFH: # %bb.0:530; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma531; ZVFH-NEXT: vfabs.v v9, v8532; ZVFH-NEXT: li a0, 25533; ZVFH-NEXT: slli a0, a0, 10534; ZVFH-NEXT: fmv.h.x fa5, a0535; ZVFH-NEXT: vmflt.vf v0, v9, fa5536; ZVFH-NEXT: fsrmi a0, 3537; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t538; ZVFH-NEXT: fsrm a0539; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t540; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu541; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t542; ZVFH-NEXT: ret543;544; ZVFHMIN-LABEL: vp_ceil_vv_nxv2f16_unmasked:545; ZVFHMIN: # %bb.0:546; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma547; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8548; ZVFHMIN-NEXT: lui a0, 307200549; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma550; ZVFHMIN-NEXT: vfabs.v v8, v9551; ZVFHMIN-NEXT: fmv.w.x fa5, a0552; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5553; ZVFHMIN-NEXT: fsrmi a0, 3554; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t555; ZVFHMIN-NEXT: fsrm a0556; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t557; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu558; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t559; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma560; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9561; ZVFHMIN-NEXT: ret562 %v = call <vscale x 2 x half> @llvm.vp.ceil.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)563 ret <vscale x 2 x half> %v564}565 566define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {567; ZVFH-LABEL: vp_ceil_vv_nxv4f16:568; ZVFH: # %bb.0:569; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma570; ZVFH-NEXT: vfabs.v v9, v8, v0.t571; ZVFH-NEXT: li a0, 25572; ZVFH-NEXT: slli a0, a0, 10573; ZVFH-NEXT: fmv.h.x fa5, a0574; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu575; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t576; ZVFH-NEXT: fsrmi a0, 3577; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma578; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t579; ZVFH-NEXT: fsrm a0580; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t581; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu582; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t583; ZVFH-NEXT: ret584;585; ZVFHMIN-LABEL: vp_ceil_vv_nxv4f16:586; ZVFHMIN: # %bb.0:587; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma588; ZVFHMIN-NEXT: vmv1r.v v9, v0589; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t590; ZVFHMIN-NEXT: lui a0, 307200591; ZVFHMIN-NEXT: vmv1r.v v8, v0592; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma593; ZVFHMIN-NEXT: vfabs.v v12, v10, v0.t594; ZVFHMIN-NEXT: fmv.w.x fa5, a0595; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu596; ZVFHMIN-NEXT: vmflt.vf v8, v12, fa5, v0.t597; ZVFHMIN-NEXT: fsrmi a0, 3598; ZVFHMIN-NEXT: vmv1r.v v0, v8599; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma600; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t601; ZVFHMIN-NEXT: fsrm a0602; ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t603; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu604; ZVFHMIN-NEXT: vfsgnj.vv v10, v12, v10, v0.t605; ZVFHMIN-NEXT: vmv1r.v v0, v9606; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma607; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t608; ZVFHMIN-NEXT: ret609 %v = call <vscale x 4 x half> @llvm.vp.ceil.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)610 ret <vscale x 4 x half> %v611}612 613define <vscale x 4 x half> @vp_ceil_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {614; ZVFH-LABEL: vp_ceil_vv_nxv4f16_unmasked:615; ZVFH: # %bb.0:616; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma617; ZVFH-NEXT: vfabs.v v9, v8618; ZVFH-NEXT: li a0, 25619; ZVFH-NEXT: slli a0, a0, 10620; ZVFH-NEXT: fmv.h.x fa5, a0621; ZVFH-NEXT: vmflt.vf v0, v9, fa5622; ZVFH-NEXT: fsrmi a0, 3623; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t624; ZVFH-NEXT: fsrm a0625; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t626; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu627; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t628; ZVFH-NEXT: ret629;630; ZVFHMIN-LABEL: vp_ceil_vv_nxv4f16_unmasked:631; ZVFHMIN: # %bb.0:632; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma633; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8634; ZVFHMIN-NEXT: lui a0, 307200635; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma636; ZVFHMIN-NEXT: vfabs.v v8, v10637; ZVFHMIN-NEXT: fmv.w.x fa5, a0638; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5639; ZVFHMIN-NEXT: fsrmi a0, 3640; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t641; ZVFHMIN-NEXT: fsrm a0642; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t643; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu644; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t645; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma646; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10647; ZVFHMIN-NEXT: ret648 %v = call <vscale x 4 x half> @llvm.vp.ceil.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)649 ret <vscale x 4 x half> %v650}651 652define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {653; ZVFH-LABEL: vp_ceil_vv_nxv8f16:654; ZVFH: # %bb.0:655; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma656; ZVFH-NEXT: vmv1r.v v10, v0657; ZVFH-NEXT: vfabs.v v12, v8, v0.t658; ZVFH-NEXT: li a0, 25659; ZVFH-NEXT: slli a0, a0, 10660; ZVFH-NEXT: fmv.h.x fa5, a0661; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu662; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t663; ZVFH-NEXT: fsrmi a0, 3664; ZVFH-NEXT: vmv1r.v v0, v10665; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma666; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t667; ZVFH-NEXT: fsrm a0668; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t669; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu670; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t671; ZVFH-NEXT: ret672;673; ZVFHMIN-LABEL: vp_ceil_vv_nxv8f16:674; ZVFHMIN: # %bb.0:675; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma676; ZVFHMIN-NEXT: vmv1r.v v10, v0677; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t678; ZVFHMIN-NEXT: lui a0, 307200679; ZVFHMIN-NEXT: vmv1r.v v8, v0680; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma681; ZVFHMIN-NEXT: vfabs.v v16, v12, v0.t682; ZVFHMIN-NEXT: fmv.w.x fa5, a0683; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu684; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t685; ZVFHMIN-NEXT: fsrmi a0, 3686; ZVFHMIN-NEXT: vmv1r.v v0, v8687; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma688; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t689; ZVFHMIN-NEXT: fsrm a0690; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t691; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu692; ZVFHMIN-NEXT: vfsgnj.vv v12, v16, v12, v0.t693; ZVFHMIN-NEXT: vmv1r.v v0, v10694; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma695; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t696; ZVFHMIN-NEXT: ret697 %v = call <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)698 ret <vscale x 8 x half> %v699}700 701define <vscale x 8 x half> @vp_ceil_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {702; ZVFH-LABEL: vp_ceil_vv_nxv8f16_unmasked:703; ZVFH: # %bb.0:704; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma705; ZVFH-NEXT: vfabs.v v10, v8706; ZVFH-NEXT: li a0, 25707; ZVFH-NEXT: slli a0, a0, 10708; ZVFH-NEXT: fmv.h.x fa5, a0709; ZVFH-NEXT: vmflt.vf v0, v10, fa5710; ZVFH-NEXT: fsrmi a0, 3711; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t712; ZVFH-NEXT: fsrm a0713; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t714; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu715; ZVFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t716; ZVFH-NEXT: ret717;718; ZVFHMIN-LABEL: vp_ceil_vv_nxv8f16_unmasked:719; ZVFHMIN: # %bb.0:720; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma721; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8722; ZVFHMIN-NEXT: lui a0, 307200723; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma724; ZVFHMIN-NEXT: vfabs.v v8, v12725; ZVFHMIN-NEXT: fmv.w.x fa5, a0726; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5727; ZVFHMIN-NEXT: fsrmi a0, 3728; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t729; ZVFHMIN-NEXT: fsrm a0730; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t731; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu732; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t733; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma734; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12735; ZVFHMIN-NEXT: ret736 %v = call <vscale x 8 x half> @llvm.vp.ceil.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)737 ret <vscale x 8 x half> %v738}739 740define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {741; ZVFH-LABEL: vp_ceil_vv_nxv16f16:742; ZVFH: # %bb.0:743; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma744; ZVFH-NEXT: vmv1r.v v12, v0745; ZVFH-NEXT: vfabs.v v16, v8, v0.t746; ZVFH-NEXT: li a0, 25747; ZVFH-NEXT: slli a0, a0, 10748; ZVFH-NEXT: fmv.h.x fa5, a0749; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu750; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t751; ZVFH-NEXT: fsrmi a0, 3752; ZVFH-NEXT: vmv1r.v v0, v12753; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma754; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t755; ZVFH-NEXT: fsrm a0756; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t757; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu758; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t759; ZVFH-NEXT: ret760;761; ZVFHMIN-LABEL: vp_ceil_vv_nxv16f16:762; ZVFHMIN: # %bb.0:763; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma764; ZVFHMIN-NEXT: vmv1r.v v12, v0765; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t766; ZVFHMIN-NEXT: lui a0, 307200767; ZVFHMIN-NEXT: vmv1r.v v8, v0768; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma769; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t770; ZVFHMIN-NEXT: fmv.w.x fa5, a0771; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu772; ZVFHMIN-NEXT: vmflt.vf v8, v24, fa5, v0.t773; ZVFHMIN-NEXT: fsrmi a0, 3774; ZVFHMIN-NEXT: vmv1r.v v0, v8775; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma776; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t777; ZVFHMIN-NEXT: fsrm a0778; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t779; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu780; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t781; ZVFHMIN-NEXT: vmv1r.v v0, v12782; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma783; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t784; ZVFHMIN-NEXT: ret785 %v = call <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)786 ret <vscale x 16 x half> %v787}788 789define <vscale x 16 x half> @vp_ceil_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {790; ZVFH-LABEL: vp_ceil_vv_nxv16f16_unmasked:791; ZVFH: # %bb.0:792; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma793; ZVFH-NEXT: vfabs.v v12, v8794; ZVFH-NEXT: li a0, 25795; ZVFH-NEXT: slli a0, a0, 10796; ZVFH-NEXT: fmv.h.x fa5, a0797; ZVFH-NEXT: vmflt.vf v0, v12, fa5798; ZVFH-NEXT: fsrmi a0, 3799; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t800; ZVFH-NEXT: fsrm a0801; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t802; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu803; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t804; ZVFH-NEXT: ret805;806; ZVFHMIN-LABEL: vp_ceil_vv_nxv16f16_unmasked:807; ZVFHMIN: # %bb.0:808; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma809; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8810; ZVFHMIN-NEXT: lui a0, 307200811; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma812; ZVFHMIN-NEXT: vfabs.v v8, v16813; ZVFHMIN-NEXT: fmv.w.x fa5, a0814; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5815; ZVFHMIN-NEXT: fsrmi a0, 3816; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t817; ZVFHMIN-NEXT: fsrm a0818; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t819; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu820; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t821; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma822; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16823; ZVFHMIN-NEXT: ret824 %v = call <vscale x 16 x half> @llvm.vp.ceil.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)825 ret <vscale x 16 x half> %v826}827 828define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {829; ZVFH-LABEL: vp_ceil_vv_nxv32f16:830; ZVFH: # %bb.0:831; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma832; ZVFH-NEXT: vmv1r.v v16, v0833; ZVFH-NEXT: vfabs.v v24, v8, v0.t834; ZVFH-NEXT: li a0, 25835; ZVFH-NEXT: slli a0, a0, 10836; ZVFH-NEXT: fmv.h.x fa5, a0837; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu838; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t839; ZVFH-NEXT: fsrmi a0, 3840; ZVFH-NEXT: vmv1r.v v0, v16841; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma842; ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t843; ZVFH-NEXT: fsrm a0844; ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t845; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu846; ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t847; ZVFH-NEXT: ret848;849; ZVFHMIN-LABEL: vp_ceil_vv_nxv32f16:850; ZVFHMIN: # %bb.0:851; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma852; ZVFHMIN-NEXT: vmv1r.v v7, v0853; ZVFHMIN-NEXT: csrr a2, vlenb854; ZVFHMIN-NEXT: lui a3, 307200855; ZVFHMIN-NEXT: slli a1, a2, 1856; ZVFHMIN-NEXT: srli a2, a2, 2857; ZVFHMIN-NEXT: fmv.w.x fa5, a3858; ZVFHMIN-NEXT: sub a3, a0, a1859; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2860; ZVFHMIN-NEXT: sltu a2, a0, a3861; ZVFHMIN-NEXT: vmv1r.v v5, v6862; ZVFHMIN-NEXT: addi a2, a2, -1863; ZVFHMIN-NEXT: and a2, a2, a3864; ZVFHMIN-NEXT: vmv1r.v v0, v6865; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma866; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t867; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma868; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t869; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu870; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t871; ZVFHMIN-NEXT: fsrmi a2, 3872; ZVFHMIN-NEXT: vmv1r.v v0, v5873; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma874; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t875; ZVFHMIN-NEXT: fsrm a2876; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t877; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu878; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t879; ZVFHMIN-NEXT: vmv1r.v v0, v6880; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma881; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t882; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2883; ZVFHMIN-NEXT: # %bb.1:884; ZVFHMIN-NEXT: mv a0, a1885; ZVFHMIN-NEXT: .LBB22_2:886; ZVFHMIN-NEXT: vmv1r.v v0, v7887; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma888; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t889; ZVFHMIN-NEXT: vmv1r.v v8, v7890; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma891; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t892; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu893; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t894; ZVFHMIN-NEXT: fsrmi a0, 3895; ZVFHMIN-NEXT: vmv1r.v v0, v8896; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma897; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t898; ZVFHMIN-NEXT: fsrm a0899; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t900; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu901; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t902; ZVFHMIN-NEXT: vmv1r.v v0, v7903; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma904; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t905; ZVFHMIN-NEXT: ret906 %v = call <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)907 ret <vscale x 32 x half> %v908}909 910define <vscale x 32 x half> @vp_ceil_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {911; ZVFH-LABEL: vp_ceil_vv_nxv32f16_unmasked:912; ZVFH: # %bb.0:913; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma914; ZVFH-NEXT: vfabs.v v16, v8915; ZVFH-NEXT: li a0, 25916; ZVFH-NEXT: slli a0, a0, 10917; ZVFH-NEXT: fmv.h.x fa5, a0918; ZVFH-NEXT: vmflt.vf v0, v16, fa5919; ZVFH-NEXT: fsrmi a0, 3920; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t921; ZVFH-NEXT: fsrm a0922; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t923; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu924; ZVFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t925; ZVFH-NEXT: ret926;927; ZVFHMIN-LABEL: vp_ceil_vv_nxv32f16_unmasked:928; ZVFHMIN: # %bb.0:929; ZVFHMIN-NEXT: csrr a2, vlenb930; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma931; ZVFHMIN-NEXT: vmset.m v16932; ZVFHMIN-NEXT: lui a3, 307200933; ZVFHMIN-NEXT: slli a1, a2, 1934; ZVFHMIN-NEXT: srli a2, a2, 2935; ZVFHMIN-NEXT: fmv.w.x fa5, a3936; ZVFHMIN-NEXT: sub a3, a0, a1937; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma938; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2939; ZVFHMIN-NEXT: sltu a2, a0, a3940; ZVFHMIN-NEXT: vmv1r.v v6, v7941; ZVFHMIN-NEXT: addi a2, a2, -1942; ZVFHMIN-NEXT: and a2, a2, a3943; ZVFHMIN-NEXT: vmv1r.v v0, v7944; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma945; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t946; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma947; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t948; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu949; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t950; ZVFHMIN-NEXT: fsrmi a2, 3951; ZVFHMIN-NEXT: vmv1r.v v0, v6952; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma953; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t954; ZVFHMIN-NEXT: fsrm a2955; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t956; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu957; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t958; ZVFHMIN-NEXT: vmv1r.v v0, v7959; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma960; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t961; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2962; ZVFHMIN-NEXT: # %bb.1:963; ZVFHMIN-NEXT: mv a0, a1964; ZVFHMIN-NEXT: .LBB23_2:965; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma966; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8967; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma968; ZVFHMIN-NEXT: vfabs.v v24, v16969; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5970; ZVFHMIN-NEXT: fsrmi a0, 3971; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t972; ZVFHMIN-NEXT: fsrm a0973; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t974; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu975; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t976; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma977; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16978; ZVFHMIN-NEXT: ret979 %v = call <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)980 ret <vscale x 32 x half> %v981}982 983define <vscale x 1 x float> @vp_ceil_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {984; CHECK-LABEL: vp_ceil_vv_nxv1f32:985; CHECK: # %bb.0:986; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma987; CHECK-NEXT: vfabs.v v9, v8, v0.t988; CHECK-NEXT: lui a0, 307200989; CHECK-NEXT: fmv.w.x fa5, a0990; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu991; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t992; CHECK-NEXT: fsrmi a0, 3993; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma994; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t995; CHECK-NEXT: fsrm a0996; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t997; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu998; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t999; CHECK-NEXT: ret1000 %v = call <vscale x 1 x float> @llvm.vp.ceil.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)1001 ret <vscale x 1 x float> %v1002}1003 1004define <vscale x 1 x float> @vp_ceil_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {1005; CHECK-LABEL: vp_ceil_vv_nxv1f32_unmasked:1006; CHECK: # %bb.0:1007; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1008; CHECK-NEXT: vfabs.v v9, v81009; CHECK-NEXT: lui a0, 3072001010; CHECK-NEXT: fmv.w.x fa5, a01011; CHECK-NEXT: vmflt.vf v0, v9, fa51012; CHECK-NEXT: fsrmi a0, 31013; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1014; CHECK-NEXT: fsrm a01015; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1016; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu1017; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1018; CHECK-NEXT: ret1019 %v = call <vscale x 1 x float> @llvm.vp.ceil.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1020 ret <vscale x 1 x float> %v1021}1022 1023define <vscale x 2 x float> @vp_ceil_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1024; CHECK-LABEL: vp_ceil_vv_nxv2f32:1025; CHECK: # %bb.0:1026; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1027; CHECK-NEXT: vfabs.v v9, v8, v0.t1028; CHECK-NEXT: lui a0, 3072001029; CHECK-NEXT: fmv.w.x fa5, a01030; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1031; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t1032; CHECK-NEXT: fsrmi a0, 31033; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1034; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1035; CHECK-NEXT: fsrm a01036; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1037; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1038; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1039; CHECK-NEXT: ret1040 %v = call <vscale x 2 x float> @llvm.vp.ceil.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)1041 ret <vscale x 2 x float> %v1042}1043 1044define <vscale x 2 x float> @vp_ceil_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {1045; CHECK-LABEL: vp_ceil_vv_nxv2f32_unmasked:1046; CHECK: # %bb.0:1047; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1048; CHECK-NEXT: vfabs.v v9, v81049; CHECK-NEXT: lui a0, 3072001050; CHECK-NEXT: fmv.w.x fa5, a01051; CHECK-NEXT: vmflt.vf v0, v9, fa51052; CHECK-NEXT: fsrmi a0, 31053; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t1054; CHECK-NEXT: fsrm a01055; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t1056; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu1057; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t1058; CHECK-NEXT: ret1059 %v = call <vscale x 2 x float> @llvm.vp.ceil.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1060 ret <vscale x 2 x float> %v1061}1062 1063define <vscale x 4 x float> @vp_ceil_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1064; CHECK-LABEL: vp_ceil_vv_nxv4f32:1065; CHECK: # %bb.0:1066; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1067; CHECK-NEXT: vmv1r.v v10, v01068; CHECK-NEXT: vfabs.v v12, v8, v0.t1069; CHECK-NEXT: lui a0, 3072001070; CHECK-NEXT: fmv.w.x fa5, a01071; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1072; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t1073; CHECK-NEXT: fsrmi a0, 31074; CHECK-NEXT: vmv1r.v v0, v101075; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1076; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t1077; CHECK-NEXT: fsrm a01078; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t1079; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1080; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t1081; CHECK-NEXT: ret1082 %v = call <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)1083 ret <vscale x 4 x float> %v1084}1085 1086define <vscale x 4 x float> @vp_ceil_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {1087; CHECK-LABEL: vp_ceil_vv_nxv4f32_unmasked:1088; CHECK: # %bb.0:1089; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1090; CHECK-NEXT: vfabs.v v10, v81091; CHECK-NEXT: lui a0, 3072001092; CHECK-NEXT: fmv.w.x fa5, a01093; CHECK-NEXT: vmflt.vf v0, v10, fa51094; CHECK-NEXT: fsrmi a0, 31095; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t1096; CHECK-NEXT: fsrm a01097; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t1098; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu1099; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t1100; CHECK-NEXT: ret1101 %v = call <vscale x 4 x float> @llvm.vp.ceil.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1102 ret <vscale x 4 x float> %v1103}1104 1105define <vscale x 8 x float> @vp_ceil_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1106; CHECK-LABEL: vp_ceil_vv_nxv8f32:1107; CHECK: # %bb.0:1108; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1109; CHECK-NEXT: vmv1r.v v12, v01110; CHECK-NEXT: vfabs.v v16, v8, v0.t1111; CHECK-NEXT: lui a0, 3072001112; CHECK-NEXT: fmv.w.x fa5, a01113; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1114; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t1115; CHECK-NEXT: fsrmi a0, 31116; CHECK-NEXT: vmv1r.v v0, v121117; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1118; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1119; CHECK-NEXT: fsrm a01120; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1121; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1122; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1123; CHECK-NEXT: ret1124 %v = call <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)1125 ret <vscale x 8 x float> %v1126}1127 1128define <vscale x 8 x float> @vp_ceil_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {1129; CHECK-LABEL: vp_ceil_vv_nxv8f32_unmasked:1130; CHECK: # %bb.0:1131; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1132; CHECK-NEXT: vfabs.v v12, v81133; CHECK-NEXT: lui a0, 3072001134; CHECK-NEXT: fmv.w.x fa5, a01135; CHECK-NEXT: vmflt.vf v0, v12, fa51136; CHECK-NEXT: fsrmi a0, 31137; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t1138; CHECK-NEXT: fsrm a01139; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t1140; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu1141; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t1142; CHECK-NEXT: ret1143 %v = call <vscale x 8 x float> @llvm.vp.ceil.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1144 ret <vscale x 8 x float> %v1145}1146 1147define <vscale x 16 x float> @vp_ceil_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1148; CHECK-LABEL: vp_ceil_vv_nxv16f32:1149; CHECK: # %bb.0:1150; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1151; CHECK-NEXT: vmv1r.v v16, v01152; CHECK-NEXT: vfabs.v v24, v8, v0.t1153; CHECK-NEXT: lui a0, 3072001154; CHECK-NEXT: fmv.w.x fa5, a01155; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1156; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t1157; CHECK-NEXT: fsrmi a0, 31158; CHECK-NEXT: vmv1r.v v0, v161159; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma1160; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t1161; CHECK-NEXT: fsrm a01162; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t1163; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1164; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t1165; CHECK-NEXT: ret1166 %v = call <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)1167 ret <vscale x 16 x float> %v1168}1169 1170define <vscale x 16 x float> @vp_ceil_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {1171; CHECK-LABEL: vp_ceil_vv_nxv16f32_unmasked:1172; CHECK: # %bb.0:1173; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1174; CHECK-NEXT: vfabs.v v16, v81175; CHECK-NEXT: lui a0, 3072001176; CHECK-NEXT: fmv.w.x fa5, a01177; CHECK-NEXT: vmflt.vf v0, v16, fa51178; CHECK-NEXT: fsrmi a0, 31179; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t1180; CHECK-NEXT: fsrm a01181; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t1182; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu1183; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t1184; CHECK-NEXT: ret1185 %v = call <vscale x 16 x float> @llvm.vp.ceil.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1186 ret <vscale x 16 x float> %v1187}1188 1189define <vscale x 1 x double> @vp_ceil_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1190; RV32ZFH-LABEL: vp_ceil_vv_nxv1f64:1191; RV32ZFH: # %bb.0:1192; RV32ZFH-NEXT: lui a1, %hi(.LCPI34_0)1193; RV32ZFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)1194; RV32ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1195; RV32ZFH-NEXT: vfabs.v v9, v8, v0.t1196; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1197; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1198; RV32ZFH-NEXT: fsrmi a0, 31199; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1200; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1201; RV32ZFH-NEXT: fsrm a01202; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1203; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1204; RV32ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1205; RV32ZFH-NEXT: ret1206;1207; RV64ZFH-LABEL: vp_ceil_vv_nxv1f64:1208; RV64ZFH: # %bb.0:1209; RV64ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1210; RV64ZFH-NEXT: vfabs.v v9, v8, v0.t1211; RV64ZFH-NEXT: li a0, 10751212; RV64ZFH-NEXT: slli a0, a0, 521213; RV64ZFH-NEXT: fmv.d.x fa5, a01214; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1215; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5, v0.t1216; RV64ZFH-NEXT: fsrmi a0, 31217; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma1218; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1219; RV64ZFH-NEXT: fsrm a01220; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1221; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1222; RV64ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1223; RV64ZFH-NEXT: ret1224 %v = call <vscale x 1 x double> @llvm.vp.ceil.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)1225 ret <vscale x 1 x double> %v1226}1227 1228define <vscale x 1 x double> @vp_ceil_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {1229; RV32ZFH-LABEL: vp_ceil_vv_nxv1f64_unmasked:1230; RV32ZFH: # %bb.0:1231; RV32ZFH-NEXT: lui a1, %hi(.LCPI35_0)1232; RV32ZFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)1233; RV32ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1234; RV32ZFH-NEXT: vfabs.v v9, v81235; RV32ZFH-NEXT: vmflt.vf v0, v9, fa51236; RV32ZFH-NEXT: fsrmi a0, 31237; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1238; RV32ZFH-NEXT: fsrm a01239; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1240; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1241; RV32ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1242; RV32ZFH-NEXT: ret1243;1244; RV64ZFH-LABEL: vp_ceil_vv_nxv1f64_unmasked:1245; RV64ZFH: # %bb.0:1246; RV64ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma1247; RV64ZFH-NEXT: vfabs.v v9, v81248; RV64ZFH-NEXT: li a0, 10751249; RV64ZFH-NEXT: slli a0, a0, 521250; RV64ZFH-NEXT: fmv.d.x fa5, a01251; RV64ZFH-NEXT: vmflt.vf v0, v9, fa51252; RV64ZFH-NEXT: fsrmi a0, 31253; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t1254; RV64ZFH-NEXT: fsrm a01255; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t1256; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu1257; RV64ZFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t1258; RV64ZFH-NEXT: ret1259 %v = call <vscale x 1 x double> @llvm.vp.ceil.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)1260 ret <vscale x 1 x double> %v1261}1262 1263define <vscale x 2 x double> @vp_ceil_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1264; RV32ZFH-LABEL: vp_ceil_vv_nxv2f64:1265; RV32ZFH: # %bb.0:1266; RV32ZFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1267; RV32ZFH-NEXT: vmv1r.v v10, v01268; RV32ZFH-NEXT: lui a0, %hi(.LCPI36_0)1269; RV32ZFH-NEXT: fld fa5, %lo(.LCPI36_0)(a0)1270; RV32ZFH-NEXT: vfabs.v v12, v8, v0.t1271; RV32ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1272; RV32ZFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1273; RV32ZFH-NEXT: fsrmi a0, 31274; RV32ZFH-NEXT: vmv1r.v v0, v101275; RV32ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1276; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1277; RV32ZFH-NEXT: fsrm a01278; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1279; RV32ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1280; RV32ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1281; RV32ZFH-NEXT: ret1282;1283; RV64ZFH-LABEL: vp_ceil_vv_nxv2f64:1284; RV64ZFH: # %bb.0:1285; RV64ZFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1286; RV64ZFH-NEXT: vmv1r.v v10, v01287; RV64ZFH-NEXT: vfabs.v v12, v8, v0.t1288; RV64ZFH-NEXT: li a0, 10751289; RV64ZFH-NEXT: slli a0, a0, 521290; RV64ZFH-NEXT: fmv.d.x fa5, a01291; RV64ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1292; RV64ZFH-NEXT: vmflt.vf v10, v12, fa5, v0.t1293; RV64ZFH-NEXT: fsrmi a0, 31294; RV64ZFH-NEXT: vmv1r.v v0, v101295; RV64ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, ma1296; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1297; RV64ZFH-NEXT: fsrm a01298; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1299; RV64ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1300; RV64ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1301; RV64ZFH-NEXT: ret1302 %v = call <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)1303 ret <vscale x 2 x double> %v1304}1305 1306define <vscale x 2 x double> @vp_ceil_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {1307; RV32ZFH-LABEL: vp_ceil_vv_nxv2f64_unmasked:1308; RV32ZFH: # %bb.0:1309; RV32ZFH-NEXT: lui a1, %hi(.LCPI37_0)1310; RV32ZFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)1311; RV32ZFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1312; RV32ZFH-NEXT: vfabs.v v10, v81313; RV32ZFH-NEXT: vmflt.vf v0, v10, fa51314; RV32ZFH-NEXT: fsrmi a0, 31315; RV32ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1316; RV32ZFH-NEXT: fsrm a01317; RV32ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1318; RV32ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1319; RV32ZFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1320; RV32ZFH-NEXT: ret1321;1322; RV64ZFH-LABEL: vp_ceil_vv_nxv2f64_unmasked:1323; RV64ZFH: # %bb.0:1324; RV64ZFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma1325; RV64ZFH-NEXT: vfabs.v v10, v81326; RV64ZFH-NEXT: li a0, 10751327; RV64ZFH-NEXT: slli a0, a0, 521328; RV64ZFH-NEXT: fmv.d.x fa5, a01329; RV64ZFH-NEXT: vmflt.vf v0, v10, fa51330; RV64ZFH-NEXT: fsrmi a0, 31331; RV64ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t1332; RV64ZFH-NEXT: fsrm a01333; RV64ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t1334; RV64ZFH-NEXT: vsetvli zero, zero, e64, m2, ta, mu1335; RV64ZFH-NEXT: vfsgnj.vv v8, v10, v8, v0.t1336; RV64ZFH-NEXT: ret1337 %v = call <vscale x 2 x double> @llvm.vp.ceil.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)1338 ret <vscale x 2 x double> %v1339}1340 1341define <vscale x 4 x double> @vp_ceil_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1342; RV32ZFH-LABEL: vp_ceil_vv_nxv4f64:1343; RV32ZFH: # %bb.0:1344; RV32ZFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1345; RV32ZFH-NEXT: vmv1r.v v12, v01346; RV32ZFH-NEXT: lui a0, %hi(.LCPI38_0)1347; RV32ZFH-NEXT: fld fa5, %lo(.LCPI38_0)(a0)1348; RV32ZFH-NEXT: vfabs.v v16, v8, v0.t1349; RV32ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1350; RV32ZFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1351; RV32ZFH-NEXT: fsrmi a0, 31352; RV32ZFH-NEXT: vmv1r.v v0, v121353; RV32ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1354; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1355; RV32ZFH-NEXT: fsrm a01356; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1357; RV32ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1358; RV32ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1359; RV32ZFH-NEXT: ret1360;1361; RV64ZFH-LABEL: vp_ceil_vv_nxv4f64:1362; RV64ZFH: # %bb.0:1363; RV64ZFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1364; RV64ZFH-NEXT: vmv1r.v v12, v01365; RV64ZFH-NEXT: vfabs.v v16, v8, v0.t1366; RV64ZFH-NEXT: li a0, 10751367; RV64ZFH-NEXT: slli a0, a0, 521368; RV64ZFH-NEXT: fmv.d.x fa5, a01369; RV64ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1370; RV64ZFH-NEXT: vmflt.vf v12, v16, fa5, v0.t1371; RV64ZFH-NEXT: fsrmi a0, 31372; RV64ZFH-NEXT: vmv1r.v v0, v121373; RV64ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, ma1374; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1375; RV64ZFH-NEXT: fsrm a01376; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1377; RV64ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1378; RV64ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1379; RV64ZFH-NEXT: ret1380 %v = call <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)1381 ret <vscale x 4 x double> %v1382}1383 1384define <vscale x 4 x double> @vp_ceil_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {1385; RV32ZFH-LABEL: vp_ceil_vv_nxv4f64_unmasked:1386; RV32ZFH: # %bb.0:1387; RV32ZFH-NEXT: lui a1, %hi(.LCPI39_0)1388; RV32ZFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)1389; RV32ZFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1390; RV32ZFH-NEXT: vfabs.v v12, v81391; RV32ZFH-NEXT: vmflt.vf v0, v12, fa51392; RV32ZFH-NEXT: fsrmi a0, 31393; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1394; RV32ZFH-NEXT: fsrm a01395; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1396; RV32ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1397; RV32ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1398; RV32ZFH-NEXT: ret1399;1400; RV64ZFH-LABEL: vp_ceil_vv_nxv4f64_unmasked:1401; RV64ZFH: # %bb.0:1402; RV64ZFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma1403; RV64ZFH-NEXT: vfabs.v v12, v81404; RV64ZFH-NEXT: li a0, 10751405; RV64ZFH-NEXT: slli a0, a0, 521406; RV64ZFH-NEXT: fmv.d.x fa5, a01407; RV64ZFH-NEXT: vmflt.vf v0, v12, fa51408; RV64ZFH-NEXT: fsrmi a0, 31409; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t1410; RV64ZFH-NEXT: fsrm a01411; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t1412; RV64ZFH-NEXT: vsetvli zero, zero, e64, m4, ta, mu1413; RV64ZFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t1414; RV64ZFH-NEXT: ret1415 %v = call <vscale x 4 x double> @llvm.vp.ceil.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)1416 ret <vscale x 4 x double> %v1417}1418 1419define <vscale x 7 x double> @vp_ceil_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {1420; RV32ZFH-LABEL: vp_ceil_vv_nxv7f64:1421; RV32ZFH: # %bb.0:1422; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1423; RV32ZFH-NEXT: vmv1r.v v16, v01424; RV32ZFH-NEXT: lui a0, %hi(.LCPI40_0)1425; RV32ZFH-NEXT: fld fa5, %lo(.LCPI40_0)(a0)1426; RV32ZFH-NEXT: vfabs.v v24, v8, v0.t1427; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1428; RV32ZFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1429; RV32ZFH-NEXT: fsrmi a0, 31430; RV32ZFH-NEXT: vmv1r.v v0, v161431; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1432; RV32ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1433; RV32ZFH-NEXT: fsrm a01434; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1435; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1436; RV32ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1437; RV32ZFH-NEXT: ret1438;1439; RV64ZFH-LABEL: vp_ceil_vv_nxv7f64:1440; RV64ZFH: # %bb.0:1441; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1442; RV64ZFH-NEXT: vmv1r.v v16, v01443; RV64ZFH-NEXT: vfabs.v v24, v8, v0.t1444; RV64ZFH-NEXT: li a0, 10751445; RV64ZFH-NEXT: slli a0, a0, 521446; RV64ZFH-NEXT: fmv.d.x fa5, a01447; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1448; RV64ZFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1449; RV64ZFH-NEXT: fsrmi a0, 31450; RV64ZFH-NEXT: vmv1r.v v0, v161451; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1452; RV64ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1453; RV64ZFH-NEXT: fsrm a01454; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1455; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1456; RV64ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1457; RV64ZFH-NEXT: ret1458 %v = call <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)1459 ret <vscale x 7 x double> %v1460}1461 1462define <vscale x 7 x double> @vp_ceil_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {1463; RV32ZFH-LABEL: vp_ceil_vv_nxv7f64_unmasked:1464; RV32ZFH: # %bb.0:1465; RV32ZFH-NEXT: lui a1, %hi(.LCPI41_0)1466; RV32ZFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)1467; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1468; RV32ZFH-NEXT: vfabs.v v16, v81469; RV32ZFH-NEXT: vmflt.vf v0, v16, fa51470; RV32ZFH-NEXT: fsrmi a0, 31471; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1472; RV32ZFH-NEXT: fsrm a01473; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1474; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1475; RV32ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1476; RV32ZFH-NEXT: ret1477;1478; RV64ZFH-LABEL: vp_ceil_vv_nxv7f64_unmasked:1479; RV64ZFH: # %bb.0:1480; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1481; RV64ZFH-NEXT: vfabs.v v16, v81482; RV64ZFH-NEXT: li a0, 10751483; RV64ZFH-NEXT: slli a0, a0, 521484; RV64ZFH-NEXT: fmv.d.x fa5, a01485; RV64ZFH-NEXT: vmflt.vf v0, v16, fa51486; RV64ZFH-NEXT: fsrmi a0, 31487; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1488; RV64ZFH-NEXT: fsrm a01489; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1490; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1491; RV64ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1492; RV64ZFH-NEXT: ret1493 %v = call <vscale x 7 x double> @llvm.vp.ceil.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)1494 ret <vscale x 7 x double> %v1495}1496 1497define <vscale x 8 x double> @vp_ceil_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1498; RV32ZFH-LABEL: vp_ceil_vv_nxv8f64:1499; RV32ZFH: # %bb.0:1500; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1501; RV32ZFH-NEXT: vmv1r.v v16, v01502; RV32ZFH-NEXT: lui a0, %hi(.LCPI42_0)1503; RV32ZFH-NEXT: fld fa5, %lo(.LCPI42_0)(a0)1504; RV32ZFH-NEXT: vfabs.v v24, v8, v0.t1505; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1506; RV32ZFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1507; RV32ZFH-NEXT: fsrmi a0, 31508; RV32ZFH-NEXT: vmv1r.v v0, v161509; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1510; RV32ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1511; RV32ZFH-NEXT: fsrm a01512; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1513; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1514; RV32ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1515; RV32ZFH-NEXT: ret1516;1517; RV64ZFH-LABEL: vp_ceil_vv_nxv8f64:1518; RV64ZFH: # %bb.0:1519; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1520; RV64ZFH-NEXT: vmv1r.v v16, v01521; RV64ZFH-NEXT: vfabs.v v24, v8, v0.t1522; RV64ZFH-NEXT: li a0, 10751523; RV64ZFH-NEXT: slli a0, a0, 521524; RV64ZFH-NEXT: fmv.d.x fa5, a01525; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1526; RV64ZFH-NEXT: vmflt.vf v16, v24, fa5, v0.t1527; RV64ZFH-NEXT: fsrmi a0, 31528; RV64ZFH-NEXT: vmv1r.v v0, v161529; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1530; RV64ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1531; RV64ZFH-NEXT: fsrm a01532; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1533; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1534; RV64ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1535; RV64ZFH-NEXT: ret1536 %v = call <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)1537 ret <vscale x 8 x double> %v1538}1539 1540define <vscale x 8 x double> @vp_ceil_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {1541; RV32ZFH-LABEL: vp_ceil_vv_nxv8f64_unmasked:1542; RV32ZFH: # %bb.0:1543; RV32ZFH-NEXT: lui a1, %hi(.LCPI43_0)1544; RV32ZFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)1545; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1546; RV32ZFH-NEXT: vfabs.v v16, v81547; RV32ZFH-NEXT: vmflt.vf v0, v16, fa51548; RV32ZFH-NEXT: fsrmi a0, 31549; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1550; RV32ZFH-NEXT: fsrm a01551; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1552; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1553; RV32ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1554; RV32ZFH-NEXT: ret1555;1556; RV64ZFH-LABEL: vp_ceil_vv_nxv8f64_unmasked:1557; RV64ZFH: # %bb.0:1558; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1559; RV64ZFH-NEXT: vfabs.v v16, v81560; RV64ZFH-NEXT: li a0, 10751561; RV64ZFH-NEXT: slli a0, a0, 521562; RV64ZFH-NEXT: fmv.d.x fa5, a01563; RV64ZFH-NEXT: vmflt.vf v0, v16, fa51564; RV64ZFH-NEXT: fsrmi a0, 31565; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t1566; RV64ZFH-NEXT: fsrm a01567; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t1568; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1569; RV64ZFH-NEXT: vfsgnj.vv v8, v16, v8, v0.t1570; RV64ZFH-NEXT: ret1571 %v = call <vscale x 8 x double> @llvm.vp.ceil.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)1572 ret <vscale x 8 x double> %v1573}1574 1575; Test splitting.1576 1577define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1578; RV32ZFH-LABEL: vp_ceil_vv_nxv16f64:1579; RV32ZFH: # %bb.0:1580; RV32ZFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1581; RV32ZFH-NEXT: vmv1r.v v7, v01582; RV32ZFH-NEXT: csrr a1, vlenb1583; RV32ZFH-NEXT: lui a2, %hi(.LCPI44_0)1584; RV32ZFH-NEXT: srli a3, a1, 31585; RV32ZFH-NEXT: fld fa5, %lo(.LCPI44_0)(a2)1586; RV32ZFH-NEXT: sub a2, a0, a11587; RV32ZFH-NEXT: vslidedown.vx v6, v0, a31588; RV32ZFH-NEXT: sltu a3, a0, a21589; RV32ZFH-NEXT: addi a3, a3, -11590; RV32ZFH-NEXT: and a2, a3, a21591; RV32ZFH-NEXT: vmv1r.v v0, v61592; RV32ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1593; RV32ZFH-NEXT: vfabs.v v24, v16, v0.t1594; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1595; RV32ZFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1596; RV32ZFH-NEXT: fsrmi a2, 31597; RV32ZFH-NEXT: vmv1r.v v0, v61598; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1599; RV32ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1600; RV32ZFH-NEXT: fsrm a21601; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1602; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1603; RV32ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1604; RV32ZFH-NEXT: bltu a0, a1, .LBB44_21605; RV32ZFH-NEXT: # %bb.1:1606; RV32ZFH-NEXT: mv a0, a11607; RV32ZFH-NEXT: .LBB44_2:1608; RV32ZFH-NEXT: vmv1r.v v0, v71609; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1610; RV32ZFH-NEXT: vfabs.v v24, v8, v0.t1611; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1612; RV32ZFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1613; RV32ZFH-NEXT: fsrmi a0, 31614; RV32ZFH-NEXT: vmv1r.v v0, v71615; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1616; RV32ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1617; RV32ZFH-NEXT: fsrm a01618; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1619; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1620; RV32ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1621; RV32ZFH-NEXT: ret1622;1623; RV64ZFH-LABEL: vp_ceil_vv_nxv16f64:1624; RV64ZFH: # %bb.0:1625; RV64ZFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1626; RV64ZFH-NEXT: vmv1r.v v7, v01627; RV64ZFH-NEXT: csrr a1, vlenb1628; RV64ZFH-NEXT: li a2, 10751629; RV64ZFH-NEXT: srli a3, a1, 31630; RV64ZFH-NEXT: vslidedown.vx v6, v0, a31631; RV64ZFH-NEXT: sub a3, a0, a11632; RV64ZFH-NEXT: slli a2, a2, 521633; RV64ZFH-NEXT: fmv.d.x fa5, a21634; RV64ZFH-NEXT: sltu a2, a0, a31635; RV64ZFH-NEXT: addi a2, a2, -11636; RV64ZFH-NEXT: and a2, a2, a31637; RV64ZFH-NEXT: vmv1r.v v0, v61638; RV64ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1639; RV64ZFH-NEXT: vfabs.v v24, v16, v0.t1640; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1641; RV64ZFH-NEXT: vmflt.vf v6, v24, fa5, v0.t1642; RV64ZFH-NEXT: fsrmi a2, 31643; RV64ZFH-NEXT: vmv1r.v v0, v61644; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1645; RV64ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1646; RV64ZFH-NEXT: fsrm a21647; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1648; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1649; RV64ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1650; RV64ZFH-NEXT: bltu a0, a1, .LBB44_21651; RV64ZFH-NEXT: # %bb.1:1652; RV64ZFH-NEXT: mv a0, a11653; RV64ZFH-NEXT: .LBB44_2:1654; RV64ZFH-NEXT: vmv1r.v v0, v71655; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1656; RV64ZFH-NEXT: vfabs.v v24, v8, v0.t1657; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1658; RV64ZFH-NEXT: vmflt.vf v7, v24, fa5, v0.t1659; RV64ZFH-NEXT: fsrmi a0, 31660; RV64ZFH-NEXT: vmv1r.v v0, v71661; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma1662; RV64ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1663; RV64ZFH-NEXT: fsrm a01664; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1665; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1666; RV64ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1667; RV64ZFH-NEXT: ret1668 %v = call <vscale x 16 x double> @llvm.vp.ceil.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)1669 ret <vscale x 16 x double> %v1670}1671 1672define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {1673; RV32ZFH-LABEL: vp_ceil_vv_nxv16f64_unmasked:1674; RV32ZFH: # %bb.0:1675; RV32ZFH-NEXT: csrr a1, vlenb1676; RV32ZFH-NEXT: lui a2, %hi(.LCPI45_0)1677; RV32ZFH-NEXT: sub a3, a0, a11678; RV32ZFH-NEXT: fld fa5, %lo(.LCPI45_0)(a2)1679; RV32ZFH-NEXT: sltu a2, a0, a31680; RV32ZFH-NEXT: addi a2, a2, -11681; RV32ZFH-NEXT: and a2, a2, a31682; RV32ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1683; RV32ZFH-NEXT: vfabs.v v24, v161684; RV32ZFH-NEXT: vmflt.vf v0, v24, fa51685; RV32ZFH-NEXT: fsrmi a2, 31686; RV32ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1687; RV32ZFH-NEXT: fsrm a21688; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1689; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1690; RV32ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1691; RV32ZFH-NEXT: bltu a0, a1, .LBB45_21692; RV32ZFH-NEXT: # %bb.1:1693; RV32ZFH-NEXT: mv a0, a11694; RV32ZFH-NEXT: .LBB45_2:1695; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1696; RV32ZFH-NEXT: vfabs.v v24, v81697; RV32ZFH-NEXT: vmflt.vf v0, v24, fa51698; RV32ZFH-NEXT: fsrmi a0, 31699; RV32ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1700; RV32ZFH-NEXT: fsrm a01701; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1702; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1703; RV32ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1704; RV32ZFH-NEXT: ret1705;1706; RV64ZFH-LABEL: vp_ceil_vv_nxv16f64_unmasked:1707; RV64ZFH: # %bb.0:1708; RV64ZFH-NEXT: csrr a1, vlenb1709; RV64ZFH-NEXT: li a2, 10751710; RV64ZFH-NEXT: sub a3, a0, a11711; RV64ZFH-NEXT: slli a2, a2, 521712; RV64ZFH-NEXT: fmv.d.x fa5, a21713; RV64ZFH-NEXT: sltu a2, a0, a31714; RV64ZFH-NEXT: addi a2, a2, -11715; RV64ZFH-NEXT: and a2, a2, a31716; RV64ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma1717; RV64ZFH-NEXT: vfabs.v v24, v161718; RV64ZFH-NEXT: vmflt.vf v0, v24, fa51719; RV64ZFH-NEXT: fsrmi a2, 31720; RV64ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t1721; RV64ZFH-NEXT: fsrm a21722; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1723; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1724; RV64ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t1725; RV64ZFH-NEXT: bltu a0, a1, .LBB45_21726; RV64ZFH-NEXT: # %bb.1:1727; RV64ZFH-NEXT: mv a0, a11728; RV64ZFH-NEXT: .LBB45_2:1729; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma1730; RV64ZFH-NEXT: vfabs.v v24, v81731; RV64ZFH-NEXT: vmflt.vf v0, v24, fa51732; RV64ZFH-NEXT: fsrmi a0, 31733; RV64ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t1734; RV64ZFH-NEXT: fsrm a01735; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t1736; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu1737; RV64ZFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t1738; RV64ZFH-NEXT: ret1739 %v = call <vscale x 16 x double> @llvm.vp.ceil.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)1740 ret <vscale x 16 x double> %v1741}1742