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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zbb | FileCheck %s --check-prefixes=CHECK,V3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zbb | FileCheck %s --check-prefixes=CHECK,V4; RUN: llc < %s -mtriple=riscv64 -mattr=+zve32x,+zvl128b,+zbb | FileCheck %s --check-prefixes=CHECK,ZVE5 6define i32 @test_v2i1(<2 x i1> %x) {7; V-LABEL: test_v2i1:8; V: # %bb.0:9; V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma10; V-NEXT: vcpop.m a0, v011; V-NEXT: ret12;13; ZVE-LABEL: test_v2i1:14; ZVE: # %bb.0:15; ZVE-NEXT: vsetivli zero, 2, e8, mf4, ta, ma16; ZVE-NEXT: vcpop.m a0, v017; ZVE-NEXT: ret18 %a = zext <2 x i1> %x to <2 x i32>19 %b = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a)20 ret i32 %b21}22 23define i32 @test_v4i1(<4 x i1> %x) {24; CHECK-LABEL: test_v4i1:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma27; CHECK-NEXT: vcpop.m a0, v028; CHECK-NEXT: ret29 %a = zext <4 x i1> %x to <4 x i32>30 %b = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)31 ret i32 %b32}33 34define i32 @test_v8i1(<8 x i1> %x) {35; CHECK-LABEL: test_v8i1:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma38; CHECK-NEXT: vcpop.m a0, v039; CHECK-NEXT: ret40 %a = zext <8 x i1> %x to <8 x i32>41 %b = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)42 ret i32 %b43}44 45define i32 @test_v16i1(<16 x i1> %x) {46; CHECK-LABEL: test_v16i1:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma49; CHECK-NEXT: vcpop.m a0, v050; CHECK-NEXT: ret51 %a = zext <16 x i1> %x to <16 x i32>52 %b = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)53 ret i32 %b54}55 56define i32 @test_v32i1(<32 x i1> %x) {57; CHECK-LABEL: test_v32i1:58; CHECK: # %bb.0:59; CHECK-NEXT: li a0, 3260; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma61; CHECK-NEXT: vcpop.m a0, v062; CHECK-NEXT: ret63 %a = zext <32 x i1> %x to <32 x i32>64 %b = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %a)65 ret i32 %b66}67 68define i32 @test_v64i1(<64 x i1> %x) {69; CHECK-LABEL: test_v64i1:70; CHECK: # %bb.0:71; CHECK-NEXT: li a0, 6472; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma73; CHECK-NEXT: vcpop.m a0, v074; CHECK-NEXT: ret75 %a = zext <64 x i1> %x to <64 x i32>76 %b = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %a)77 ret i32 %b78}79 80define i32 @test_v128i1(<128 x i1> %x) {81; CHECK-LABEL: test_v128i1:82; CHECK: # %bb.0:83; CHECK-NEXT: li a0, 12884; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma85; CHECK-NEXT: vcpop.m a0, v086; CHECK-NEXT: ret87 %a = zext <128 x i1> %x to <128 x i32>88 %b = call i32 @llvm.vector.reduce.add.v128i32(<128 x i32> %a)89 ret i32 %b90}91 92define i32 @test_v256i1(<256 x i1> %x) {93; CHECK-LABEL: test_v256i1:94; CHECK: # %bb.0:95; CHECK-NEXT: addi sp, sp, -1696; CHECK-NEXT: .cfi_def_cfa_offset 1697; CHECK-NEXT: csrr a0, vlenb98; CHECK-NEXT: slli a0, a0, 499; CHECK-NEXT: sub sp, sp, a0100; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb101; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma102; CHECK-NEXT: vmv1r.v v7, v8103; CHECK-NEXT: vmv1r.v v6, v0104; CHECK-NEXT: li a0, 32105; CHECK-NEXT: vslidedown.vi v5, v8, 8106; CHECK-NEXT: vslidedown.vi v4, v0, 8107; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma108; CHECK-NEXT: vslidedown.vi v0, v5, 4109; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma110; CHECK-NEXT: vmv.v.i v16, 0111; CHECK-NEXT: vmerge.vim v8, v16, 1, v0112; CHECK-NEXT: csrr a1, vlenb113; CHECK-NEXT: slli a1, a1, 3114; CHECK-NEXT: add a1, sp, a1115; CHECK-NEXT: addi a1, a1, 16116; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill117; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma118; CHECK-NEXT: vslidedown.vi v0, v4, 4119; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma120; CHECK-NEXT: vmerge.vim v8, v16, 1, v0121; CHECK-NEXT: addi a1, sp, 16122; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill123; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma124; CHECK-NEXT: vslidedown.vi v0, v7, 4125; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma126; CHECK-NEXT: vmerge.vim v8, v16, 1, v0127; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma128; CHECK-NEXT: vslidedown.vi v0, v6, 4129; CHECK-NEXT: csrr a1, vlenb130; CHECK-NEXT: slli a1, a1, 3131; CHECK-NEXT: add a1, sp, a1132; CHECK-NEXT: addi a1, a1, 16133; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload134; CHECK-NEXT: addi a1, sp, 16135; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload136; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma137; CHECK-NEXT: vadd.vv v16, v16, v24138; CHECK-NEXT: csrr a0, vlenb139; CHECK-NEXT: slli a0, a0, 3140; CHECK-NEXT: add a0, sp, a0141; CHECK-NEXT: addi a0, a0, 16142; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill143; CHECK-NEXT: vmv.v.i v16, 0144; CHECK-NEXT: vmerge.vim v24, v16, 1, v0145; CHECK-NEXT: vadd.vv v8, v24, v8146; CHECK-NEXT: addi a0, sp, 16147; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill148; CHECK-NEXT: vmv1r.v v0, v5149; CHECK-NEXT: vmerge.vim v8, v16, 1, v0150; CHECK-NEXT: vmv1r.v v0, v4151; CHECK-NEXT: vmerge.vim v24, v16, 1, v0152; CHECK-NEXT: vadd.vv v8, v24, v8153; CHECK-NEXT: vmv1r.v v0, v7154; CHECK-NEXT: vmerge.vim v24, v16, 1, v0155; CHECK-NEXT: vmv1r.v v0, v6156; CHECK-NEXT: vmerge.vim v16, v16, 1, v0157; CHECK-NEXT: vadd.vv v16, v16, v24158; CHECK-NEXT: csrr a0, vlenb159; CHECK-NEXT: slli a0, a0, 3160; CHECK-NEXT: add a0, sp, a0161; CHECK-NEXT: addi a0, a0, 16162; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload163; CHECK-NEXT: addi a0, sp, 16164; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload165; CHECK-NEXT: vadd.vv v24, v0, v24166; CHECK-NEXT: vadd.vv v8, v16, v8167; CHECK-NEXT: vadd.vv v8, v8, v24168; CHECK-NEXT: vmv.s.x v16, zero169; CHECK-NEXT: vredsum.vs v8, v8, v16170; CHECK-NEXT: vmv.x.s a0, v8171; CHECK-NEXT: csrr a1, vlenb172; CHECK-NEXT: slli a1, a1, 4173; CHECK-NEXT: add sp, sp, a1174; CHECK-NEXT: .cfi_def_cfa sp, 16175; CHECK-NEXT: addi sp, sp, 16176; CHECK-NEXT: .cfi_def_cfa_offset 0177; CHECK-NEXT: ret178 %a = zext <256 x i1> %x to <256 x i32>179 %b = call i32 @llvm.vector.reduce.add.v256i32(<256 x i32> %a)180 ret i32 %b181}182 183; FIXME: Optimize this case with Zve32x. We have to use mf4 and set the VL to184; VLEN/64.185define i32 @test_nxv1i1(<vscale x 1 x i1> %x) {186; V-LABEL: test_nxv1i1:187; V: # %bb.0: # %entry188; V-NEXT: vsetvli a0, zero, e8, mf8, ta, ma189; V-NEXT: vcpop.m a0, v0190; V-NEXT: ret191;192; ZVE-LABEL: test_nxv1i1:193; ZVE: # %bb.0: # %entry194; ZVE-NEXT: vsetvli a0, zero, e32, m1, ta, ma195; ZVE-NEXT: vmv.v.i v8, 0196; ZVE-NEXT: csrr a0, vlenb197; ZVE-NEXT: srli a0, a0, 3198; ZVE-NEXT: vsetvli zero, a0, e32, m1, ta, ma199; ZVE-NEXT: vmerge.vim v8, v8, 1, v0200; ZVE-NEXT: vsetivli zero, 1, e32, m1, ta, ma201; ZVE-NEXT: vmv.s.x v9, zero202; ZVE-NEXT: vsetvli zero, a0, e32, m1, ta, ma203; ZVE-NEXT: vredsum.vs v9, v8, v9204; ZVE-NEXT: vmv.x.s a0, v9205; ZVE-NEXT: ret206entry:207 %a = zext <vscale x 1 x i1> %x to <vscale x 1 x i32>208 %b = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %a)209 ret i32 %b210}211 212define i32 @test_nxv2i1(<vscale x 2 x i1> %x) {213; CHECK-LABEL: test_nxv2i1:214; CHECK: # %bb.0: # %entry215; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma216; CHECK-NEXT: vcpop.m a0, v0217; CHECK-NEXT: ret218entry:219 %a = zext <vscale x 2 x i1> %x to <vscale x 2 x i32>220 %b = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %a)221 ret i32 %b222}223 224define i32 @test_nxv4i1(<vscale x 4 x i1> %x) {225; CHECK-LABEL: test_nxv4i1:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma228; CHECK-NEXT: vcpop.m a0, v0229; CHECK-NEXT: ret230entry:231 %a = zext <vscale x 4 x i1> %x to <vscale x 4 x i32>232 %b = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %a)233 ret i32 %b234}235 236define i32 @test_nxv8i1(<vscale x 8 x i1> %x) {237; CHECK-LABEL: test_nxv8i1:238; CHECK: # %bb.0: # %entry239; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma240; CHECK-NEXT: vcpop.m a0, v0241; CHECK-NEXT: ret242entry:243 %a = zext <vscale x 8 x i1> %x to <vscale x 8 x i32>244 %b = call i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32> %a)245 ret i32 %b246}247 248define i32 @test_nxv16i1(<vscale x 16 x i1> %x) {249; CHECK-LABEL: test_nxv16i1:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma252; CHECK-NEXT: vcpop.m a0, v0253; CHECK-NEXT: ret254entry:255 %a = zext <vscale x 16 x i1> %x to <vscale x 16 x i32>256 %b = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %a)257 ret i32 %b258}259 260define i32 @test_nxv32i1(<vscale x 32 x i1> %x) {261; CHECK-LABEL: test_nxv32i1:262; CHECK: # %bb.0: # %entry263; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma264; CHECK-NEXT: vcpop.m a0, v0265; CHECK-NEXT: ret266entry:267 %a = zext <vscale x 32 x i1> %x to <vscale x 32 x i32>268 %b = call i32 @llvm.vector.reduce.add.nxv32i32(<vscale x 32 x i32> %a)269 ret i32 %b270}271 272define i32 @test_nxv64i1(<vscale x 64 x i1> %x) {273; CHECK-LABEL: test_nxv64i1:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma276; CHECK-NEXT: vcpop.m a0, v0277; CHECK-NEXT: ret278entry:279 %a = zext <vscale x 64 x i1> %x to <vscale x 64 x i32>280 %b = call i32 @llvm.vector.reduce.add.nxv64i32(<vscale x 64 x i32> %a)281 ret i32 %b282}283 284define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {285; CHECK-LABEL: test_nxv128i1:286; CHECK: # %bb.0: # %entry287; CHECK-NEXT: addi sp, sp, -16288; CHECK-NEXT: .cfi_def_cfa_offset 16289; CHECK-NEXT: csrr a0, vlenb290; CHECK-NEXT: slli a0, a0, 3291; CHECK-NEXT: sub sp, sp, a0292; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb293; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma294; CHECK-NEXT: vmv1r.v v7, v8295; CHECK-NEXT: vmv1r.v v6, v0296; CHECK-NEXT: vmv.v.i v16, 0297; CHECK-NEXT: csrr a0, vlenb298; CHECK-NEXT: vmerge.vim v8, v16, 1, v0299; CHECK-NEXT: addi a1, sp, 16300; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill301; CHECK-NEXT: srli a1, a0, 1302; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma303; CHECK-NEXT: vslidedown.vx v0, v0, a1304; CHECK-NEXT: srli a0, a0, 2305; CHECK-NEXT: vmv8r.v v8, v16306; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma307; CHECK-NEXT: vmerge.vim v24, v16, 1, v0308; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma309; CHECK-NEXT: vslidedown.vx v0, v0, a0310; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma311; CHECK-NEXT: vmerge.vim v16, v16, 1, v0312; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma313; CHECK-NEXT: vslidedown.vx v0, v6, a0314; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma315; CHECK-NEXT: vslidedown.vx v6, v7, a1316; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma317; CHECK-NEXT: vmerge.vim v8, v8, 1, v0318; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma319; CHECK-NEXT: vslidedown.vx v0, v7, a0320; CHECK-NEXT: vslidedown.vx v5, v6, a0321; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu322; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t323; CHECK-NEXT: vmv1r.v v0, v5324; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t325; CHECK-NEXT: vadd.vv v8, v8, v16326; CHECK-NEXT: vmv1r.v v0, v6327; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t328; CHECK-NEXT: vmv1r.v v0, v7329; CHECK-NEXT: addi a0, sp, 16330; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload331; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t332; CHECK-NEXT: vadd.vv v16, v16, v24333; CHECK-NEXT: vadd.vv v8, v16, v8334; CHECK-NEXT: vmv.s.x v16, zero335; CHECK-NEXT: vredsum.vs v8, v8, v16336; CHECK-NEXT: vmv.x.s a0, v8337; CHECK-NEXT: csrr a1, vlenb338; CHECK-NEXT: slli a1, a1, 3339; CHECK-NEXT: add sp, sp, a1340; CHECK-NEXT: .cfi_def_cfa sp, 16341; CHECK-NEXT: addi sp, sp, 16342; CHECK-NEXT: .cfi_def_cfa_offset 0343; CHECK-NEXT: ret344entry:345 %a = zext <vscale x 128 x i1> %x to <vscale x 128 x i32>346 %b = call i32 @llvm.vector.reduce.add.nxv128i32(<vscale x 128 x i32> %a)347 ret i32 %b348}349 350define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {351; CHECK-LABEL: test_nxv256i1:352; CHECK: # %bb.0: # %entry353; CHECK-NEXT: addi sp, sp, -16354; CHECK-NEXT: .cfi_def_cfa_offset 16355; CHECK-NEXT: csrr a0, vlenb356; CHECK-NEXT: slli a0, a0, 4357; CHECK-NEXT: mv a1, a0358; CHECK-NEXT: slli a0, a0, 1359; CHECK-NEXT: add a0, a0, a1360; CHECK-NEXT: sub sp, sp, a0361; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb362; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma363; CHECK-NEXT: vmv1r.v v6, v10364; CHECK-NEXT: vmv1r.v v7, v9365; CHECK-NEXT: vmv1r.v v5, v8366; CHECK-NEXT: vmv1r.v v4, v0367; CHECK-NEXT: vmv.v.i v16, 0368; CHECK-NEXT: csrr a1, vlenb369; CHECK-NEXT: vmerge.vim v8, v16, 1, v0370; CHECK-NEXT: csrr a0, vlenb371; CHECK-NEXT: slli a0, a0, 3372; CHECK-NEXT: mv a2, a0373; CHECK-NEXT: slli a0, a0, 2374; CHECK-NEXT: add a0, a0, a2375; CHECK-NEXT: add a0, sp, a0376; CHECK-NEXT: addi a0, a0, 16377; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill378; CHECK-NEXT: vmv1r.v v0, v5379; CHECK-NEXT: vmerge.vim v8, v16, 1, v0380; CHECK-NEXT: csrr a0, vlenb381; CHECK-NEXT: slli a0, a0, 5382; CHECK-NEXT: add a0, sp, a0383; CHECK-NEXT: addi a0, a0, 16384; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill385; CHECK-NEXT: srli a0, a1, 1386; CHECK-NEXT: srli a1, a1, 2387; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma388; CHECK-NEXT: vslidedown.vx v3, v4, a0389; CHECK-NEXT: vslidedown.vx v2, v5, a0390; CHECK-NEXT: vmv.v.v v0, v3391; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma392; CHECK-NEXT: vmerge.vim v8, v16, 1, v0393; CHECK-NEXT: csrr a2, vlenb394; CHECK-NEXT: slli a2, a2, 3395; CHECK-NEXT: mv a3, a2396; CHECK-NEXT: slli a2, a2, 1397; CHECK-NEXT: add a2, a2, a3398; CHECK-NEXT: add a2, sp, a2399; CHECK-NEXT: addi a2, a2, 16400; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill401; CHECK-NEXT: vmv1r.v v0, v2402; CHECK-NEXT: vmv8r.v v8, v16403; CHECK-NEXT: vmerge.vim v16, v16, 1, v0404; CHECK-NEXT: csrr a2, vlenb405; CHECK-NEXT: slli a2, a2, 4406; CHECK-NEXT: add a2, sp, a2407; CHECK-NEXT: addi a2, a2, 16408; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill409; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma410; CHECK-NEXT: vslidedown.vx v0, v3, a1411; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma412; CHECK-NEXT: vmerge.vim v16, v8, 1, v0413; CHECK-NEXT: csrr a2, vlenb414; CHECK-NEXT: slli a2, a2, 3415; CHECK-NEXT: add a2, sp, a2416; CHECK-NEXT: addi a2, a2, 16417; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill418; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma419; CHECK-NEXT: vslidedown.vx v0, v2, a1420; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma421; CHECK-NEXT: vmerge.vim v24, v8, 1, v0422; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma423; CHECK-NEXT: vslidedown.vx v0, v4, a1424; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma425; CHECK-NEXT: vmerge.vim v16, v8, 1, v0426; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma427; CHECK-NEXT: vslidedown.vx v0, v5, a1428; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma429; CHECK-NEXT: vmerge.vim v8, v8, 1, v0430; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma431; CHECK-NEXT: vslidedown.vx v0, v6, a1432; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu433; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t434; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma435; CHECK-NEXT: vslidedown.vx v0, v7, a1436; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu437; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t438; CHECK-NEXT: vadd.vv v8, v16, v8439; CHECK-NEXT: addi a2, sp, 16440; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill441; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma442; CHECK-NEXT: vslidedown.vx v5, v7, a0443; CHECK-NEXT: vslidedown.vx v4, v6, a0444; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma445; CHECK-NEXT: vslidedown.vx v0, v4, a1446; CHECK-NEXT: vslidedown.vx v3, v5, a1447; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu448; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t449; CHECK-NEXT: vmv1r.v v0, v3450; CHECK-NEXT: csrr a0, vlenb451; CHECK-NEXT: slli a0, a0, 3452; CHECK-NEXT: add a0, sp, a0453; CHECK-NEXT: addi a0, a0, 16454; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload455; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t456; CHECK-NEXT: vadd.vv v8, v8, v24457; CHECK-NEXT: csrr a0, vlenb458; CHECK-NEXT: slli a0, a0, 3459; CHECK-NEXT: add a0, sp, a0460; CHECK-NEXT: addi a0, a0, 16461; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill462; CHECK-NEXT: vmv1r.v v0, v4463; CHECK-NEXT: csrr a0, vlenb464; CHECK-NEXT: slli a0, a0, 4465; CHECK-NEXT: add a0, sp, a0466; CHECK-NEXT: addi a0, a0, 16467; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload468; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t469; CHECK-NEXT: vmv1r.v v0, v5470; CHECK-NEXT: csrr a0, vlenb471; CHECK-NEXT: slli a0, a0, 3472; CHECK-NEXT: mv a1, a0473; CHECK-NEXT: slli a0, a0, 1474; CHECK-NEXT: add a0, a0, a1475; CHECK-NEXT: add a0, sp, a0476; CHECK-NEXT: addi a0, a0, 16477; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload478; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t479; CHECK-NEXT: vadd.vv v16, v8, v16480; CHECK-NEXT: vmv1r.v v0, v6481; CHECK-NEXT: csrr a0, vlenb482; CHECK-NEXT: slli a0, a0, 5483; CHECK-NEXT: add a0, sp, a0484; CHECK-NEXT: addi a0, a0, 16485; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload486; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t487; CHECK-NEXT: vmv1r.v v0, v7488; CHECK-NEXT: csrr a0, vlenb489; CHECK-NEXT: slli a0, a0, 3490; CHECK-NEXT: mv a1, a0491; CHECK-NEXT: slli a0, a0, 2492; CHECK-NEXT: add a0, a0, a1493; CHECK-NEXT: add a0, sp, a0494; CHECK-NEXT: addi a0, a0, 16495; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload496; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t497; CHECK-NEXT: vadd.vv v24, v24, v8498; CHECK-NEXT: addi a0, sp, 16499; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload500; CHECK-NEXT: csrr a0, vlenb501; CHECK-NEXT: slli a0, a0, 3502; CHECK-NEXT: add a0, sp, a0503; CHECK-NEXT: addi a0, a0, 16504; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload505; CHECK-NEXT: vadd.vv v8, v8, v0506; CHECK-NEXT: vadd.vv v16, v24, v16507; CHECK-NEXT: vadd.vv v8, v16, v8508; CHECK-NEXT: vmv.s.x v16, zero509; CHECK-NEXT: vredsum.vs v8, v8, v16510; CHECK-NEXT: vmv.x.s a0, v8511; CHECK-NEXT: csrr a1, vlenb512; CHECK-NEXT: slli a1, a1, 4513; CHECK-NEXT: mv a2, a1514; CHECK-NEXT: slli a1, a1, 1515; CHECK-NEXT: add a1, a1, a2516; CHECK-NEXT: add sp, sp, a1517; CHECK-NEXT: .cfi_def_cfa sp, 16518; CHECK-NEXT: addi sp, sp, 16519; CHECK-NEXT: .cfi_def_cfa_offset 0520; CHECK-NEXT: ret521entry:522 %a = zext <vscale x 256 x i1> %x to <vscale x 256 x i32>523 %b = call i32 @llvm.vector.reduce.add.nxv256i32(<vscale x 256 x i32> %a)524 ret i32 %b525}526 527define i4 @test_narrow_v16i1(<16 x i1> %x) {528; CHECK-LABEL: test_narrow_v16i1:529; CHECK: # %bb.0: # %entry530; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma531; CHECK-NEXT: vcpop.m a0, v0532; CHECK-NEXT: ret533entry:534 %a = zext <16 x i1> %x to <16 x i4>535 %b = call i4 @llvm.vector.reduce.add.v16i4(<16 x i4> %a)536 ret i4 %b537}538 539define i16 @test_narrow_nxv64i1(<vscale x 64 x i1> %x) {540; CHECK-LABEL: test_narrow_nxv64i1:541; CHECK: # %bb.0: # %entry542; CHECK-NEXT: csrr a0, vlenb543; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma544; CHECK-NEXT: vmv.v.i v16, 0545; CHECK-NEXT: srli a0, a0, 1546; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma547; CHECK-NEXT: vslidedown.vx v8, v0, a0548; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu549; CHECK-NEXT: vmerge.vim v16, v16, 1, v0550; CHECK-NEXT: vmv1r.v v0, v8551; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t552; CHECK-NEXT: vmv.s.x v8, zero553; CHECK-NEXT: vredsum.vs v8, v16, v8554; CHECK-NEXT: vmv.x.s a0, v8555; CHECK-NEXT: ret556entry:557 %a = zext <vscale x 64 x i1> %x to <vscale x 64 x i16>558 %b = call i16 @llvm.vector.reduce.add.nxv64i16(<vscale x 64 x i16> %a)559 ret i16 %b560}561