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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s \3; RUN: --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s \5; RUN: --check-prefixes=CHECK,RV646 7; fold (add (umax X, C), -C) --> (usubsat X, C)8 9define <2 x i64> @add_umax_v2i64(<2 x i64> %a0) {10; CHECK-LABEL: add_umax_v2i64:11; CHECK: # %bb.0:12; CHECK-NEXT: li a0, 713; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma14; CHECK-NEXT: vssubu.vx v8, v8, a015; CHECK-NEXT: ret16 %v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> <i64 7, i64 7>)17 %v2 = add <2 x i64> %v1, <i64 -7, i64 -7>18 ret <2 x i64> %v219}20 21define <vscale x 2 x i64> @add_umax_nxv2i64(<vscale x 2 x i64> %a0) {22; CHECK-LABEL: add_umax_nxv2i64:23; CHECK: # %bb.0:24; CHECK-NEXT: li a0, 725; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma26; CHECK-NEXT: vssubu.vx v8, v8, a027; CHECK-NEXT: ret28 %v1 = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> splat (i64 7))29 %v2 = add <vscale x 2 x i64> %v1, splat (i64 -7)30 ret <vscale x 2 x i64> %v231}32 33; Try to find umax(a,b) - b or a - umin(a,b) patterns34; they may be converted to usubsat(a,b).35 36define <2 x i64> @sub_umax_v2i64(<2 x i64> %a0, <2 x i64> %a1) {37; CHECK-LABEL: sub_umax_v2i64:38; CHECK: # %bb.0:39; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma40; CHECK-NEXT: vssubu.vv v8, v8, v941; CHECK-NEXT: ret42 %v1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a0, <2 x i64> %a1)43 %v2 = sub <2 x i64> %v1, %a144 ret <2 x i64> %v245}46 47define <vscale x 2 x i64> @sub_umax_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {48; CHECK-LABEL: sub_umax_nxv2i64:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma51; CHECK-NEXT: vssubu.vv v8, v8, v1052; CHECK-NEXT: ret53 %v1 = call <vscale x 2 x i64> @llvm.umax.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1)54 %v2 = sub <vscale x 2 x i64> %v1, %a155 ret <vscale x 2 x i64> %v256}57 58define <2 x i64> @sub_umin_v2i64(<2 x i64> %a0, <2 x i64> %a1) {59; CHECK-LABEL: sub_umin_v2i64:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma62; CHECK-NEXT: vssubu.vv v8, v8, v963; CHECK-NEXT: ret64 %v1 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a0, <2 x i64> %a1)65 %v2 = sub <2 x i64> %a0, %v166 ret <2 x i64> %v267}68 69define <vscale x 2 x i64> @sub_umin_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {70; CHECK-LABEL: sub_umin_nxv2i64:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma73; CHECK-NEXT: vssubu.vv v8, v8, v1074; CHECK-NEXT: ret75 %v1 = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1)76 %v2 = sub <vscale x 2 x i64> %a0, %v177 ret <vscale x 2 x i64> %v278}79 80; Match VSELECTs into sub with unsigned saturation.81 82; x >= y ? x-y : 0 --> usubsat x, y83 84define <2 x i64> @vselect_sub_v2i64(<2 x i64> %a0, <2 x i64> %a1) {85; CHECK-LABEL: vselect_sub_v2i64:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma88; CHECK-NEXT: vssubu.vv v8, v8, v989; CHECK-NEXT: ret90 %cmp = icmp uge <2 x i64> %a0, %a191 %v1 = sub <2 x i64> %a0, %a192 %v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> zeroinitializer93 ret <2 x i64> %v294}95 96define <vscale x 2 x i64> @vselect_sub_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {97; CHECK-LABEL: vselect_sub_nxv2i64:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma100; CHECK-NEXT: vssubu.vv v8, v8, v10101; CHECK-NEXT: ret102 %cmp = icmp uge <vscale x 2 x i64> %a0, %a1103 %v1 = sub <vscale x 2 x i64> %a0, %a1104 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> zeroinitializer105 ret <vscale x 2 x i64> %v2106}107 108define <8 x i16> @vselect_sub_2_v8i16(<8 x i16> %x, i16 zeroext %w) nounwind {109; CHECK-LABEL: vselect_sub_2_v8i16:110; CHECK: # %bb.0: # %entry111; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma112; CHECK-NEXT: vssubu.vx v8, v8, a0113; CHECK-NEXT: ret114entry:115 %0 = insertelement <8 x i16> poison, i16 %w, i32 0116 %broadcast15 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> zeroinitializer117 %1 = icmp ult <8 x i16> %x, %broadcast15118 %2 = sub <8 x i16> %x, %broadcast15119 %res = select <8 x i1> %1, <8 x i16> zeroinitializer, <8 x i16> %2120 ret <8 x i16> %res121}122 123define <vscale x 8 x i16> @vselect_sub_2_nxv8i16(<vscale x 8 x i16> %x, i16 zeroext %w) nounwind {124; CHECK-LABEL: vselect_sub_2_nxv8i16:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma127; CHECK-NEXT: vssubu.vx v8, v8, a0128; CHECK-NEXT: ret129entry:130 %0 = insertelement <vscale x 8 x i16> poison, i16 %w, i32 0131 %broadcast15 = shufflevector <vscale x 8 x i16> %0, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer132 %1 = icmp ult <vscale x 8 x i16> %x, %broadcast15133 %2 = sub <vscale x 8 x i16> %x, %broadcast15134 %res = select <vscale x 8 x i1> %1, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %2135 ret <vscale x 8 x i16> %res136}137 138; x > y ? x-y : 0 --> usubsat x, y139; x > C-1 ? x+-C : 0 --> usubsat x, C140 141define <2 x i64> @vselect_add_const_v2i64(<2 x i64> %a0) {142; CHECK-LABEL: vselect_add_const_v2i64:143; CHECK: # %bb.0:144; CHECK-NEXT: li a0, 6145; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma146; CHECK-NEXT: vssubu.vx v8, v8, a0147; CHECK-NEXT: ret148 %v1 = add <2 x i64> %a0, <i64 -6, i64 -6>149 %cmp = icmp ugt <2 x i64> %a0, <i64 5, i64 5>150 %v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> zeroinitializer151 ret <2 x i64> %v2152}153 154define <vscale x 2 x i64> @vselect_add_const_nxv2i64(<vscale x 2 x i64> %a0) {155; CHECK-LABEL: vselect_add_const_nxv2i64:156; CHECK: # %bb.0:157; CHECK-NEXT: li a0, 6158; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma159; CHECK-NEXT: vssubu.vx v8, v8, a0160; CHECK-NEXT: ret161 %v1 = add <vscale x 2 x i64> %a0, splat (i64 -6)162 %cmp = icmp ugt <vscale x 2 x i64> %a0, splat (i64 5)163 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> zeroinitializer164 ret <vscale x 2 x i64> %v2165}166 167define <2 x i16> @vselect_add_const_signbit_v2i16(<2 x i16> %a0) {168; CHECK-LABEL: vselect_add_const_signbit_v2i16:169; CHECK: # %bb.0:170; CHECK-NEXT: lui a0, 8171; CHECK-NEXT: addi a0, a0, -1172; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma173; CHECK-NEXT: vssubu.vx v8, v8, a0174; CHECK-NEXT: ret175 %cmp = icmp ugt <2 x i16> %a0, <i16 32766, i16 32766>176 %v1 = add <2 x i16> %a0, <i16 -32767, i16 -32767>177 %v2 = select <2 x i1> %cmp, <2 x i16> %v1, <2 x i16> zeroinitializer178 ret <2 x i16> %v2179}180 181define <vscale x 2 x i16> @vselect_add_const_signbit_nxv2i16(<vscale x 2 x i16> %a0) {182; CHECK-LABEL: vselect_add_const_signbit_nxv2i16:183; CHECK: # %bb.0:184; CHECK-NEXT: lui a0, 8185; CHECK-NEXT: addi a0, a0, -1186; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma187; CHECK-NEXT: vssubu.vx v8, v8, a0188; CHECK-NEXT: ret189 %cmp = icmp ugt <vscale x 2 x i16> %a0, splat (i16 32766)190 %v1 = add <vscale x 2 x i16> %a0, splat (i16 -32767)191 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %v1, <vscale x 2 x i16> zeroinitializer192 ret <vscale x 2 x i16> %v2193}194 195; x s< 0 ? x^C : 0 --> usubsat x, C196 197define <2 x i16> @vselect_xor_const_signbit_v2i16(<2 x i16> %a0) {198; CHECK-LABEL: vselect_xor_const_signbit_v2i16:199; CHECK: # %bb.0:200; CHECK-NEXT: lui a0, 8201; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma202; CHECK-NEXT: vssubu.vx v8, v8, a0203; CHECK-NEXT: ret204 %cmp = icmp slt <2 x i16> %a0, zeroinitializer205 %v1 = xor <2 x i16> %a0, <i16 -32768, i16 -32768>206 %v2 = select <2 x i1> %cmp, <2 x i16> %v1, <2 x i16> zeroinitializer207 ret <2 x i16> %v2208}209 210define <vscale x 2 x i16> @vselect_xor_const_signbit_nxv2i16(<vscale x 2 x i16> %a0) {211; CHECK-LABEL: vselect_xor_const_signbit_nxv2i16:212; CHECK: # %bb.0:213; CHECK-NEXT: lui a0, 8214; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma215; CHECK-NEXT: vssubu.vx v8, v8, a0216; CHECK-NEXT: ret217 %cmp = icmp slt <vscale x 2 x i16> %a0, zeroinitializer218 %v1 = xor <vscale x 2 x i16> %a0, splat (i16 -32768)219 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %v1, <vscale x 2 x i16> zeroinitializer220 ret <vscale x 2 x i16> %v2221}222 223; Match VSELECTs into add with unsigned saturation.224 225; x <= x+y ? x+y : ~0 --> uaddsat x, y226; x+y >= x ? x+y : ~0 --> uaddsat x, y227 228define <2 x i64> @vselect_add_v2i64(<2 x i64> %a0, <2 x i64> %a1) {229; CHECK-LABEL: vselect_add_v2i64:230; CHECK: # %bb.0:231; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma232; CHECK-NEXT: vsaddu.vv v8, v8, v9233; CHECK-NEXT: ret234 %v1 = add <2 x i64> %a0, %a1235 %cmp = icmp ule <2 x i64> %a0, %v1236 %v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> <i64 -1, i64 -1>237 ret <2 x i64> %v2238}239 240define <vscale x 2 x i64> @vselect_add_nxv2i64(<vscale x 2 x i64> %a0, <vscale x 2 x i64> %a1) {241; CHECK-LABEL: vselect_add_nxv2i64:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma244; CHECK-NEXT: vsaddu.vv v8, v8, v10245; CHECK-NEXT: ret246 %v1 = add <vscale x 2 x i64> %a0, %a1247 %cmp = icmp ule <vscale x 2 x i64> %a0, %v1248 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> splat (i64 -1)249 ret <vscale x 2 x i64> %v2250}251 252; if the rhs is a constant we have to reverse the const canonicalization.253; x >= ~C ? x+C : ~0 --> uaddsat x, C254 255define <2 x i64> @vselect_add_const_2_v2i64(<2 x i64> %a0) {256; CHECK-LABEL: vselect_add_const_2_v2i64:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma259; CHECK-NEXT: vsaddu.vi v8, v8, 6260; CHECK-NEXT: ret261 %v1 = add <2 x i64> %a0, <i64 6, i64 6>262 %cmp = icmp ule <2 x i64> %a0, <i64 -7, i64 -7>263 %v2 = select <2 x i1> %cmp, <2 x i64> %v1, <2 x i64> <i64 -1, i64 -1>264 ret <2 x i64> %v2265}266 267define <vscale x 2 x i64> @vselect_add_const_2_nxv2i64(<vscale x 2 x i64> %a0) {268; CHECK-LABEL: vselect_add_const_2_nxv2i64:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma271; CHECK-NEXT: vsaddu.vi v8, v8, 6272; CHECK-NEXT: ret273 %v1 = add <vscale x 2 x i64> %a0, splat (i64 6)274 %cmp = icmp ule <vscale x 2 x i64> %a0, splat (i64 -7)275 %v2 = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %v1, <vscale x 2 x i64> splat (i64 -1)276 ret <vscale x 2 x i64> %v2277}278 279;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:280; RV32: {{.*}}281; RV64: {{.*}}282