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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v,+xtheadmemidx,+xtheadmempair -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix RV324; RUN: llc -mtriple=riscv64 -mattr=+v,+xtheadmemidx,+xtheadmempair -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefix RV646 7define void @test(ptr %ref_array, ptr %sad_array) {8; RV32-LABEL: test:9; RV32: # %bb.0: # %entry10; RV32-NEXT: th.lwd a2, a3, (a0), 0, 311; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma12; RV32-NEXT: vle8.v v12, (a2)13; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma14; RV32-NEXT: vzext.vf4 v8, v1215; RV32-NEXT: vmv.s.x v12, zero16; RV32-NEXT: vredsum.vs v8, v8, v1217; RV32-NEXT: vmv.x.s a0, v818; RV32-NEXT: th.swia a0, (a1), 4, 019; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma20; RV32-NEXT: vle8.v v13, (a3)21; RV32-NEXT: vmv.v.i v8, 022; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma23; RV32-NEXT: vslideup.vi v13, v8, 424; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma25; RV32-NEXT: vzext.vf4 v8, v1326; RV32-NEXT: vredsum.vs v8, v8, v1227; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma28; RV32-NEXT: vse32.v v8, (a1)29; RV32-NEXT: ret30;31; RV64-LABEL: test:32; RV64: # %bb.0: # %entry33; RV64-NEXT: th.ldd a2, a3, (a0), 0, 434; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma35; RV64-NEXT: vle8.v v12, (a2)36; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma37; RV64-NEXT: vzext.vf4 v8, v1238; RV64-NEXT: vmv.s.x v12, zero39; RV64-NEXT: vredsum.vs v8, v8, v1240; RV64-NEXT: vmv.x.s a0, v841; RV64-NEXT: th.swia a0, (a1), 4, 042; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma43; RV64-NEXT: vle8.v v13, (a3)44; RV64-NEXT: vmv.v.i v8, 045; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma46; RV64-NEXT: vslideup.vi v13, v8, 447; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma48; RV64-NEXT: vzext.vf4 v8, v1349; RV64-NEXT: vredsum.vs v8, v8, v1250; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma51; RV64-NEXT: vse32.v v8, (a1)52; RV64-NEXT: ret53entry:54 %0 = load ptr, ptr %ref_array, align 855 %1 = load <4 x i8>, ptr %0, align 156 %2 = shufflevector <4 x i8> %1, <4 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>57 %3 = zext <16 x i8> %2 to <16 x i32>58 %4 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %3)59 store i32 %4, ptr %sad_array, align 4, !tbaa !060 %arrayidx.1 = getelementptr ptr, ptr %ref_array, i64 161 %5 = load ptr, ptr %arrayidx.1, align 8, !tbaa !462 %6 = load <4 x i8>, ptr %5, align 163 %7 = shufflevector <4 x i8> %6, <4 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>64 %8 = zext <16 x i8> %7 to <16 x i32>65 %9 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %8)66 %arrayidx2.1 = getelementptr i32, ptr %sad_array, i64 167 store i32 %9, ptr %arrayidx2.1, align 468 ret void69}70 71!0 = !{!1, !1, i64 0}72!1 = !{!"int", !2, i64 0}73!2 = !{!"omnipotent char", !3, i64 0}74!3 = !{!"Simple C/C++ TBAA"}75!4 = !{!5, !5, i64 0}76!5 = !{!"any pointer", !2, i64 0}77