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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646 7define void @v4xi8_concat_vector_insert_idx0(ptr %a, ptr %b, i8 %x) {8; CHECK-LABEL: v4xi8_concat_vector_insert_idx0:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma11; CHECK-NEXT: vle8.v v8, (a0)12; CHECK-NEXT: vle8.v v9, (a1)13; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma14; CHECK-NEXT: vmv.s.x v8, a215; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma16; CHECK-NEXT: vslideup.vi v8, v9, 217; CHECK-NEXT: vse8.v v8, (a0)18; CHECK-NEXT: ret19 %v1 = load <2 x i8>, ptr %a20 %v2 = load <2 x i8>, ptr %b21 %concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>22 %ins = insertelement <4 x i8> %concat, i8 %x, i32 023 store <4 x i8> %ins, ptr %a24 ret void25}26 27define void @v4xi8_concat_vector_insert_idx1(ptr %a, ptr %b, i8 %x) {28; CHECK-LABEL: v4xi8_concat_vector_insert_idx1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma31; CHECK-NEXT: vle8.v v8, (a0)32; CHECK-NEXT: vle8.v v9, (a1)33; CHECK-NEXT: vmv.s.x v10, a234; CHECK-NEXT: vslideup.vi v8, v10, 135; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma36; CHECK-NEXT: vslideup.vi v8, v9, 237; CHECK-NEXT: vse8.v v8, (a0)38; CHECK-NEXT: ret39 %v1 = load <2 x i8>, ptr %a40 %v2 = load <2 x i8>, ptr %b41 %concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>42 %ins = insertelement <4 x i8> %concat, i8 %x, i32 143 store <4 x i8> %ins, ptr %a44 ret void45}46 47define void @v4xi8_concat_vector_insert_idx2(ptr %a, ptr %b, i8 %x) {48; CHECK-LABEL: v4xi8_concat_vector_insert_idx2:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma51; CHECK-NEXT: vle8.v v8, (a1)52; CHECK-NEXT: vle8.v v9, (a0)53; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, ma54; CHECK-NEXT: vmv.s.x v8, a255; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma56; CHECK-NEXT: vslideup.vi v9, v8, 257; CHECK-NEXT: vse8.v v9, (a0)58; CHECK-NEXT: ret59 %v1 = load <2 x i8>, ptr %a60 %v2 = load <2 x i8>, ptr %b61 %concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>62 %ins = insertelement <4 x i8> %concat, i8 %x, i32 263 store <4 x i8> %ins, ptr %a64 ret void65}66 67define void @v4xi8_concat_vector_insert_idx3(ptr %a, ptr %b, i8 %x) {68; CHECK-LABEL: v4xi8_concat_vector_insert_idx3:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma71; CHECK-NEXT: vle8.v v8, (a1)72; CHECK-NEXT: vle8.v v9, (a0)73; CHECK-NEXT: vmv.s.x v10, a274; CHECK-NEXT: vslideup.vi v8, v10, 175; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma76; CHECK-NEXT: vslideup.vi v9, v8, 277; CHECK-NEXT: vse8.v v9, (a0)78; CHECK-NEXT: ret79 %v1 = load <2 x i8>, ptr %a80 %v2 = load <2 x i8>, ptr %b81 %concat = shufflevector <2 x i8> %v1, <2 x i8> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>82 %ins = insertelement <4 x i8> %concat, i8 %x, i32 383 store <4 x i8> %ins, ptr %a84 ret void85}86 87define void @v4xi64_concat_vector_insert_idx0(ptr %a, ptr %b, i64 %x) {88; RV32-LABEL: v4xi64_concat_vector_insert_idx0:89; RV32: # %bb.0:90; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma91; RV32-NEXT: vle64.v v8, (a0)92; RV32-NEXT: vle64.v v10, (a1)93; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma94; RV32-NEXT: vslide1down.vx v8, v8, a295; RV32-NEXT: vslide1down.vx v8, v8, a396; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma97; RV32-NEXT: vslideup.vi v8, v10, 298; RV32-NEXT: vse64.v v8, (a0)99; RV32-NEXT: ret100;101; RV64-LABEL: v4xi64_concat_vector_insert_idx0:102; RV64: # %bb.0:103; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma104; RV64-NEXT: vle64.v v8, (a0)105; RV64-NEXT: vle64.v v10, (a1)106; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma107; RV64-NEXT: vmv.s.x v8, a2108; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma109; RV64-NEXT: vslideup.vi v8, v10, 2110; RV64-NEXT: vse64.v v8, (a0)111; RV64-NEXT: ret112 %v1 = load <2 x i64>, ptr %a113 %v2 = load <2 x i64>, ptr %b114 %concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>115 %ins = insertelement <4 x i64> %concat, i64 %x, i32 0116 store <4 x i64> %ins, ptr %a117 ret void118}119 120define void @v4xi64_concat_vector_insert_idx1(ptr %a, ptr %b, i64 %x) {121; RV32-LABEL: v4xi64_concat_vector_insert_idx1:122; RV32: # %bb.0:123; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma124; RV32-NEXT: vle64.v v8, (a0)125; RV32-NEXT: vle64.v v10, (a1)126; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma127; RV32-NEXT: vslide1down.vx v9, v8, a2128; RV32-NEXT: vslide1down.vx v9, v9, a3129; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma130; RV32-NEXT: vslideup.vi v8, v9, 1131; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma132; RV32-NEXT: vslideup.vi v8, v10, 2133; RV32-NEXT: vse64.v v8, (a0)134; RV32-NEXT: ret135;136; RV64-LABEL: v4xi64_concat_vector_insert_idx1:137; RV64: # %bb.0:138; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma139; RV64-NEXT: vle64.v v8, (a0)140; RV64-NEXT: vle64.v v10, (a1)141; RV64-NEXT: vmv.s.x v9, a2142; RV64-NEXT: vslideup.vi v8, v9, 1143; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma144; RV64-NEXT: vslideup.vi v8, v10, 2145; RV64-NEXT: vse64.v v8, (a0)146; RV64-NEXT: ret147 %v1 = load <2 x i64>, ptr %a148 %v2 = load <2 x i64>, ptr %b149 %concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>150 %ins = insertelement <4 x i64> %concat, i64 %x, i32 1151 store <4 x i64> %ins, ptr %a152 ret void153}154 155define void @v4xi64_concat_vector_insert_idx2(ptr %a, ptr %b, i64 %x) {156; RV32-LABEL: v4xi64_concat_vector_insert_idx2:157; RV32: # %bb.0:158; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma159; RV32-NEXT: vle64.v v8, (a1)160; RV32-NEXT: vle64.v v10, (a0)161; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, ma162; RV32-NEXT: vslide1down.vx v8, v8, a2163; RV32-NEXT: vslide1down.vx v8, v8, a3164; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma165; RV32-NEXT: vslideup.vi v10, v8, 2166; RV32-NEXT: vse64.v v10, (a0)167; RV32-NEXT: ret168;169; RV64-LABEL: v4xi64_concat_vector_insert_idx2:170; RV64: # %bb.0:171; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma172; RV64-NEXT: vle64.v v8, (a1)173; RV64-NEXT: vle64.v v10, (a0)174; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma175; RV64-NEXT: vmv.s.x v8, a2176; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma177; RV64-NEXT: vslideup.vi v10, v8, 2178; RV64-NEXT: vse64.v v10, (a0)179; RV64-NEXT: ret180 %v1 = load <2 x i64>, ptr %a181 %v2 = load <2 x i64>, ptr %b182 %concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>183 %ins = insertelement <4 x i64> %concat, i64 %x, i32 2184 store <4 x i64> %ins, ptr %a185 ret void186}187 188define void @v4xi64_concat_vector_insert_idx3(ptr %a, ptr %b, i64 %x) {189; RV32-LABEL: v4xi64_concat_vector_insert_idx3:190; RV32: # %bb.0:191; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma192; RV32-NEXT: vle64.v v8, (a1)193; RV32-NEXT: vle64.v v10, (a0)194; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma195; RV32-NEXT: vslide1down.vx v9, v8, a2196; RV32-NEXT: vslide1down.vx v9, v9, a3197; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma198; RV32-NEXT: vslideup.vi v8, v9, 1199; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma200; RV32-NEXT: vslideup.vi v10, v8, 2201; RV32-NEXT: vse64.v v10, (a0)202; RV32-NEXT: ret203;204; RV64-LABEL: v4xi64_concat_vector_insert_idx3:205; RV64: # %bb.0:206; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma207; RV64-NEXT: vle64.v v8, (a1)208; RV64-NEXT: vle64.v v10, (a0)209; RV64-NEXT: vmv.s.x v9, a2210; RV64-NEXT: vslideup.vi v8, v9, 1211; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma212; RV64-NEXT: vslideup.vi v10, v8, 2213; RV64-NEXT: vse64.v v10, (a0)214; RV64-NEXT: ret215 %v1 = load <2 x i64>, ptr %a216 %v2 = load <2 x i64>, ptr %b217 %concat = shufflevector <2 x i64> %v1, <2 x i64> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>218 %ins = insertelement <4 x i64> %concat, i64 %x, i32 3219 store <4 x i64> %ins, ptr %a220 ret void221}222