80 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefix RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefix RV646 7; This used to crash during type legalization, where lowering (v4i1 =8; BUILD_VECTOR) created a (v4i1 = SETCC v4i8) which during constant-folding9; created illegally-typed i8 nodes. Ultimately, constant-folding failed and so10; the new illegal nodes had no uses. However, during a second round of11; legalization, this same pattern was generated from another BUILD_VECTOR. This12; meant one of the illegally-typed (i8 = Constant<0>) nodes now had two dead13; uses. Because the Constant and one of the uses were from round 1, they were14; further up in the node order than the new second use, so the constant was15; visited while it wasn't "dead". At the point of visiting the constant, we16; crashed.17 18define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b, <4 x i1> %sel) {19; RV32-LABEL: constant_folding_crash:20; RV32: # %bb.0: # %entry21; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma22; RV32-NEXT: vmv1r.v v10, v023; RV32-NEXT: lw a0, 8(a0)24; RV32-NEXT: andi a0, a0, 125; RV32-NEXT: seqz a0, a026; RV32-NEXT: vmv.v.x v11, a027; RV32-NEXT: vmsne.vi v0, v11, 028; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma29; RV32-NEXT: vmerge.vvm v8, v9, v8, v030; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma31; RV32-NEXT: vmv.v.i v9, 032; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma33; RV32-NEXT: vmv.v.i v11, 1034; RV32-NEXT: vmv1r.v v0, v1035; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma36; RV32-NEXT: vmerge.vim v9, v9, 1, v037; RV32-NEXT: vrgather.vi v10, v9, 038; RV32-NEXT: vmsne.vi v0, v10, 039; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma40; RV32-NEXT: vmv.x.s a0, v841; RV32-NEXT: vse32.v v11, (a0), v0.t42; RV32-NEXT: ret43;44; RV64-LABEL: constant_folding_crash:45; RV64: # %bb.0: # %entry46; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma47; RV64-NEXT: vmv1r.v v12, v048; RV64-NEXT: ld a0, 8(a0)49; RV64-NEXT: andi a0, a0, 150; RV64-NEXT: seqz a0, a051; RV64-NEXT: vmv.v.x v13, a052; RV64-NEXT: vmsne.vi v0, v13, 053; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma54; RV64-NEXT: vmerge.vvm v8, v10, v8, v055; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma56; RV64-NEXT: vmv.v.i v9, 057; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma58; RV64-NEXT: vmv.v.i v10, 1059; RV64-NEXT: vmv1r.v v0, v1260; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma61; RV64-NEXT: vmerge.vim v9, v9, 1, v062; RV64-NEXT: vrgather.vi v11, v9, 063; RV64-NEXT: vmsne.vi v0, v11, 064; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma65; RV64-NEXT: vmv.x.s a0, v866; RV64-NEXT: vse32.v v10, (a0), v0.t67; RV64-NEXT: ret68entry:69 %sunkaddr = getelementptr i8, ptr %v54, i64 870 %v56 = load i64, ptr %sunkaddr, align 871 %trunc = and i64 %v56, 172 %cmp = icmp eq i64 %trunc, 073 %ptrs = select i1 %cmp, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b74 %v67 = extractelement <4 x ptr> %ptrs, i64 075 %mask = shufflevector <4 x i1> %sel, <4 x i1> poison, <4 x i32> zeroinitializer76 call void @llvm.masked.store.v4i32.p0(<4 x i32> <i32 10, i32 10, i32 10, i32 10>, ptr %v67, i32 16, <4 x i1> %mask)77 ret void78}79 80